CA1166773A - Automatic protection apparatus for span lines employed in high speed digital systems - Google Patents

Abstract

A.K.Edwards - 3 Abstract of the Disclosure An automatic span line switch for high speed com-munication lines is disclosed. The apparatus employs an alarm interface unit which is coupled to a service line terminal in order to detect a line failure mode Upon detection of such a mode, the system operates to modify the parity bit content of the transmitted digital signal in order to provide a unique code to be transmitted to a remote office connected to a near office and indica-tive of a span line failure. The apparatus automatically proceeds to switch the failed transmission line to a back-up protection line to enable the near location to communicate with the remote location via, the back-up line. All control signals transmitted between the loca-tions are implemented by means of unique codes which are generated by purposely modifying the parity bit content in each successive frame of the transmitted digital sig-nal. The system further describes a priority system for preferentially switching higher priority service lines when multiple failures occur. Various other techniques such as manual operation are disclosed to enable manual switching of protection lines during system operation.

Description

t I ;t ~ t; 7 7 3 ~ K ~ l;awarc~s - ~

AUTOM~TIC PROTECTION APPARATUS FOR SPAN
LINES EMPLOYED IN HIGH SPEED DIGITAL SYSTEMS
~ackgroimd o~ the Invention .
The use o automatic protestion switching in ~he fiela of telecommunication transmission'is employed as a means of ~educing the out o~ service time where signals must be transmitted over span lines, which lines include repeater amplifiers. In telephony systems, co,mmunication occurs over pulse code modulated (PCM) transmission lines which may multiplex a number o~
terminals onto a common PCM channel. Accordingly, in such'systems, communications between central of~ices occur over span lines which essentially consist o~
multiwi,re'cables' containing repeating amplifiers at intervals. The main function of such span lines is to maintain the data ~ithin acceptable amplitudesduring transmission between offices.
I~ is, of cou,rse, possible that a span line or a repsater contained in such a line exhibits a failure and hence,' the'line becom~s inoperative, Therefore, the prior art has determined that it is desirable to switch a defective span line to an operative span line in order to maintain communications. As indicated, such an interrupt~on in transmission due to outside eguipment failure or cable breakage is thus avoided by automatic transfer of the signal to a working spare line.
The prior art ha5 been cognizant of such problems and has emp7oyed systems ~hich operate to monitor the ~ ~.Edwards - 3 .. . .

2 ~
quality of the signal and to provide aukomatic transfer to a spare line upon detection of signal degradation.
Upon removal of a fault condition, the data would then be transferred back to the ori~inal line.
For an example of such prior art techniques, reference is made to U.S. Patenk 3~715,503 entitled AUTO~L~TIC TRANSFER ARRANGEMENT FOR A TELEP~IONE SYSTEM
issued in February, 1973 to Jungbluth et al.
In any event, with the increasing demand for 10 high speed operation which is attendant with high frequency of transmission, the information capacity is much greater and hence increased reliahlity is neces-sary in order to operate such systems in a reliable and e~f~cient manner. Therefore, the need for protective 15 s~itchin~ in regard to span lines becomes even more ~mportant. However, if one employs the lower frequency schemeb of the prior art, the protection apparatus - beco~es extremely expensive while consuming a great deal o~ powex. Accordinglyr it is necessary to provide 20 ~n altexnative'ap~roach for high speed operation.
In particular, a modern day system may employ, as'a transmission medium,optical fibers coupled toland which o~erate with suitable optical transmitters and receivers and which function as span lines. As a txans-25 mission medium, optical fibers have a number of unique advantages when compared with the conventional conductors.
In regard to such advantages, is the ability to provide a system with a low total cost. In implementing such systems, only one fiber is required per direction of 30 transmission. Hence, this feature makes optical fibers attractive'for use'in crowded ducts. Furthermore, term~nals and/or repeaters can be spaced at greater' ~nter~als because of the reduced signal attenuation/
de~radation in optical ~ibers. In this manner, the 35 attenuation per unit length of optical fibers allows a longer xepeater spacing than khat employed in coaxial cables'. In present day systems, such repeaters can be spaced between four to five miles or six to eight ~ 166 ~73 . -A. K,E:d-~Jardg - 3 ~, " ., -- 3 --, /b ~ '^S
~e~e-~3~ apart. In view of progress being made in present technology, the performance of such optical fibers will probably improve in the future and allow even greater spacing.
The op~ical fiber further permits reduced system cost based on its wide band width, low attenuation and the attendant reduction of cable size. Presently graded index fibers as manufactured by the Assignee herein can operate at bit rates varying from 1.544Mb/s to 44.736Mb/s. In fiber communications, there is also a ~irtual absence of crosstalk and hence, systems of various bit rates may be mixed in the same optical fibex cable. The fibers are completely immune to all foxms o~ electrostatic or electromagnetic interfer-ence and are virtually unaffected by moisture, while providing a great deal of system security.
In any event, in employing such fibers in an optimum way, one must face various problems which are associated with iber use. At the high frequencies of transmission, fiber op-tic systems typically employ single ibers as the transmission medium and a laser diode as the light source. Since it is difficult to transmit multile~el signs using laser sources, a binary s~ynal is normally sent. Unless there are error check bits built into the frame format of the signal, there is no facility for in~traffic line error monitoring and therefore the line signal frequency must be in-creased to include the extra bits f~r error detection.
It is therefore an object of the present inven-tion to provide an automatic protection switch for ~ span line employed in a high speed digital system, which s~stem may include optical fiber span lines.
It is a further object of this invention to modify the parity bit content in such a sys tem to obtain ~n-txaf~ic bit error rate monitoring and to further use those bits for bit ~rror purposes to enable control of a protection switch for a span line.

773 A,K.~dwards - 3 " .. ~ 4 -Brief Description of the Preferred Embodiment Automatic protection apparatus for a telecom-munication~ syst~m including at least one service line terminal associated with a service line and at least one protection line terminal associa-ted with a pro-tection line, with said service and protection lines extending between a near telecommunications office to a far telecommunications office for transmitting between said offices digital data indicative o~ infor-mation, with 'said data as transmitted comprising a number o~ successive data frames, wherein each frame ~as a plurality o~ data bits and at least one parity bit ~ndicative'o~ the count of said data bits being even or`odd, comprising monitoring means for sensing a failuxe'o~ sexvice line between said near and far offices, parity code inserting means coupled to said monitoring means and operative to modify said parity bit from frame to frame to indicate said failure, switching means responsive to said frames of data as modified in parity by said code inserting means ~or transferr~ng at said near and fa'r end said telecom-munications ser~ice line to said protection line upon sens~n~ said failure according to said parity bit modi~ication', and control generation means coupled to saia parity code inserting means for further modify- !
in~ said paritv bit as transmitted to enable said near a,nd far end to communicate to provide indications necessary to fully.complete said transfer.
Brief Description of the Drawings FIGURE 1 is a simple bloc~ diagram showing optical service lines protected hy a protection line according to this invention;
FIGURES 2A through 2C are a series o~ timing d;~c~rams depicting a frame format in FIG. 2A,an even parity ~rame Ln FIG. 2B~and an odd parity ~xame in FIG. 2C;
FIGURE 3 is a simple block diagram depicting an optical span line;

~ 3 A~K.Edwards ~ 3 ~ ~ . , FIGURE 4 is a block diagram depictiny a service line terminal according to this invention;
FIGURE ~ is a schematic aiagram depicting a framing algorithm to enable parity insertion according to this invention;
FIGURE 6 is a simple diagram showing input and output signals to an alarm and interface unit (AIU) according to this invention;
FIGURE 7 is an end to end simplified system blo~k diagram of an automatic protection system;
FIGURES 8 through 19 are a se-t of simplified block diagrams ~hat are useful in depicting the .timed ~e~uence of events to show the transfer o~ a faulty ser~ice line to a protection line and in particular:
FIGU~E 8 depicts a near ena service line terminal under normal traffic conditions;
~IGURE 9 depicts a near end line terminal when detectIng a major alarm condition;
FIGURE 10 depicts a near end lin~ tarminal ge~er-atin~ a transfer request;
FIG~RE 11 depicts a near end line terminal imple-me.ntin~ a firs.t step in the transfer;
FIGURE 12 depicts a near-end line terminal imple-~entin~ a second step in the transfer;
PIGVRE 13 depicts a near end line terminal imple-menting a transfer at the near end;
FIGURE 14 depicts a near end line terminal pro-ceeding with transfer at the near end;
FIGURE 15 depicts the transfer sequence which is repea-ted at the far end to provide an end to end transfer;
FIGURE 16 depicts a reset at the near end after a transfer;
FIGURE 17 depicts a completion of the reset at the near end aftex a transfer;
FXGURE 18 depicts a completed transfex at both enas and acknowledgement;
FIGURE 19 depicts the remaining step in completing a transfer between the near and far end;
Figure 20 depicts a table of e:ight bit cyclical code words which are available according to this invention;
Figure 21 is a detailed block diagram of a parity insertion circuit according to this invention;
Figure 22 is a simplified timing diagram of parity insertion as im-plemented by the circuit of Figure 21;
Figure 23 is a store and gating timing diagram and component struc-ture useful in explaining operation of the parity circuit;
Figure 24 is a simplified block diagram and timing diagram of a parity counter according to this invention;
Figure 25 is a timing diagram depicting parity bit stuffing accord-ing to this invention;
Figure 26 is a detailed block diagram depicting parity bit removal circuitry according to this invention;
Figure 27 is a timing diagram depicting a gating sequence used in parity removal;
Figure 28, appearing on the same drawing sheet as Figure 22, is a timing diagram depicting the timing relationship in parity removal; and Figure 29 is a simplified block diagram of a control bus interface (CBI) according to this invention.
Detailed Description of the Invention Referring to Figure 1, there is depicted a simplified block diagram showing the environment in which this invention operates. Figure 1 shows a number of telephone offices designated as A, B, C and D. For purposes of this example, office A which contains a multiplex terminal 10 is the near end office. Office D (20) is the far end office. The central offices A and D
are connected together via span sections 1, 2 and 3. Fach span section may comprise high speed digital transmission channels employing repeaters. As 30 indicated, the span lines employed in this system are optical fibers~ but .~;

'773 as one will ascertain, the techniques to be described for syste~ control are applicable to high speed electrical systems as well.
The multiplex terminal 10, for present purposes, generates digital electrical signals at a 44.736 Mb/s rate for transmission over optical fibers designated as 1, 2, 3 and N. There are four optical fibers depicted and hellce, four span lines, but it is understood that more or less can be em-ployed. Essentially, the optical fibers 1 to N operate to transmit the op-tical signals via the span sections through the intermediate offices B and C
and hence, to the far end office D.
The span sections which will be described in detail include neces-sary switching and control modules to monitor the signal content and quality on each line and to switch to an alternate or protective span line in the event of a signal failure. The optical signal which is transmitted via the fibers associated with the span sections is reconverted back to an electrical signal at each intermediate office location.
As shown in Figure 1, there is an X located in span section 1 asso-ciated with the level of cable 2. Another X exists in span section 3 at the level of cable 3. This nomenclature indicates a failure of a span line at that location~ which failure, for example, could have been caused by signal degradation, repeater failure and so on. As seen in Figure 1, cable 2 is routed via a protective span line in span section 1, while failed cable 3 is routed via a protection span line in span section 3. Accordingly, the trans-mission of data on cable 2 and cable 3 is not interrupted to enable the far end ofice D to receive all data as transmitted by the near end office A.
The system to be described automatically detects a span line failure and switches the data to a protection span line by monitoring the signal trans-mitted.
Thus, as seen in Figure 1, due to the failure of the second service span section between office A and the intermediate officc B, the system will operate to seize the span protection line in section 1 only, leaving the ~ 18~3 remainder of the protection line to ser-v:ice other sections. Ilence, the third service line section between intermediate office C and the far end office D
will cause the protection span line to service this failure. Hence, based on system operation, the automatic protection switch of this system seizes the backup line in one section only, allowing the rest of the protection line to serve other line sections.
In order to accomplish switching and to afford the type of protec-tion indicated in Figure 1, one has to provide a communications channel over which control information can be sent.
Referring to Figure 2A, there is shown two typical frames consist-ing of eighteen bits each. In the format depicted, the numeral P which is the eighteenth and thirty-sixth bit represents the parity bit, while numerals X represent data bits. In the system to be described, the parity bit is added every seventeen data bits and the line bit rate is increased by a fac-tor of 18/17.
Figure 2B depicts an even parity bit frame where the eighteenth bit or parity bit is zero and the thirty-sixth bit is a one.
Figure 2C depicts an odd parity frame where the eighteenth bit is a one and the thirty-sixth bit is a zero.
Referring to Figure 3, there is shown a simple block diagram of a single span line connection. The incoming electrical signal is applied to a parity insertion module 21 and then applied to an optical transmitter 22 for application to optical span line 23. At the receiving end, the optical sig-nal is received by an optical receiver 24, converted back to an electrical slgnal, and then transmitted to a parity removal circuit 25.
In Figure 3, there is also shown a receiver path for an optical span line. The data is basically applied to a parity insertion module 21R
and then applied to an optical transmitter 22R where it is directed ovcr the optical span line (shown dashed), received by an opt:ical recciver 2~R and thence, to a parity removal circuit 25R.

:
., :~,.

The configurations ot optical transrnitters and optical receivers are well known in the art. ~ssentially an optical transmitter may cornprise a laser diode capable of being pulsed on and off according to an electrical signal applied at its input. In this manner, the optical transmitter serves to produce a train of binary signals (light on and light off) analogous to binary ones or zeroes.
The optical receiver comprises a photo device at its input which receives the binary optical signal and converts ~he same to an electrical signal by the photo device responding to the intensity of light. In this manner, the parity removal circuit of both the transmit and the receive mod-ules can operate with electrical signals as will be explained in Figure 4 as can the parity insertion modules 21 and 21R.
It is noted that in actual practice, an optical span may constitute a single fiber, which fiber is unidirectional and hence, two fibers are needed for a transmit and a receive mode.
The dashed configurations of Figure 3 schematically represent ampli-fiers as a repeater amplifier which may be employed in a coaxial transmission span line. It is understood that such amplifiers as 23 and 23R are not nec-essarily included in the span line configurations according to this invention.
For examples of receivers and transmitters employed with fiber optic cables and typical circuit configurations, reference is made to the August 5, 1~76 issue of Electronics maga~ine, Vol. 49~ No. 16, published by McGraw Hill, pp 88-102.

. . . . . .... . .. . .. .
A~K~Ed~7ards -~ ~ , .
~ 1 0 --In reyard to FIG. 2, it is seen that the parity bit is always present in the line signal, but the parity bit does no-t carry any data information. Hence, this bi~ is to be used as a data channel to control S the transfer and reset sequences in an automatic pro-tection scheme.
In the configuration depicted in FIG. 4, the parity bit is inserted at a rate of 44.736 di~ided by 17 or at a rate o~ 2.63Mb/s and therefore, the frequency 10 at which the transfer control circuit has to operate is greatly reduced, while employing the already high - speed portions of the terminal equipment.
Referring to FIG. 4, there is depicted a block diagram of terminal equipment which is employed to 15 process the electrical signal in ~his system~ The terminal depicted in FIG. 4 is of relatively conven-tional design and i5 the type of terminal which will work in conjunction with the fiber protection switch of this invention.
In the system,~ incoming data at the 44.736Mb/s rate is applied to an input and output routing module 30 and then applied to a scrambler circuit 31. Scrambler circuits as 31 are well known in the art and essentially, operate to accept the data and the 44.736MHz clock 25 signal to scramble the data so that the output signal is roughly independent of the input data signal pulse ~ensity. The scrambled data enables reliable timing extraction in the optical repeaters. Examples of scrambliny circuits are well known in the art and 30 basically consist of a series of input buffer gates, a loss of signal detector and a suitablP scrambling circuit which may include a flip/flop register. The main purpose of the 5cramb1ing circuit, as indicated, is to scramble data to make the output signal roughly 35 independentof the input data signal density.
The scrambled data i5 directed to a parity insertion circuit 32 as is the 44.376MHz clock. In the parity insertion circuit, the parity bit is added ~.K.Édwards - 3 ~, , . - 1 1 eve~y seventeen data bits to force even parity on a frame to frame basis. A control line 33 is used to modify the parity bit to enable one to force odd par-ity on command. In this manner, the sys~em allows particular sequences of odd and even pari~y frames to be transmitted as part of the "handshake" between oppos-ite ends of a span line.
The output of the paxity circuit together with a 47.367MHz clock is applied to an input/output inter-face circuit 35. The data on port 36 is at a 47.367~b/s rate due to stuffing of the parity bit and together with the 47.367MHz clock on terminal 37 provides ~he input signals which are transmitted to the optical transmitter~
15 - Incoming optical data t~geth~r with incoming clock is applied to terminals 38 and 39 where ît is directed to ~â parity removal circuit 40. In ~his unit, the eignteenth bit is detected and the parity bit is removed to recover the original data sequence. Framing is performed by looking for con-secutive eighteen bit sequences which have even parity and once a suf~icient consecutive propex count has been received, an in frame condition is assumed.
A long sequence of odd parity counts will cause the receive terminal to believe that it has los-t frame.
~: using a framing algorithm (FIG. 5), i~ allows sequences of up to nine consecutive odd parity counts.
Therefore, by never exceeding this number of consecu-tive odd parity counts, the parity bit can be employed as a data channel.
The scrambled data is then applied to a descram-bler 41 which functions opposite to scrambler 31 to provide data and clock to the input/output module 30 and hence, proper data information on the output line.
It is understood that the terminal eguipment depicted in FIG. 4 is relatively conventional in format with the exception of the above explanation concerning parity insertion and removal and has been included as ~ :~66773 A.K.Edwards - 3 .

being necessary for a complete understanding of the invention. In any event, such terminals have been employed in the prior art and for example 9 see a publication entitled "Fiber Transmission System", Publication No. 650058-823-001 published by ITT o~
Raliegh, North Carolina.
Referring to FIG. 5, ~here is shown a framing algorithm in schematic ~orm to clearly indicate all possikle states of the framing circuitry. In FIG.
5, I indicates the fully in frame condition, while states 1 to 9 are reached ~y that number of consecu-tive odd parity counts. An even parity count after as many as nine odd parity counts, will se~ the state back to the in frame condition. The zero state indi-cates out of~rame and once this state is reached, ten addi~ional even parity counts must be registered to return to the in frame state. It is understoo~
that the reframe sequence is not of consequence to operation of the present invention and the framing algorithm depicted in FIG. ~ is well known, but recog-nizing the conditions of such an algorithm allows one to use the parity bit as a data channel.
In FIG. 4, there is an alarm and interface unit tAIu) 50. This unit is depicted in simple sche-matic form in FIG. 6 and the appropriate interface lines to this unit are shown. The AIU 50 will be described in greater detail subsequently, but it is necessary ~or an understanding of operation to in~icate the nature of the interface lines to this unit in order to explain system operation.
Referring to FIG. 6, the AIU unit 50 is depicted with applicable interface lines. On the high frequenc~
side of the interface~ there are shown the following control lines: ~ ~
4~ 35 Line ~ is a parity violation ~E~n line.
~31~ This is an output from the parity removal unit 40 of FIG. 4 which detects ~dd parity counts The alarm unit wiLl count these parity violations and pursuant 1 ~6773 - -A.K.Edwards-3 .
_ 13 -to such violations, sets thresholds for automatic switching and alarm conditions.
Line 52 is a divide by 18 sync signal. This si~nal is a synchronized pulse defining the eighteenth S bit frame and allows the interface unit to syncrhonize the odd parity insertions with the eighte~n bit frame.
51 inse~i Line ~3 designated as parity violations is a parity ~iolation insertion signal. Upon each positive goin~ transistion, this line will force an odd parity coun~ in that ~rame. This line is connected to ter-minal 33 of FIG~ 4 coupled ~o the pari~y insertion module 32. Hence, this line allows control o the parity bit in each frame via the AIU 50.
Line 54 designated as transfer contxol is directed to the input/output module-30 of FIG. 4 and in an automatic protection switch, will control the transfer of the data signal to the spare line.
On the low ~requency side of the interface, there is shown a con~rol line 55 designated as parity violation code and ~ line 56 designated as clock.
These two lines function to load a particular parity code violation sequence (CVSt into the interface unit.
This sequence is an eight bit sequence as will be further described.
Line 57 designated as enable operates as follows:
Once an eight bit word is loaded into the AIU 50, it can be outputted sequentially as a code violation sequence by impressing a high level on the enable line. As long as the-enable l~ne is high, it will -be cyclically repeated. If the sequences are sent repetitively, they must be cyclically unique and there-~ore~ one sequence is not a delayed version o another.
In this manner, with an eight bit word, one can obtain thirty-two unique sequences.
As will be explained, the loading and enabling of the CVS or the parity code violation se~uence is performed by the protection switch central control unit ~PSC) which will be described.

r~ 3 A.K.Edward 5- 3 .

Lead 58 is designated as paxity violations.
This lead transmits odd and even parity information to the protection swi-tch central control unit at the frame rate of 2.63MHz. The protection switch central control unit takes this information and decodes the eight bit word being received to implement any command sign~fied by that word.
Lead 59 is designated as ~ransfer request and this is activated as a resul-t of the parity rate violation threshold bei'ng excebded or by- the loss o~ frame or loss of line'signal and ser~es as a request out to the pro~ection switch central contxol unit for the trans~er to be enacted.
Lead 60 is designated as transfer control and it is a contxol line from the PSC which enables transfer to a spare span line.
Re~erring to FIG~ 7, there is shown an end to end simplified system block diagram. The terminals designated as terminals 1 throu~h N are individua,l terminal units as depicted in FIG. 4. A near end terminal unit is connected to a far end terminal unit via an associated span line.' As indicated, the span lines may be 'optical span lines. Thus, as shown in FI~7 7, near terminal 1 is connected to far terminal 1 v~a span l~ne'l.
Shown in FIG. 7 are span lines 1,2 and N, each having associated near and far terminals. The terminals are coupled via appropriate buses to,a near high fx,e-quency coaxial jackfield. Jac~fields are well known and are used for data routing.
Shown coupled to a near high frequency coaxial jackfield is a fiber protection switch system module 70 which interfaces ~ith a near protection line terminal 71. A far protection line terminal 72 is coupled to terminal 71 ~ia a protection span line. The far pro-tect~on line terminal 72 is coupled to the far protec-tion swi~ch system 73 via~a 5uitable data bus, which system 73 is directed via a data bus to the far high A.K.~dwards - 3 ~ . .

freguency coaxial jackfield.
As indicated, any service effecting failure in either direction of transmission at either the near or far end wi]l cause a transfer to occur to the protection span line. This transfer is normally effected by a set of priority rules. The priority of service span line as span lines 1 to N to transfer to the protection span line is determined by the location of ~he line in the ~erminal. In this manner, the highest priority is assigned to span line 1 and so on. I~ the prote~tion span line or its ~ssociated terminals as 71 and 72 fail, all transfers are prevented. If a transfer by a service line occurs and t~ protection line fails, the transfer is rese~. The highest priority to seize the protection line will prevent transfers by low prioxity lines. If a low priority line such as line 2 seizes the protection line and a higher priori~y line such as line:l then fails, the higher priority line will over-ride the lo~er priority l~ne and hence, seize th~ pro-tect~on span l;ne. I~ this occurs, the low priorityline will be rese~.
Each fiber protection switch system tFPS~
includes a protection s~itch control unit ~SC.
This un~t supervises the tranference reset evolutions which are brough~ about-by the various alarms forwarded to the PSC via the alarm interface unit AIU 50 of FIG. 6.
. The PSC, in turn, generates control signals which cause - its associated input and output units to xeroute PCM
data ~ro~ a failea service line to an operating protection line durin~ transfer an~ back to the service line at xeset. Further, the FPS as 70 and 73 monitors its associated span line for evidence of failure, which in turn will cause the PSC to inhibit ser~ice line transfer to the protection line. Xn this manner, the trans~er of a failed service line to a failed protection line is avoided as such a transfer is useless.
All PSC functions are controlled by a micro-processor such as the 8035 which has a stored pxogram A.X.Edwards - 3 , ~ .
- 16 ~
operating according to the above described sequences and sequences ko be further described.
As will be shown, the PSC directly interfaces with its associated input and output units via a c,ontrol bus interface (CBI) as well as with the AIU
50. When the PSC is initialized or placed in operation, it assures a unique fi~e bit address code ko ~ach CBI
unit. This,address code i5 subsequently recognized by the CBI as a signal to accept and interprets data rom khe PSC and in turn, to generate DC control signals to ~he AIU and the inpu~ and output units. In the reverse direction, the CBI accepts alarm levels and converts them to 'four bi-t data words for transmission to the' P5C. ' The input unit will ~e referred to as a DTI and receives an electrical signal through a suitable hybrid to proYide at an output a two rail NR~ data and clock signal~, The output ~,designated as DTO,pro-l~ I vides a compatible'signal which is derived from the two rail NRZ data and clock'signals forwarded by the ~TI. The'input signals from the PSC control operation of the DTO.
In order to best understand system operation, reference will be made to FI~S. 8 through 19 which will describe a sequence of events that occur at the near and far end of the syskem during the trans~er and reset operations necessary to access the protection or spare span line. The sequence of events to be described relate to the'aukomatic mode o~ operation. The basic objects of the system operation have been discussed in conjunct~on with FIG. 1 and FIG. 7~
In FIGS. 8-19, in order to understand signal flow, various line configura~ions have been used as shown in the legend. For example, a broken line ~hich is a series of successive dashes and doks represents the transmission of a keep alive signal. A heavy line represents the transmission o~ active control and data signals. A dashed line represents the transmission ~ ~6r~3 A.K~Edwards - 3 , .

o~ a code 1 signal, while a dotted line represents a data inhibit mode.
In the FIGS. 8-19 and in the system -to be des-cribed, the data signal is a 44.736Mb/s electrical waveform known in the art as a DS-3 signal~ This signal is converted to an optical signal and trans- -mitted via an optical fi~er, which fibers constitute both the sPrvice and protection lines which are shown . .
in FIGS~ 8-19.
NEAR END NORMAL OPER~TION
~eferring to FIG. 8', there is shown a near end terminal 84 which is designated,as a service line ter-minal and has the 'configuration depicted in FIG. 4.
The protection line terminal 94 is also shown and is associated with a protection span line 90. The service line'texminal is associated wi~h the service line 80.
Each'terminal as 84 and 94 has a separate AIU unit as 85 and 95 w~ich is the alarm interface unit briefly desc~bed in FIGS. 4 and 5.
The service line terminal is associated with a ' transmit hybrid 82 which receives transmitted aata from the multiplexer 81 ~as 10 of FIG. 1). The ser-vice'l~ne terminal transmits received data to the recei've hybrid 83 ~or transmission to the received port o~ multiplexer 81.
Shown enclosed in the dashed lines is a service line CBI 86 which is associated with terminal 84 and a protection line CBI 96 which is associated with protectiorl line terminal 94. Each CBI as 86 and 96 communicates with the respective AIU 85 and 95. The service line CBI interfaces with its data transfer output module 87, while protection line CBI 96 commun~
ic~tes with ;ts DTO 97. The output o~ DTO 87 is ~urther directed to ~n input o~ xeceived hybrid 83.
Th.e serv~ce line CBI 86 also communicates with the line DTI 88, while 'the protection line CBI communicates with DTI 98. Located between the service line DTI 88 and the protection line DTO 97 is a DTI data hus 99.

'773 The protection switch control unit (PSC) l00 communicates with the service line CBI 86 and the protection line CBI 96. The protection line ter-minal has a first data path coupled to its DTI 98 and a second data path which emanates from its DTO 97.
In Figure 8, the service line terminal 84 and its associated ser-vice line 80 are operating normally as are terminal 94 and protection line 90. The protection switch control unit or PSC 100 is providing a control signal test pattern insert to the protection line DTO 97 via the protection line CBI 96, which test signal is the binary signal 101010. This signal is a 10 "keep alivel' signal. The DTO 97 verifies reception of this signal by sending a test pattern detect signal through ~TI 88 to the PSC 100.
Hence, as one can ascertain, during the generation of the keep alive signal, which as will be explained further is 101010, the PSC executes a diagnostic routine which operates to monitor the operational status of the system as will be further described. Hence, in Figure 8, during a normal traffic condition on the service span line 80, the protection line DTO 97 gates a I01010 pa~tern onto the transmit direction at the respective system ends.
SER~I CE LINE AIU DETECTS AN ALARM CONDITION
Reerring to Figure 9, the AIU 85 of the service line has detected a major alarm condition in the local service line terminal 84. Under these conditions, the AIU generates a transfer request (59 of Figure 6). The transfer request ~XFREQ) is directed to the PSC via the CBI 86. In addition, the AIU 85 pauses for one second before enabling a Major Alarm, which will be further explained. The Major Alarm (MAJ AL) is not i~lemented until after a one second pause, as will be explained.
T PSC DETECTS TWE TRANSFER REQUEST
Referring to Figure 10, there is shown the sequence of events next occurring. The PSC has sensed the transfer request as shown in Figure 9. The AIU receives the acknowledged signal from the PSC (XFREN) and translates this acknowledged signal to a code 1 parity violation sequence which is ~ransmitted to the remote end. In es-sence, the AIU acknowledges the fact that the PSC has detected thc transfer request by generating the code 1 transmission. The presence of the transfer request causes the protection switch control 100 to initiate an interrupt via a stored program routine. When the interrupt occurs, the PSC immediately switches to a transfer subroutine. In sequence, the PSC obtains the address of the failed service terminal from the CBI unit 86 associated with the ter-minal. As indicated, the CBI is assigned a unique five bit address code bythe PSC, which code enables the PSC to access the CBI and hence, to accept and interpret data and to therefore in turn generate DC control signals to the AI U, DTI and DTO.
In the reverse direction, the CBI accepts alarm levels and converts them to four bit data words for transmission to the PSC. The PSC, as mon-itoring the protection line terminal, also determines that the protection line can accept transfer data and therefore transmits the transfer enabled (XFREN) to the AIU 54 of Figure 6. ~he AIU initiates this DC level into a hexidecimal code word known as code 1 (01010101 or 55H). The AIU 85 forwards code 1 to the transmit (Figure 10) direction of the service line terminal as shown by the dashed lines to notify the remote terminal that a transfer is to take place~ as will be explained.
The PSC 100 continues to step through the transfer subroutine gen-erating control enables to operate to latch both the service and protection CBIs 86 and 96, which in turn enable circuits at the near end.
PSC TURNS ON SERVICE LINE DTI
Referring to Figure 11, the PSC 100 supplies the 7 .3 \~ , . . .
A.K.Edwards - 3 ...
~, . .
- ~0 -service line CBI 86 with a receive control signal ~RX CONT)~ whioh in turn latches the service line DTI 88 gating the data signal from hybrid 82 onto the DTI data bus 99.
PSC ACTIVATES THE PROTECTION LINE CBI
Referring to FIG. 12, the PSC now supplies the protection-line CBI 96 with a receive control signal, which in turn latches the protection line DTI g8 gating the protection line receive signal which is the keep alive signal onto the DTO data bus. The DTO 87 is coupled to the receive hybrid 83 and hence, a receive path is afforde~ through protection line DTI 98, the service line DTO 87 to the hybrid 83.
THE PSC SUPPLIES THE PROTECTION LINE WITH
` A T~ANSMIT CONTROL SIGNAL
Referring to ~IG. 13 and simultaneously with the actions occurring in FIG. 12, the PSC supplies the protection line CBI 96 with a ~raRs~t control signal ~TX CONT), which in turn latches the protection line DTO 97. This inhibits the keep alive signal and serves to thereore gate the near end transmit signal from hybrid 82 onto the protection line transmit direction.
This occurs via DTI 88, the DTI data bus 99, DTO 97 and thence, to the protection line terminal 94. In this event, the keep alive is still being received from the far end which is untransferred.
THE PSC INHI~ITS SERVICE LINE TRANSMIT DIRE~TION
AND COMPLETES TRANSFER AT NEAR END
Referring to FIG. 14, the PSC turns off the service line terminal with a DS 3 inhi~it signal ~oupled to the service line terminal via the AIU 85. This in turn removes the data input to the receive hybrid 83 as shown in FIG. 14. Simultaneously, the PSC 100 supplies the service line CB~ 86 with a TX CONT signal, which in turn latches the service line DTO 87, which thereby gates the receive direction Erom the protection line into the hybrid 73. This path is a~orded throu~h the protection line ter~inal 9~ via its DTI 98 and DTO 87 A~K~Edwards ~ 3 of the service line. This completes the transEer at the near end.
At this point in time, it is now noted that the far end terminal still has the da~a signal impressed S upon its transmit line. The receive path at the near end is completed, but the far end is still transmitting a keep alive signal towards ~he near end~ The transfer at one end, as above described, requires approximately 250 microseconds.
TRANSFER SEQUENCE IS REPEATED AT THE FAR END
. ~
Referring to FIG. 15, the far end terminal is shown. As indicated, the individual components at the far end are identical with those at the near end and hencer similar numerals have been retained with the ar end terminal-and reference numerals followed by the letter F denote the far end.
At the far end, the service line AIU 85F has detected a code 1 which is being transmitted from the near end. This code l informs the AIU 85F that a ailure has occurred at the near end. The AIU 85F
translates ~he code 1 into a code 1 detect si~nal (CIDET~ which it forwards to the PSC lOOF~ This signal produces the same exact effect on the PSC lOOF as the XFREQ signal had on PSC 100 at the near end.
Thus, the PSC lOOF switches to the transfer subroutine which causes an identical transfer sequence to occur at the far end whereby all transmit and receive data at the far end are now applied to the far end protection line terminal 94F. Thus, both ends have now transferr~d to the protection line. Accordingly, it is understood that at this time, the keep alive was removed from both directions of transmission just prior to transfer. The normal data outputs from the service line terminals as directed to the hybrids are inhibited for the duration of the kransfer. The trans-fer sequence, as described, is completely symmetrical and may be inhibited at either end of the system with the same results.

As indicated above, it was explained that the near end AIIJ 85 paused for one second before initiating a major alarm closure ~MAJ AL). The AIU 85 waits or watches for the XFREN signal from the near end PSC 100 and if it does not receive this signal, it times out. The time out activates the major alarm lamp or other visual indicator. This also occurs at the far end.
If a major alarm occurs, it indicates that there is a failed service line which has not transferred and this is a permanent indication to the system user. If the XFREN signal is received, the AIU converts the major alarm to a minor alarm, thus indicating a line failure and implementing the transfer to the protection span line.
With the above description in mind, after the PSCs 100 and lOOF
complete the transfer routine just described, they switch back to the last instruction executed in the main program and continue in the main program cycle. The main program contains a subset of instructions to generate a status word. This word contains the address of the transferred service line system, which address is the same at both ends of the system and further con-tains a reset okay bit. The address part of the word determines that a proper transfer occurred to provide fail safe operation to insure that a split transfer has not occurred. The status word is periodically transmitted from both ends of the system.
In the sequence depicted, to implement a transfer subroutine, a counter is loaded. The counter is held in a set position as long as the XFREQ signal line at the near end is active. When this line goes passive, the timer is set to ~ero~ setting a reset okay flag at the near end. This flag is transmitted to the far end in the status word. In such circumstances where a transfer occurs at the near end, the XFREQ signal is never active at the far end. Hence, the timer commences j V~ 7 3 A.K.Ed~ards - 3 ~. .. .

its countdown as soon as transfer is completed at the ~ar end. When the timer goes to zero, the far end transmits a xeset oXay flag to the near end.
When the reset okay is received and transmitted at the near end, it provides the enable signal for a branch routine which corresponds to the reset su~-routine in the main program of the PSC. It is under-stood that thi~ branch rou~ine does not preempt the main program as was done in the case of a transfer request, but is initiated by a request sequential pro~ram instruction that has been written in such a way as to taXe into account the reset oXay flag status.
Thè sequential steps in the reset routine cause the following near end control signals to occur:
lS Referring to FIG. 16, the near end PSC 100 will open a communications channel to the far end via the parity bit which occurs d~ring every eighteen time ~.
slots.:.~.In FIG.. 16, it will be described how a xeset comm~.nces at the near ~d a~d the communication channel to the far end is established.
The PSC 100 clears the XFREQ and IDENT latches on the service line CB~ 86. The IDENT is a line which is directed to each CBI that senses the unit's location in the assembly which allows it to be assured a unique address by the PSC 100 during the initialization pro ces~. The PSC 100 sets priority interrupt threshold such that a new failure in the service line system undergoing reset will ef~ectuate a proper transfer.
This is necessary to prevent the reset routine fxom masking or hiding a new failure.
Re~erring to FIG. 17, there is shown near end operation where the PSC 100 clears the DS3 inhibit to reset the receive direction at the near end. The PSC 100 clears the DS3 inhibit and the TX control la-tch on the service line terminal and tu~ns oEf the service line DTO 87. Received data is now obtained via the service line and the receive output of th~protection line has.been blocXed at the DTO. The transmit direction I;1~6~

A.K.Edwards - 3 . .
- 2~ -is unaffected in this sequence.
Referring to FIG. 18, there is shown a near and a far end system. The PSC 100 at the near end transmi~s a reset code ~Code 14 OB hexidecimal or 00001011 binary) to the far end and waits for the far end PSC to send ei ~er reset or a xeset echo - ' (code 11~05 hexidecimal or 00000101 binary). The far end returns reset echo if the reset sequence is completed at the far end. Otherwise, it transmits resetO This establishes a route for both ends. Thus, if reset is receivea, the PSC 100 or 100F res~onds with a reset echo. If the reset echo is received, the PSC
~` ceases txansmission of reset/reset echo. As a result~
of the reset/reset echo, both ends commence a series lS ~4 steps to completely reset as follows:
Referring to FIG. 19, the PSC 100 activates the test pattern selected in the protection line DTI 98.
This removes data in the transmit direction via the service line DTO 87. This action restores the 101010 keep alive'pattern to the protection line. As a result, transfer data has been removed from the pro-tection line in both directions of transmission. ~he PSCs at both'ends clear the RX CONT ~rom the service line DTIs to therefore remove the input data from the D~I bus 99. The PSCs at both ends clear the transfer request (XFREN) from the service line AIUs 85 and 85F
removin~ the' major alarm inhibit. The PSCs at both ends reset the priority threshold to the lowest level to the'reby enable'the low priority service line to transfer in the absence of any transfer request from - --a hi'gh priority line.
It is, of course, understood that ~he above de$cribed automatic transfer can be manually implemented.
Essentially, the'above described description indicates how a transfer is accommodated to a span line ~or a service line failure. It is, of course, noted that operation occurs independent of the t~pe of span lines employed and hence, the above described system Edwards - 3 will operate with fiber optic span lines or coaxial lines.
As indicated above, the transmission system em-ploys parity bit addition to the data bik stxeam for error detection purposes. In this case, there is no xedundancy in the original binary sequence and hence, it cannot be altered except by increasing the frequency to insert extra parity bitsO Thus, as indicated, upon detection of an alarm condition, the near end PSC
operates to open a communications channel to the far end or vice versa ~ia the parity bit ~mployed as a controi signal. In this manner, a unique sequence of codes can be provide~, as will be explained, which employ parity bits both for bit error rate purposes as ~s done in the priOrart~ but also for a control ~nformat~on channeI, which channel operates to switch in a protection span line in the event of a service li~ne failure.
In implementing system operation, an eight bit code word is employed, which code woxd defines up to thirty-two codes or commands and which words are con-- tained in a cyclical code. These codes are extremely important to system operation as will now be explained.
T~E-AIU OPERATI~G CHARACTERISTICS
Basically, the AIU 85 operates to respond to system alarms and sends the proper loop signals to the PSC and the serv;ce line terminal. The AIU thus, as shown in FIG. 4, is an inherent and important part of the line terminal . Essentially, there are seven alaxms which are monitored by the AIU. It is noted at the onset that these alarms are convent.ionai alarms found in telecommunications systems and techniques for detecting these conditions are well known.
A first alarm is designated as the E.Q.L.O S
This:alarm indicates an equipment loss of s.ignal alarm and specifies a loss of signal to the input/output module 30 o~ FIG. 3. This alarm can be classified as a major or minor alarm depending upon the operation 1 l B~773 A.X.Edwards - 3 .
.

of a particular switch.
REMOTE L.O.S.
The remote loss of signal alarm is a loss of signal to the input/output unit 35 and is also classi-fied by the user.
TX LOL
This alarm indica~es that -there is a loss of lock on the clock signal and is a major alarm.
RCCPR
This alarm indicates one of ~wo alarms and speci-ies that either a clock converter has lost lock or the parity removal unit 40 has lost frame on the data.
SPAN L.O.S.
Span loss of signal means that there is a loss 15 - of signa~ to an optical receiver unit as unit 24 of FIG. 3. This is a major alarm~
EXCESSIVE ERRORS
This alarm indicates that the error rate on an optical span line has exceeded the error rate threshold which is selected by a user.
LVE'A
This low voltage and fuse alarm emanates from the sy~tem power supply and occurs when the power is intexrupted.
In the event of a major alarm, the AIU alerts the RSC ana waits for a response. ~any of the alarm func-~ions of the AIU are well known in the art and have been implemented in prior systems. In any event, in this ~ particular system, there are three high priority lin~s that the ~IU must handle extremely rapidly. These lines are the XFREQ, the CID and the XFREN. In the even~
of one o~ these lines becoming active, the AIU sends a transfer request signal, as indicated, to the PSC.
I~ the code word 1 is detected by the AIU, it sends a code 1 de~ect signal CID to the PSC. If the local AIU
receives a transfer enable signal XFREN from the PSC, it then sends the code word 1 CI to ~he remote ~IU.
The AIU communicates with the PSC via serial input B~3 A.K.Edwards - 3 . .

data lines~ The receive~parity code is the data line going to the PSC. Depending on the particular code word in the!parity code, the AIU can communicate between itself and the PSC and can convey messa~es from khe local PSC to the remote P5C via the parity code.
Accordingly/ the AIU communicates directly with the PSC by means of convenkional handshake lines which mark.-the beginning and end of communications be~ween the AIU and P5C, If the PSC initiates a commu~ica~ions sequence, its interrupt line goes to a low condition.
The AIU responds by sending a low. If the AIU initi-ates a se~uence, the handshake routing is reversed.
I~ either the PSC or AIU breaks the link between the units, the corresponding interrupt line will go high.
15 -- The above sequence is extremely simple-to imFle---ment and is a typical operating procedure between two eIectronic systems~ Hence, such handshake lines are well known and conventional in the axt and have been .
described in order to enable a clearer understanding o~ communications betwe~n the AIU and thePSC. Thexe-fore, the communications between the AIU and PSC must consist o~ unique codes which are mani~ested by forcing th.e~ parik~ bit to be modified to thus provide suffi-cient.codes indicative of parity bit variation to enable proper communictions between the AIU and the PSC ~
As indicated in conjunction with FIG. 6, the low fre~uency and high frequency lines to the AIU are derived from theparity information. The local AIU
communicates with a remote AIU via the parity bit in the data stream and the AIU will insert an eight bit - .
code word ten times or a total of eight~ bits of code. The other AIU will detect and process the code and .~nitiate tne.:proper response. Thus, the AIU can communicate with its counterpart at the remote end of thb switch.
In the above manner and in regard to data code depicted in FIG. 2, the AIU and khe PSC can communicate 1 X ~
A.K.Edwards - 3 with each other and have remote counterparts using eight bit cyclical code words, There are thirty-two code words available as shown in FIG. 20~ When a code word is transmitted over a span line, the Bo bit is sent first and the B7 bit is sent last. Henc~, the code words depicted above can be employed to denote var~ous operations. For example, code 1 is employed by thb local AIU 85 to alert a remote AIU ~5F tha~ a transfer has started at a local or near end. Coae 2 is sent by the PSC to alert the AIU that the local PSC will communicate with the remote PSC. Code 3 is employed as a rese~ command in order to eliminate a code 2,4,5 or 6 condition. Code 4 indicates that an AIU and associated circuitry wants to transmit errors down the span line.
Various other codes in cyclical order can be.
employed to implement all remote and local communica-tions. These codes.are implemented by the parity insertion circuit 32 of FIG. 4. The parity insertion unit basically operates to insert a parity bit into thb pulse stream at everyseventeen data bits and re-transmits the pulse stream at 18/17 times the incoming frequenc~. .
As indicated in FIG. 2~ a zero parity bi~ is transmitted for an even number of marks and a 1 parity bit is transmitted for an odd number of marks. The parity insertion circuit 32 controls insertion of the par~ty bit into the 4~.736MHz bit stream from the scrambler 31. This occurs under control of the clock from the clock generation circuit of FIG. 3. Circuits for performing bit stuffing employing a fixed frequency stuffing process for parity insertion are well known.
Referring to FIG. 21, there is shown a block diagram of a.parity insertion unit which can be employed for the parity insertion module 32 oE FIG. 4. A brie~
description of operation will be given as man~ of the circuit components in FIG. 21 are well known.
The incom~ng scrambled data is applied via a '7 ~ 3 A.K.~dwards - 3 .
.. . v dat~ buffer 120 into data ~lip/flops 121 at the rate of 44.736MHz. The data is gated out of NOR gate 122 at a 47.367MHz rate. After gating seventeen data bits, the gating action is inhibited for one bit by the clock inhibit circuit 123 to allow time for a parity ~it to be inserted. The gated data is clo~ked into a data flip/flop 124 which feeds the~parity counter 125 and the parity bit stuffing circuit 126 including the stuffed data buffer 127. The resulting :stuffed data is clocked out of buffer 127 at the 47.367MHz rate.
Refexring to FIG. 22, there is shown a simplified timing diagram o parity insertion. The incoming scrambled data as buffered by data buf~er 120 and fed into the da~a flip/flops 121 is clocked into the flip/
flops by a 44.736MHz four-phase clock derived from module 130. The data from the flip/flops is gated out ~la the NOR gates 122 under control of this clock to the data flip/flop 124.
FIG. 23 is a t~ming diagram which depicts the store a~d gate process. As shown in FIG. 23, the in-coming 44.736MHz clock is clocked into the data flip/
flop 121 on the risiny edge of the first clock period.
The same data bit is gated out of the ~OR gate 122 when terminals 3 and 10 shown in FIG. 23 which are employed for the four-phase clock, are low. The data bit is then clocked into the data flip/flop 124 on the rising edge of the third clock period. The incoming 47~367MHz clock is fed via clock buffer 131 and a di~ided by eiyhteen counter 132 to the clock inhibitor circuit 123 which produces a clock inhibit pulse at its output. This pulse is used to initiate the stuff-in~ pxocess since a parity bit is stuffed after every seventeenth data bit~ The output of counter 132 is also f~d to a sync buffer 133. A divided s~nc pulse appears at the output of buf~er 133 at the same time the parity b~t appears at the output of the data buffer 1~7. This divided sync pulse can be used to mask the parity bit -A parity counter circuit consists J ~B773 of the parity counter 125.
Referring to Figure 24, there is shown a timing diagram denoting the operation of the parity counter circuit. The parity counter as shown in Figure 24 is basically a toggle flip/flop. ',Vhen the output 15 of the flip/
flop is at logic one~ the parity bit at the flip/flop output 3 stays tlle same. Once the output 14 of the flip/flop goes to zero, the parity bit starts to toggle. At the end of seventeen parity bits, the parity counter is preset by the stuff enable pulse to a logic one state. Then, the process continues the clock period after the stuff enable pulse goes low. The parity bit stuffing process is a synchronous procedure which takes a total time of three clock periods to perform.
Figure 25 is a timing diagram of the stuffing process. When the clock inhibit pulse goes high, it stops the four-phase clock circuit 130 for the necessary clock period. The clock inhibit pulse applies a logic one to the input of the parity bit stufE circuit 126. This allows one to stuEf the parity bit on the input of the stuffed data buffer 127. On the next rising edge, the parity bit will be clocked out of buffer 127 as stuffed data out to the optical transmitter. The parity bit can be inverted to cause a parity bit violation and hence, to control the information conveyed by the parity stream as above described.
A falling edge of the signal on the parity violation insertion ~PVI) input to buffer 140 is fed to a discriminator 141 where it is digitally dif-ferentiated. On the falling edge of the PVI input signal, a logic one is clocked into the discriminator by means of buffer 142 and appears at the in-put of the pulse generator 143 for one clock period. When the clock inhibit goes low, the discriminator is reset. The logic one signal at the input of the pulse generator 143 appears at the output when the stuff enable pulse goes high. Thus, the pulse generator will enable ~ 16~ 773 A.K~EdwArds - 3 inverted parity bit to be inserted into the ;stuffed data output. In this manner, the unit allows *or deliberate violation of parity to be trans~itted required for proper operation of the automatic detect-ion switch as above described.
~ ssentially, the parity removal circuit 40 isshown in block diagram in FIG. 26. The parity removal circuit removes theparity check bit from the pulse stream and pro~ides an output pulse stream at 17~]8 times the incoming ~requency. The parity removal accepts incoming data applied to buffer 150 and an incoming clock 'applied to buffer 151 at 47.36MHz.
These'are'obtained from the optical receiver. The unit reframes the incoming sequence and performs a 15 -- parity check during each-frame. Under control of a-44.736MHz signal applied to bufer 152 and obtained ~rom the'clock generation circuit of ~IG. 4, the unit also removes thb previous inserted-parity bit ana brings the bit rate o~ the data back to 44.736MHz.
A four bit store circuit 153 is used to accom- ' -modate digit jitter due to frequency translation and any accumulated line jitter~ The input data as buf-fered by buffer 150 is clocked into the four bit store 153 bit b~ bit. The output of the four bit store are sequentially gated in the four to one data line serial converter 154. Divide by four counter 156 and 157 control the buffering operationO Counter 157 gates' the seriali'zer 154, while counter 156 clocks the'~our bit store.' Counter 156 as driven by the ~ncom'ing clock is inhibited for one pulse in eighteen whi'ch'is the parity time slot by the gating circuit 157 which pro~ides a ~ate one period wide by means o~
the divide'by eighteen countex 158.
Th'us, the parity bit is not clocked into the four bit store and is eliminated from the output data stream. The incoming data via buffer 150 i5 also fed to a parity counter 159 which retimes the data stream and acts as a toggle~ The tog~le output will always 1 ~66773 A.K.Edwards 3 - - 32 ~
be in the same state as the data kime slo~ i~nediately following t~.eparity bit time slot, unless there are parity violations.
The output of counter 158 i5 also applied to gate 160 which together with gate 151 provides four phases of the divide by eighteen clock sequence. This ~ating sequence is shown in FIG. 27. One o the four phases of the counter 158 i5 retimed in retimer 161 to provide a one period wide pulse, clock pulse 3 and delayed by one clock period to produce clock pulse 40 W~en the unit is in frame~ clock pulse controls the sa~pling o thepari~y bit and stores it in the parity bit sample 162. Therefore, 162 conkains the present ana previous parity samples which are exclu-sively ORed by the~parity violatlon detector 163~ Ifthe two samples are the same indicative of no parity violations, then clock pulse 4 gates a low onto the Q output of the parity violation detector 163. If the two samples are not the same, a parity violation has occurred ~nd the Q output of detector 163 goes h~h~ . -The Q output of detector 163 is fed to a divideby ten counter 164 via a count reset control arrange-ment consisting of modules 165 and 166. As long as no ~iolations are being received, the ~ivide by ten counter 164 will continuously reset. Each time a violation occurs, counter 164 will count up by one count and i~ no violation occu~s, the counter is resek.
Thus, counter 164 will reach a count of ten and trigger an out of frame condition on the loss of frame driver 16~ when ten consequtive violations are detected.
This will illuminate a suitable indicator via buffer 168.
While in thein frame condition, every violakion is gated via the buffer inverter 170 a5 a high going parity violation pulse. This pulse is eight,een time slots long for every violation. Once the ~ ~frame .3' ~ condition has been registered, the parity viola-tions .

t ;~6~773 A.K.Edw~rds - 3 .

output is inhibited and the framing circuity goes into a search mode. In this mode, a parity violation will cause counter 164 to reset and a good parity indication wi~l cause it to count. Each time a parity 5 violation is detected, it is assumed that the unit is incorrectly framed and the count reset control 166 gates an inhibit command pulse to a pulse narrower circuit 170. Tha ou~put pulse from circuit 170 is ~ed to counter 158 to delay the counter by one count 10 period. With clock pulse 1 from gate 157 delayed one period after clock pulse 3, parity bit sampler 162 contain~ the'outpuh: of the paxity counter one period later than that sampled by clock pulse 3. This infor-mat~on ;'s forced onto the parity bit sampler 162 by the'del'ayed parity gake pulse formed ~rom c'ontrol ~66. Accor~ingly, when clock pulse 3 takes the next sample~' ~t is comparing'~he present sample with the ~re~ou's sample'although'the sample has now slipped one 't;me 510t with respect to the frame. If no parity ~olat;on occurs, the counter 164 is incremented by one ,' l`here:Eore, every time a v1olatlon occurs, counter 164 i~ reset 50 tha~ it takes ten consecutive no vlo-lat~on coun~s to rea~t in an in ~rame condi~ion. Every 25 time a pari;~y viola~ion is detec~ed, counter 164 is ~orced to slip a pulse until the correct f~amlng iS
achi~'e~ed.
' While in theoutof f~ame condition, the buffer inverter 170 is prevented from gating parity violations out and its output is held low. The counter 156 must be inhibited once every eighteen time slots at the parity bit period. Clock pulse 1 accomplishes this.
S~nce clock pulse 3 samples the parity bit, this defines the phase relationship_o counter 158 with the eighteen bit frame.' This timing is depicted in'FIG. 28.
The~parity removal circuit monitors incoming line signals for pari~y violations and out of frame conditions, but serves to retrieve all parity information A,K,Edwards - 3 to enable parity codes to be used for control of the automatic span switching control as above described.
PROTECTION S~ITCH CONTROL (PSC 100 ) As is ascertained from the above descripkion, the protection switch control 100 is microprocessor based and operates with a storedprogram. The PSC
100 interfaces with a plurality of CBIs such as the service line CBI 86 and the~.protection line CBI 96 and eommunicates with the CBI. It is throuyh this unit that the PSC can communicate with the DTO 87 and DTO
as well as DTI 88 and DTI 98.and the AIU 85.
97 As is shown in FIGS. 8 through 19~ the operation ~o 3\ ~ of the PSC is relatively complex, but based on the above explanations and comments to follow, one skilled in the art will have'no diff.iculties in programming a ~onven-tional microprocessor to implement such functions.
Microprocessors which may he employed for the PSC ar~
manufactured b~.many companies as Motorola, National Sem~conductor, Zilog and others. Once the operation ' 20 re~uirements o~ the~unit are ascertained as above ~es'c~ibed, the implementation of the structure is rei'atively straightforward~
The P5C interfaces with the control bus inter-face or CBI and may interface with up to thirteen such units including khe CBI associated with the protection line'terminal~ The CBI intexfaces mainly with up to thi'rteen data transfer inputs ~DTIs) and data transfer out~uts tDTOs). All.these units comprise the ~iber protection switch (FPS) which is shown in dashed line ~n ~IG~. 8~19.
The FPS also interfaces with the AIUs in the associated line ~erminals. The combined operation of the PSC, CBI, DTO, DTI and AIU units has been explained in terms of basic functions; The present discussion concerns itself with other considerations regarding the'design and structure of such units.
The main function of the PSC is to monitor all alarm conditions orginatin~ ~rom the DTO, DTI or AIU
.. . .

7'~
A.K,Edwaras - 3 ... . . . .

ana then to initiate t~ appropriate operation in the form of the transmission of control signals which are directed to the DTO, DTI or AIU. All alarm and control lines which interface with the DTO,and~DTI
are DC control levels.
The interface between the PSC and the AIU, apart from having several DC control and alarm lines, also has a serial channel which permits the transfer of information between the modules in the orm o~ eight bit serial codes according to the format shown in æO
FIG.~ The PSC communicates with up to thirteen . C~Is by initializing each one wi'th a uniqu~ address l~ 3~`~ and therea~ter subsequently activating the desired CBI b~ outputting its address over a common bus.
The technique of doing this is easily implemented by ' means o a memory whi'ch will store each address o a CBI and access such an address when a CBI is to be activated. The'technique o~ performing such select-~on and address~ng by means o~ a microprocessor is ea's~ly implemented.
After selection of a desired CBI, the PSC act~-~ates the appropriatç input/output ~unction through appropriate select lines. In this manner, control data is forwarded over a four bit bidirectional data buS. Each'CBI as coupled to a PSC may be identified by its physical location in the switch which is deter-mined electrically by a separate IDENT line tied ~om each'CBI to the PSC. This line is used to load the' CBI address,at initialization. When in normal operation, the IDENT line also serves as a high speed p~iority interrupt which directs the PSC to the system requlrin~ ser'vice. Such interrupts in conjunc-tion with m~c~oprocessor techni~ues are also well known.
The operation of the PSC, as indicated, apart from automatic operation as desc:ribed, can be manually oriented using key pad entries fxom an appropriate control panel7 In this manner~ entries can be made on a manual basis at ar~y,time to alter the mode oE

7~3 operation or obtain status information. In order to provide system security, access to the keyboard may only be had by entry of a pass word. The aspects of implementing microprocessor operation in conjunction with a keyboard are also well known.
In regard to the system above described, a front panel associated with the keyboard would require at least three visual indications. A first indication would be a transfer complete which provides an indication that a current request for a transfer to a protection span line has been completed.
A second indication would be a transfer incomplete which would provide a vi-sual indication that a current transfer request could not be serviced due tomultiple requests or an FPS failure. A further indicator is designated as PSC fail and is a special failure mode which shows that the program has failed due to an internal failure of the PSC.
Since the PSC is the control unit for all switching functions, it is sufficient to divide its description into a control signal timing and level description as well as a switching operation, alarm and control signal sequence and system timing performance. To initialize a CBI, a unique se-lected four bit address is placed on the output bus by activating the read-write line of the PSC and by clocking in the address via a generator by puls-ing the IDENT line.
In regard to output operations, all control signals are outputtedvia the CBI using this sequence. First, the appropriate CBI is addressed and the output function selected using the select lines. Valid data is then in-serted on the data bus and clocked into the CBI by the clock pulse where it is latched in a register until cleared.
The PSC monitors alarm conditions and control inputs by scanning the appropriate lines. The sequence of events is the same as for output op-erations, except ` ~ ~

1 166773 ~K.Edwards - 3 , - 37 ~
that a clocking pulse is not generated. In regard to a re~uest from the AIU, the sequence of events in a program ormat are as follows:
The AIU places a request to kalk on an input line to the PSC. This input is periodically ~olled by the PSC based on its scanning technique. Hence, the PSC will scan the thirteen request lines from the AIUs of the serv~ce'line terminals. When a request is aetected', the PSC tran~nits to the requesting AIU a ready to recei've signal7 The moment that this signal ~s received~ the AIU tran'smiks to the PSC. Serial data ~s trans~erred to the'PSC over the aata bus and the P~C can now respond to the AIU with serial data.
The'PSC is the unit which closes down communi-15 ~ cation and hence, controls the lead to the AIU-and' wai~s ten milliseconds to insure that the AIU has ' completed transmission. When the AIU remov~s its reques't to talk, this closes down the transmission channel. I the PSC'desires to access an AIU, i-t places' an act;ve on the appropriate lead. The re,quired CBI is addressed and its request to talk lead is polled by the PSC. In the event of a CI~ET signal or an XFREQ signal, this immedîately causes the appro-' pr~ate'~nput line to the PSC to go acti~e and the P~C ~ill ~nterrupt any program to service a transfer request.
Transfer sequences start upon detection of XFREQ or CIDET signals ~rom the AIV,providing no higher priority claims the transfer. Upon receipt of the XFREQ signal as the irst stage, ~he PSC is vectored to the failed system CBI and immediately causes the DTI of the failed system to transfer t~a-~ic onto the'spare line in the transmit to span dir-ection. The CBI is made to txansmit out the XFERN, which causes thé AIU to return code 1 which is the transfer code to the ~ar end. It then ch~cks XF~EQ
~na CIDET to determine the cause of the transer request and sets up timin~ loops dependent upon that ~ \

A.K.Edwar-ls - 3 . ' . '' result. If the failure is on the incoming direction, the P5C chooses the longer timing period to allow the far end-to respond to CIDET, transfer to the spare and allow time for the spare line to settle. A~ter this reset period, the associated CBI is made'to acti-vate the DS3 CONT which completes the transfer on the incoming direction. If the CIDET signal is received first, the sequence of events is the same, except that a sho'rter timing period is selected since the remote end is assumed to have already transferred its signal.
As described above in regard to the automatic reset mode, this is initiated ~rom the end of the switch which'aetected in the incoming failure (X~'REQ). In this mode~' the PSC ~ains control of the serial channel'by activating the'ready to receive input to the AIU.
~hen the'AIU responds ~ith the request to talk, the PSC begins to transmit code ~ o~ FIG. 20. This causes the' AIU at the far end to activate its request to t~lk'to alert the remote PSC for code reception. This ~ al~ done via inserting the correct code sequence ~nto t~e'parit~ circuit in order to generate code 2.
The'remote PSC will respond by activating i~s xe~dy to receive li-ne,' thus locking in the serial chan-nel for bid~rectional connection. The remote end replies by re~urning the code 2 to the original end.
The orginating end now has confirmation that the re~ote'end is ready to receive and begins the reset sequence b~ transmitting the reset code. When the ~r end receives the reset code, it returns the same and at the 'same'time, restores the traffic in the receive direction to the service line terminal. A
counter is started and after a preset period, the ~r end removes the`transferred signal from the trans-~ ~it direction. At the originating end, as soon as ~le ~es'et code ;s received, the PSC xestores tra~fic to theservice line terminal in the receive direc~ion and removes the transferred si~nal from its transmit dir-ection. This completes the reset sequence as above ~ A.K;Ed~/axds - 3 .. . .

- 3~ -aescribed. The serial channel is then ~losed by the originating PSC which then transmits code 3 to the remote endO
As indicated, a manual or an automatic mode can be selected from a keyboar~ associated with the PSC
after entry of the pass word. On chan~ing the mode, the PSC will select a working span ~nd use the serial channel via the parity bit to signal the far end to chan~e its mode'also. In this manner, control can be' excercised ~rom either end of a span. In going from automatic to manual via the keyboard, the PSC, upon detection o~ the'manual commana, disables all high speed interrupts and will temporarily suspend all new transfers. T~e-PSC will then select the work}ng--system to tran~mit ~he mode change to the ~ar endand theh wait for a reply. The remote end, upon re-ceiving ~he mode chan~e woxd, disables high speed in~Prrupts and after a preset period, enters the 'manual mode. It immeaiately returns the manual mode set word to the orginating end. This again is a code'selected from FIG. 20 and is implemented via a change'in parity. The originatin~ end receives ` the echo mode set word and enters the manua~ mode.
~ this echo is not recei~ed, the originating end ~ill revert to the automatic moda and send the auto-mat~c mode 'set word to the far end. When both ends are 'tn the' manual mode,' transfer of any sys-tem to the spare'can be'made'if the spare line is operating propexly. This includes the option to preempt a ~a~led higher priority from the spare and replace ~t ~ith'a lower priority system.
In going from the manual to an automatic mode via the keyboard, the PSC selects a working system to transmit the automatic mode set word to the far end.
The'originatIng PSC tempoxarily suspends all transEers.
When the remote end receives the mode change word, it ret~rns it to the originating end and waits a preset period of time~ If no further commands are xeceived, 1 1667~3 A.K.Edwards - 3 . - 40 -it will then enter the automatic mode. The originating en~ on receiving the echoed mude set word, will select the automatic mode completing the mode change at both ends.
In the system, manual transfers can take place at all times, except when the spare line has failed~ If a.manual transfer is attempted while -the spare line is ~ailed, an incomplete indication will be given and ~o action taken. A request for manual transer is made from the keypad and results in the originating end transmitting the system number of required transfers to the'ar end o~er the spare line. The originating end w~ll immediately transfer the transmit direction of that system to the spare as shown above. Upon xeceiv~ng the'system number at the remote ~nd, the PSC
~ill immediately transfer its transmit direction to the'spaxe'and wait a preset period before completing the '~ransfer in the receive direction. When the ori-gina~ing end receives' the echoed system number, it will ~ait ~ prese~ period and then complete the ~ransfer in the recei've'direction.
A manual reset is performed by transmitting a reset coae word over the spare line. The remote end w;ll echo the rese~ word and immediately rese~ the s~nal in the receive direction. The transmit direction continues on the spare for a period of time after which ~t ~s removed~ The receive end transfers its receive d~rec't~on to the main span line immediately after ~ece'~'ving the keyboard commandO It will wait a preset per~oa beore removing the transmit direction from the ~pare.' I~ no'echo is received, it is assumed to be `~n undet'ected fault and the PSC will remove all keep aliYe 's~gnals from the spare,alarming the ~ar end.
Under'the condition5 w~ere a manual transfer is re~uired' and the system is already transferred, the new 'trans~er must 5imultaneousl~ re~tthe existing one.
In thi's mode, thebriginating end will first reset the existing trahs~er in the transmit direction and transfer 1 16 S 77 3 ~ . K~Edwards - 3 .. , the new system. It will then transmit the syskem number of the new transfer to the far end over the span line. Upon receiving system number at -the remote end, the PSC will immediately reset the existing trans~er in the transmit direction and transfer the new system.
It will echo the systen number and wait a preset time.
For thi's period, it will remove the old system and complete the'new transfer in the receive direction.
When thb'originatin~ end receives the echoed system number, it waits a preset period and then removes the old system and completes the new transfer in ~he réceive'directionr This completes the reset of the old system and transfers the new system.
THE CONTROL BUS INTERFACE ~CBI) As was ascertained ~rom the abov'e'descript'ion, the'CBI is used to transfer signals from the AIU to the PSC, pass alarms from the DTI and the DTO to the PSC
and transfer commands from the PSC to the DTI, DTO and ~IU un~ts as requ~red for system switchingD ~eferring to ~G. 29, ~here'is shown a simple block diagram of ~ CBI ~n order to clearly explain the ~escriptions Qf ~nputs and outputs and how the CBI operates~
As indicated above, the XFREQ is a request for transfer which orginates in the AIU and remains valid as long as an alarm is present. m is signal is trans-~erred to the CBI and then to the PSC. The signal is received by a line driver 200 where it is trans~erred and stored in a latch circuit 201 and coupled to a data selector module 202. The XFREN is sent to the AIU via driver 203 indicating that the AIU transmi~s a burst of code 1 to the other end of the system.
Hence, this signal comes from the data selector 202 and is applied through the latch circuit 201 to the driver 203. The code 1 detect is app]ied to ~ r 1 35 204 t latch 201 and data selector 202 and is a DC signal whi'ch is an indication from the AIU that code 1 has J
ne~
~'~ bee~ received at the ~ end. The DS3 CONT is a si~nal ~o ~ ~ emanatin~ rom driver 205 via latch 206 and is used 1 lB67 73 ~.K~EdwardS - 3 - ~2 ~
by the AIU to squelch th~ DS3 output of the service - line -terminal and hence, enable the DS3 output from the associated DTO.
TX CONT is obtained via latch 207 and controls the output of the DTO. The LOS O~P indicates a failure on the DTO as coupled to the PSC. The TPC ~ia amplifier 210 is a serial data path from the PSC to the AIU via the data ~us and is an indication for the transmission of th~ parity code. The ~PC via driver 211 i5 a xeceive parity code and is a serial data path from the AIU to the PSC.
The RX CONT which emanates from latch 207 squelches the data outputs to the main bus'at the DTI. The TPI
is a test pattern insert signal and in~orms the DTI to inser~ a-1010 test pattern on the main bus;- The ~OS ---I/P informs the PSC via the data bus of all ones or ~11 zeroe's condition on ;either rail of the main bus and/or'loss of input signal from the DTI. The TPD
signal indicates to the PSC that the 1010 test pattern is absent on the data inputs o~ the DTO. The TPS
~est p~ttern select places the test pattern on the DTO
output. The SBE signal is-the spare bus enable and ~nforms the DTI to insert both the test pattern and t~e 'test pattern clock on the spare bus lines. The INT ~llows the PSC to use the serial transmission to the''AIU and basically, this signal is the above des-c~bed ready to xeceive signal. The AINT is an inter-r~pt l~ne'from the AIU to the PSC and basically this s~gnal ~s the AIU's request to talk. The clock CLl is a clock pulse'~hich clears and clocks data into the ou~ut l~tches as 206 and 207 The ~/W pu-ts the TDE~T port in the input mode when active. The IDENT, as~ descr~bed above, IS a hard wired bidirectional line bbt~een the CBI to the PSC which clocXs the address l~tches as well as the latchin~ and indicatin~ XF~EQ
and~o~ code 1 detect to the PSC.
As indicated, each CB~ is assigned a uni~ue five bit address by the PSC as part o~ the initialization 7'~3 A.K~Edwards ~ 3 .. . .

process. The address is latched on the C~I via inputs A0 -to A4 to the address decoder 215 and employs a clock pulse from the PSC. This address is compared with the address bus to enable the CBI to recognize its own unique address. As seen, an eight bit word originates on the PSC, which word consists of the five bit address A0 to A4 for the CBI and a three bit CSl, CS2 and CS3 and three bit chip selection function. In this manner, the codes are as follows:
TABLE
CHIP SELECTION CODE FUNCTION
- O Cl~ars the XFREQ CI detect and IDENT
latches~
1 Enables the clock for the XFREN, INT, DS3-CONT and TX CONT- 1 atche~.
2 Enables the clock for the TPI, RX
CONT, TPS and SBE latches.
3 Allows LOS I/P and LOS O/P and alarms to be transmitted to the PSC~

4 Allows XFREQ, CIDET and AINT signal~
to be transmitted to the PSC.
Allows the PSC access to the TPC
serial transmission path.
6 Allows the PSC ~o determine if a particular CBI is enabled via the IDENT line.
7 Since the chip select lines are nor-mally high, this provides a clear or a no function condi~io~
Hence, as seen from FIG. 29, the block diagram of the CBI inconjunction with its-functions as above described, affords an extremely simple operation.
THE TRANSFER OVTPUT VNIT (DTO?
As indicated, the DTO accepts two rail NRZ from the transfer in module or DTI. The unit receives clock pulses from the DTI and operates under control o~ the PSC which sends two control signals via the CBI to the DTO. During normal operating conditions r the unit receives test patterns from the DTI sequen-tially via the main data bus and receives test pa-ttexns from the DTI via the spare da-ta bus as well as clock ~ $ ~ ~ 3 ~.K.Ed~1ards - 3 ;. ' ' .

signals. The DTO monitors the signal on the main data bus and provides an alarm signal to the CBI when the test pattern code is violated by incorning data.
Under control of the PSC via the CBI, the DTO places main data hus tra~fic or spare data bus traffic on the output stage. This output stage may ~he turned off or on by the TX CONT received from the PSC via the CBI. The DTO routes clock through reshaping circuits' ' to provide accurate con~rol pulse widths. Upon fail-' 10 ure of a ser~ice line terminal, commands will bereceived from the PSC vi~ ~he CBI which will cause the failed traffic to be routed on main data buses and transmitted by the DT~ to the protection line terminal.
In the re~erse direction, the signal received from a protection line terminal will be routed through a DTI to a DTO. The DTO will transmit a proper coded signal at this'point. The unit basically employs line receiver amplifiers in a single ended mode to receive ~r amplify clock and'two rail data signals from the D i3t- ~ 20 'buses to proper logic levels. In this manner, ~he unit uses OR/AND gates to route main and spare clock and data signals~under control of the test pattern select signal received from the PSC ~ia the CBI.
The implementation o~ the DTO is relatively simple. When the TPS signal is low, the main bus clock is routed directly to retiming flip/flops and the 101010 test pattern detector. The spare bus clock is routed to reshaping circuits. The reshape clock is xouted to spare data retiming flip/flops and an NRZ to RZ converter. The reclocked spare bus data is routed to the NRZ to RZ code converter and to an output stage. When the TPS signal is high, the main bus clock is routed to a reshaping circuit and this clock is routed to main data retiming flip/
flops, to theNRZ to RZ code converter and the 101010 pattern detector. The spare bus clock is routed directly to spare data retiming flip/flops, while the reclocked main bus data is routed to the N~Z to RZ

A.X~Edwards ~ 3 .
. : , - ~5 -code converter and on to the output stage.
Accordingly, wi-thout givin~ exact details of circuit construction, it is well known to perform clock reshaping in order to permit the DTO to develop stable, well-defined output pulses. NRZ to RZ code conversi~n is also well known and can be implemented by NOR/OR gates using clock and data as inputs.
The output stage is implemented by two identical constant current differential amplifiers, where each a~plifier pair is driven by a set of complementary ou~puts o~ the NRZ/RZ code converter to implement a rail of data received ~xom the data bus. The constant current source used to d~ive the output stages are operational amplifie~ sources and the TX CONT signal received from the PSC via the CBI is interfaced with the source to squelch ~he output by turning of~ the current to the differential amplifierO
The unit is equipped with a test pa~tern de-t~ctor which monitors the returned main data bus signals. The output of this detector is converted to a compatible logic level which is at a high value when the test pattern is reset. This is also a conventional circuit. The DTO is equipped with a loss of si~nal detector where the output of this ~ ~ `
detector is high for no signal loss and essentially~
the DTO perfor~s the functions as indicated in FIGS~
8 through 19.
THE TRAI~SFER IN INPUT CI:E~CUIT tDTI~
. .
The DTI accepts a standard si~nal from the ~
multiplexer or a line terminal via a hybrid and pro-vides two rail NRZ outputs and clocks. The DTI also has a test pattern (101010) generator which may be switched on to the two rail bus. Interface driver circuitry is provided in the unit to place the test pattern and clock on the spare two rail bus and the spare clock bus. The unit is controlled by three control sequences ~rom the CBI which is the test pattern insert TPI, the receive control spare bus A.K.Edwards ~ 3 ;'`,''. .
- ~6 -enable (SBE) and the unit provides an alarm if there is a failure of the input signal or if thexe is an all one or all zero condition on the output of the retiming circuitry~
The DTI.accepts a signal from a multiplexer or a line terminal and has an amplifier with AGC
allowing this signal to be driven at a constant level regardless of the length of line coupling the DTI.
The DTI has a clock recovery circuit where positive and negative going pulses are combined to drive a tank circuit. This clock recovery circuit is conven-tional and a signal from an LC tank is fed to an amplifier via a high impedance boot-strapped emitter follower circuit~ The output of theclock recovery circuit is-used for retiming the incoming data, generation o the test pattern and bussing to other modules.- The signal is retimed by the recovered clock and converted to two rail NRZ data by the use of conventional D type of fl.ip/~lops~ A test pattern generator uses the derived clock to generate the test pattern signal and this signal is switched to the main data bus or the spare da~a bus as required.
The data/test pattern selector is controlled by ~he TPI signal received ~rom the CBI and this signal is used to sequentially place the test pattern signals on the DTIs as controlled by the PSC.
The DTI use~ bus drivers for the two rail data bus and the clock bus. These drivers are ~ontrolled by the receive control signal received from the CBI.
The unit use5 bus drivers ~or the two rail spare data bus and clock bus. These drivers a~e controlled by the spare bus enable si~nal (SBE) received ~rom the CBI The unit provides an alarm signal upon the ~ Lines-of input signal or loss of activity at the Ç~ 35 output of the retiming circuitry. The absence o~
this alarm indicates that the input signal is heing received and that the clock recovery and retiming circuits are operating normally.

1607~3 A.K.Edwards; - 3 - ~7 -Hence, the above described system is operative to automatic protection switching which incorporates a plurality of service linesand at least one protect-ion line. The parity violation control operates to insert parity violations in a parity insertion circuit associated with a serivce line terminal. Insertiun of parity according to an algorithm allows thirty-two codes to be used for control of the automatic pro-tection system to enable near and far end terminals to communicate with one another.
The particular application described is employed for a binary transmission sy$tem which uses bit addi-tion for error detection purposes. The parity viola-tion code can also be used as a remote reporting i5 channel so that codes can be sent from distant of~ices to a central location to provide indication o~ various ~larm conditions at a remote loca~ion. The system is completely suitable for high speed digital systems such as those employing optica~ fibers and provides a lo~ freguency control interface suitable for micro~
processor control, while avoiding the use of high powex, high speed control circuitry.
By the use of parity violation control, both pro-tective switch~ng and remote reporting schemes are possible. In this manner, the system can employ an eight b~t code word to define up to thirty-two codes or com~ands and to use a portion of such commands as val~d code designat~ons to afford automatic protec-tion sw~tching as above described.

Claims (24)

A.K.Edwards - 3 I CLAIM:

1. Automatic protection apparatus for a tele-communications system including at least one service line terminal associated with a service line and at least one protection line terminal associated with a protection line, with said service and protection lines extending between a near telecom-munications office to a far telecommunica-tions office for transmitting between said offices digital data indicative of infor-mation, with said data as transmitted com-prising a number of successive data frames, wherein each frame has a plurality of data bits and at least one parity bit indicative of the count of said data bits being even or odd, comprising:
monitoring means for sensing a failure of service line between said near and far offices;
parity code inserting means coupled to said monitoring means and operative to modify said parity bit from frame to frame to indicate said failure;
switching means responsive to said frames of data as modified in parity by said code inserting means for trans-ferring at said near and far end said telecommunications service line to said protection line upon sensing said failure according to said parity bit modification; and control generation means coupled to said parity code inserting means for further modifying said parity bit as transmitted to enable said near and far end to communicate to provide indications necessary to fully complete said transfer.

2. In a telecommunications system including a plurality of service span lines connected in series relationship between a near end office and a far end office to afford communication between said offices via a digital data signal transmitted on said lines, with said signal comprising a given number of data bits per frame, with at least one parity bit indicative of the count of said data bits as being even or odd, comprising:
a protection switch control unit at each end of said span line and a line service terminal at each end of said span line coupled to said associated protection switch control unit, said service terminal including parity insertion means for modifying said parity bit on a frame to frame basis;
means responsive to a failure of said service line and coupled to said line service terminal to modify said parity bit for transmission of a code over said service line indicative of a line failure; and logic means coupled to said protection switch control unit to transfer said failed line at both said near and far end following the occur-rence of said failure.

3. The telecommunications system according to claim 2 wherein a frame of said digital data signal contains eighteen bits where-in the eighteenth bit is a parity bit, with the remaining bits being data bits.

4. The telecommunications system according to claim 3 wherein A.K.Edwards - 3 said means for modifying said parity bit is on a frame to frame basis to enable generation of at least thirty-two codes each of an eight bit code word, transmitting at least one of said codes out of said thirty-two codes to indicate service line failure.

5. The telecommunications system according to Claim 2 wherein said service span lines are optical fibers having impressed thereon optical data manifesting said digital data.

6. The telecommunications system according to Claim 2 wherein each of said service line terminals further includes parity removal means responsive to said parity bit content of said digital signal for responding thereto, and means for detecting a code carried by said bits manifesting said service span line failure.

7. The telecommunications system according to Claim 2 wherein either said near or far end office can detect said failure and hence modify said parity bit content.

8. The telecommunications system according to Claim 2 wherein each of said service lines has assigned thereto a particular priority and priority detecting means included in said protection switch control unit for affording transfer to a higher pri-ority span line when a failure occurs in at least two different priority span lines.

9. An automatic protection apparatus for a telephone system of the type including at least one service line terminal associated with a service line and at least one protection line terminal associated with a pro-tection line, with said service and protection lines extending between a near and a far central office for transmitting digital data therebetween, with said data as transmitted comprising a number of successive data frames, wherein each frame has a pre-determined number of data bits and at least one parity bit indicative of the count of said data bits in said frame being odd or even, comprising:
a first alarm interface unit coupled to said service line terminal and operative to monitor said service line to detect a failure;
a second alarm interface unit coupled to said protection line terminal and operative to monitor said protection line to detect a failure;
a service line control bus coupled to said first alarm interface unit for providing a plurality of data output lines;
a protection line control bus coupled to said second alarm interface unit to provide a plurality of data output lines;
protection switch control means coupled to one of said data output lines from each of said service and protection line buses to allow said first and second alarm interface units to communicate with said protection switch control means, said protection switch control means modifying said parity bits for communicating with said far end terminal con-nected to said service line;
first data transfer input means associated with said service line and having an input coupled to another output data line from said service line bus and an input coupled to a transmit side of said service line;

A.K.Edwards - 3 first data transfer output means associated with said service line and having one input coupled to said service line bus and an output coupled to said receive side of said service line;
second data transfer input means associated with said protection line and having one input coupled to said protection line bus and an output coupled to said first data output associated with said service line, and an input coupled to said receive side of said protection line, second data transfer output means associated with said protective line and having one input coupled to said protection line bus and an output coupled to the transmit side of said protection line;
a data bus coupled between said first data transfer input means and said second data transfer output means;
whereby upon detection of a failure by said first alarm interface unit said protection switch control operates to connect the transmit side of said service line to the transmit side of said protect-ion line via said first data transfer input means and said second data transfer output means and to connect said receive side of said service line to said receive side of said protection line via said second data transfer input means and said first data transfer output means.

10. The automatic protection apparatus according to Claim _9 wherein said protection switch control means as coupled to said service line terminal includes means for modifying said parity bits to transmit via said service line a modified parity bit signal indicative of said failure and necessary to com-municate the same to said far end terminal connected to said service line.

11. The automatic protection control apparatus according to claim 9 wherein said protection switch control means provides a control signal to said second data transfer output means associated with said protection line indicative of a "keep alive" signal indicating that said protection line is available for transfer.

12. The automatic protection control apparatus according to claim 9 wherein said first alarm interface unit upon detecting a failure provides a transfer request signal to said protection switch control means via said service line control bus.

13. The automatic protection control apparatus according to claim 12 wherein said protection control system responsive to said transfer re-quest signal provides an enable signal to said first alarm interface to en-able said first alarm interface as coupled to said service line terminal to cause a parity code signal to be transmitted on the transmit side of said service line, to notify said far end of said failure.

14. The automatic control apparatus according to claim 13 wherein said parity code signal is a selected one out of thirty-two cyclical parity codes each having eight bits.

15. The automatic control apparatus according to claim 14 wherein said protection switch control means A.K.Edwards - 3 provides a receive control signal to said service line control bus for latch-ing said first data transfer input means onto said data bus coupled to said second data transfer output means.

16. The automatic control apparatus according to claim 15 wherein said protection switch control means provides said protection line control bus with a receive control signal which latches said data transfer input means associated with said protection line onto said data bus.

17. The automatic control apparatus according to claim 16 wherein said protection switch control means provides said protection control bus with a transmit control signal to latch said protection line data transfer output means onto said protection line transmit side.

18. The automatic control apparatus according to claim 17 wherein said protection switch control means inhibits said service line terminal in the transmit direction to allow transmit data transmission through said protection line terminal.

19. The automatic control apparatus according to claim 18 wherein said protection switch control means inhibits said service line terminal in the receive direction to allow receive data transmission through said protection line terminal.

20. The automatic control apparatus according to claim 9 further including keyboard means coupled to said pro-tection switch control means to manually A.K.Edwards - 3 cause said means to transfer one of said service lines to said protection line.

21. The automatic control apparatus according to claim 9 wherein said service line and said protection line are optical fibers.

22. A method of providing a control code for use in communicating control information from a near end telecommunication location to a far end location which locations are in communi-cation via a digital transmission line, carry-ing digital data, encompassing a plurality of sequential data frames each having a predeter-mined number of binary bits, with at least one bit in each frame indicative of a parity bit for conventionally determining whether ones of said data bits in said frame are even in number or odd in number, comprising the steps of:
intentionally modifying said parity bit in successive frames to provide cyclical codes each code manifesting a separate control status;
responding to said parity bit as modified to provide said code to enable performing a control function as speci-fied by said code;

23. The method according to claim 22 further including switching a back-up transmission line between said near end telecommunications location and said far end location upon responding to one of said codes.

24. The method according to claim 22 wherein said digital data frame comprises eighteen bits, with the eighteenth bit being said parity bit, selecting said eighteenth bits, modifying said bits, in successive frames to provide thirty-two unique eight bit codes.