CA1163385A - Method of and apparatus for transmitting data in a synchronous data network - Google Patents
Method of and apparatus for transmitting data in a synchronous data networkInfo
- Publication number
- CA1163385A CA1163385A CA000369294A CA369294A CA1163385A CA 1163385 A CA1163385 A CA 1163385A CA 000369294 A CA000369294 A CA 000369294A CA 369294 A CA369294 A CA 369294A CA 1163385 A CA1163385 A CA 1163385A
- Authority
- CA
- Canada
- Prior art keywords
- bits
- data
- envelopes
- assignment
- multiplex frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/22—Arrangements affording multiple use of the transmission path using time-division multiplexing
- H04L5/24—Arrangements affording multiple use of the transmission path using time-division multiplexing with start-stop synchronous converters
- H04L5/245—Arrangements affording multiple use of the transmission path using time-division multiplexing with start-stop synchronous converters with a number of discharge tubes or semiconductor elements which successively connect the different channels to the transmission channels
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/24—Time-division multiplex systems in which the allocation is indicated by an address the different channels being transmitted sequentially
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Computer Hardware Design (AREA)
- Time-Division Multiplex Systems (AREA)
Abstract
ABSTRACT
"METHOD OF AND APPARATUS FOR TRANSMITTING
DATA IN A SYNCHRONOUS DATA NETWORK"
Summary Terminal devices El to En are connected via a t.d.m. arrangement MX to a peripherai node PK of the network. A multiplexer Ml or M2 forms a multiplex frame from a plurality of data envelopes (comprising data bits and control bits) supplied via input data channels (e.g.
Kl to Kn in the case of Ml). The synchronising bits (and possibly some of the status bits) of the control bits are substituted by assignment bits indicating the envelope/
data channel assignment. The data bits can be grouped consecutively in the frame or can be separated into groups by assignment bits distributed through the frame. The corresponding demultiplexer D2 or Dl receives the multiplex signal and distributes the data bits into envelopes assigned to data channels in dependence on the associated assignment bits.
"METHOD OF AND APPARATUS FOR TRANSMITTING
DATA IN A SYNCHRONOUS DATA NETWORK"
Summary Terminal devices El to En are connected via a t.d.m. arrangement MX to a peripherai node PK of the network. A multiplexer Ml or M2 forms a multiplex frame from a plurality of data envelopes (comprising data bits and control bits) supplied via input data channels (e.g.
Kl to Kn in the case of Ml). The synchronising bits (and possibly some of the status bits) of the control bits are substituted by assignment bits indicating the envelope/
data channel assignment. The data bits can be grouped consecutively in the frame or can be separated into groups by assignment bits distributed through the frame. The corresponding demultiplexer D2 or Dl receives the multiplex signal and distributes the data bits into envelopes assigned to data channels in dependence on the associated assignment bits.
Description
`` t IL6~385 The invention relates to a method of and apparatus for transmitting data in synchronous data networks wherein the items of data are transmitted in groups in envelopes formed from control bits and data bits, and wherein a plurality of terminal devices can be connected to the data network in each case via a data channel, ' and wherein connection lines between the terminal devices and the data network are multlply exploited.
;~ It is already generally known to transmit data via a synchronous data network in which terminal devices are connected into the data network via connecting devices. The connecting devices combine the data emanating from the terminal devices in the form of blocks which are referred to as envelopes. Each envelope is of the same length and consists of a predetermined constant number of data bits and t.wo control bits which are referred to as a synchronising bit and a status bit. The control bits may be arranged, for example, at the start of the envelope, or else the envelope commences with the synchronising bit and ends with the status bit. The synchronising bit ; facilitates the acquisition of the data bits and the restoration of the status bit from a received bit flow.
The status bit informs a swltching device of the data network as to whether the items of data contained in the data bits consist of co~munications from subscriber to subscriber or of communications for the exchanges participating in the connection or of items of control
;~ It is already generally known to transmit data via a synchronous data network in which terminal devices are connected into the data network via connecting devices. The connecting devices combine the data emanating from the terminal devices in the form of blocks which are referred to as envelopes. Each envelope is of the same length and consists of a predetermined constant number of data bits and t.wo control bits which are referred to as a synchronising bit and a status bit. The control bits may be arranged, for example, at the start of the envelope, or else the envelope commences with the synchronising bit and ends with the status bit. The synchronising bit ; facilitates the acquisition of the data bits and the restoration of the status bit from a received bit flow.
The status bit informs a swltching device of the data network as to whether the items of data contained in the data bits consist of co~munications from subscriber to subscriber or of communications for the exchanges participating in the connection or of items of control
-2- '~
.
.
t 1~;338~
information for the data terminal devices.
As regards the formation of the envelopes, in accordance with CCITT
X.50, two stnlctures are known, namely a 6-~2 structure and an 8~2 structure.
In the former case the envelopes are formed from six data bits, one synchronis-ing bit, and one status bit. In the latter case the envelopes are formed from eight data bits, one synchronising bit and one status bit. Since, during the transmission of data from the subscriber station, the formation of the envelop-es takes place in the connecting devices, the envelopes are transmitted via the subscriber connection lines to the assigned exchange. As a result of the additional control bits, the gross bit Elow which is to be transmitted is 30%
or 25% higher than the net bit flow between the terminal device and the connect-ing device.
Known connecting devices which operate with one channel can exchange data only with one terminal device. It is conceivable to precede a connecting deyice with an interface multipler, although such an arrangement would have the disadvantage that during a predetermined length of time only one data terminal device can emit data to the data network.
From our German specification AS 28 28 602 published Dec. 13, 1979, it is known to use the envelope itself as a multiplex frame. In this case the individual data ~its of the envelope are assigned to various data channels.
The assignment of the data channels to the data bits is effected by means of ~ !16.~3~
. .
control bits of the envelopes.
It would also be conceivable to connect a -; plurality of data terminal devices via a channel divider which, in accordance with a known t.d.m. process, connects the terminal devices to the data network. When a ; conventional t.d.m. process is used, here again additional ` ! synchronising devices are required to establish the correct assignment between the data channels at the transmitting subscriber station and at the receiving subscriber station.
Thus an arrangement of this kind would have the disadvantage that it necessitates a relatively high initial outlay which is not viable unless a large number of data channels are provided. Furthermore additional bits have to be inserted to characterise the assignment of the individual envelopes to the data channels.
,~ According to a fixst aspect of this invention ~,,, there is provided a method o transmitting data in a synchronous data network in which a plurality of terminal devices supplying data envelopes including control bits are to be connected to the remainder of the data network via a t.d.m. link, said method including the steps of, at the transmitting end, forming a multiplex frame from a plurality of the data envelopes supplied via a plurality of input data channels, substituting for some of the control bits, assignment bits indicating the assignment of the data bits in each multiplex frame to the input data channels, and at the receiving end, using the received ~ 1~333~
assignment bits to allocate the associated data bits to envelopes in respective corresponding output data channels and reproducing the substituted control bits and reinserting them into the appropriate envelopes.
According to a second aspect of this invention - there is provided apparatus for transmitting data in a '~ synchronous data network in which a plurality of terminal ; devices supplying data envelopes including control bits are to be connected to the remainder of the data network via a t.d.m. link, said apparatus comprising transmitting means arranged to form a multiplex frame from a plurality of the data envelopes supplied via a plurality of input data channels, means for substituting for some of the control bits, assignment bits indicating the assignment of the data bits in each multiplex frame to the input data channelsl and receiving means arranged for using the received assign-~, ment bits to allocate the associated data bits to envelopes in respective corresponding output data channels, means for reproducing the substituted control bits and means for reinserting them into the appropriate envelopes.
A particularly low outlay is required when the control bits substituted by the assignment bits are synchronising bits, and those control bits comprising status bits are trans~erred unaltered into the multiplex frame.
If the synchronisation of the multiplex frame requires more assignment bits than synchronising bits are available in the envelopes, it is favourable that the i l~3385 control bits s~stituted by the assignment bits comprise synchronising bits and some status bits and the remainder of the status bits are transferred unaltered into the multiplex frame.
It is possible to contrive the multiplex frame to be such that the data bits are arranged ` consecutively in the multiplex frame. However it can also be advantageous for the assignment bits to be distributed in the multiplex frame between data bits.
In one embodiment of the apparatus the transmitting means comprises a number of shift registers corresponding to the number of input data channels and into which the envelopes of the input data channels are respectively input in serial fashion, a synchronising stage which is connected to parallel outputs of the shift C registers and which produces the assignment bits and a further shift register into whi~h the data bits of the envelopes, the assignment bits and the remainder of the control bits are input in parallel a~d which emits the multiplex frames from its serial output.
The receiving means may include a shift register into which the received multiplex frames are input in serial fashion, a synchronising stage to which the assignment bits of the multiplex ~rame are supplied and which reproduces the substituted control bits of the envelopes, and a num~er of further shift registers correspondin~ to the number of output data channels and ~ ~338~
which are supplied with the data bits and the control bits and which at their serial outputs emit the envelopes assigned to the respective output data channels.
Embodiments of this invention will now be described, by way of example, with reerence to the accompanying drawings in which:
Fig. 1 is a block circuit diagram of a part of a known data transmission apparatus;
Fig. 2 is a block circuit diagram of data transmission apparatus embodying this invention;
Fig. 3 is a set of diagrams illustrating data envelopes and multiplex frames that can be used in the apparatus shown in Fig. 2;
Fig~ 4 is a block circuit diagram o~ the transmitting end of a multiplex axrangement used in the c~ apparatus shown in Fig. 2; and Fig. 5 is a block circuit diagram of the receiving end of the multiplex arrangement.
In the portion of a known data transmission arrangement illustrated in Fig. 1, items o~ data are transmitted from a plurality of terminal devices E,El to En via data channels K,K1 to Kn. The terminal device E
is directly connected, for example by means of its data channel K in the orm of a subscriber line, to a main node HK of a synchronous data network which node is itself connected to a trunk line FL. The terminal devices El to En are connected via the data channels Kl to Kn to a 1 ~63385 peripheral node PK and via a trunk line FLl to the main node HK. The peripheral node PK and the main node HK
comprise, for example, components of a t.d.m. system in a synchronous data network. The terminal devices E,El to En include connecting devices which combine the data character-wise and form envelopes. For example each six data bits are provided with two control bits, namely one synchronising bit and one status bit. It can be seen that the terminal devices E,El to En illustrated in Fig. 1 are connected via separate respective lines to the main node HK and to the peripheral node PK.
In the apparatus illustrated in Fig. 2 and embodying this invention, between terminal devices El to En and peripheral node PK there is provided a multiplex arrangement MX which, at each end, consists of a multiplexer Ml,M2 and a demultiplexer Dl,D2. Only one sin~le connecting line AM is required between the multiplexers and the de-multiplexers.
In Fig. 3 there is shown in line a) a ; 20 plurality of envelopes ENl to EN4 which each consist of data bits Dll to D22 and control bits S and A. Each envelope may, for example, contain a group of six data bits D. The control bits are ormed by one status bit S and one synchronising bit A. The envelopes EN1 to EN4 are assigned to the terminal devices El and E2 (for example) and are transmitted via the data channels Kl and K2. The groups of data bits Dll and D12 are transmitted via the channel Kl, ~ 1~338~
whereas the groups of data bits D21 and D22 are transmitted via the channel X2.
Line b) in Fig. 3 represents a multiplex frame MR which is produced by the multiplex arrangement MX. The multiplex frame MR is formed from the groups of data bits Dll to D22 of the envelopes ENl to EN4, the status bits S
of the envelopes ENl to EN4, and four assignment bits ~
which determine the assignment of the groups of data bits Dll to D22 to the data channels Kl and K2 and which make possible the synchronisation of the multiplex frame MR.
For the formation of the multiplex frame MR, the synchronising bits A of the envelopes ENl to EN4 are stripped off in the multiplex device MX and, in accordance with the synchronisation criteria of the multiplex device MX, assignment bits Z are produced instead and are inserted in place of the synchron-isi~g bits A. At the receiving end (D2 in arrangement MX), when the data bits Dll to D22 of the multiplex frame MR are distributed between the envelopes ENl to EN4 assigned to the data channels Kl and K2, these assignment bits Z are again stripped off and new synchronising bits A are produced and are attached to the data bits Dll to D22 in addition to the status bits S.
The substitution of the four synchronising bits A by four new assignment bits has the advantage that now, corresponding to the two channels, not only two identical synchronising bits but four~assignment bits suitable for assignment are available.
~ ~338$
In Fig. 3 c) there is shown a multiplex frame which differs rom the multiplex frame illustrated in line b) in that the number of the status bits S has been reduced in favour of the assignment bits Z in order to achieve a synchronisation of the multiplex frame which is better than in the case illustrated in line b).
The multiplex frame shown in line d) is basically the same as that illustrated in line c), except that the assignment bits Z have been insertedr as assignment bits Zl to Z3, between the groups of data bits Dll to D22 in order to achieve a substantially uniform distribution of the assignment bits Z.
Referring to Fig. 4 it has been assumed that the multiplexer of the multiplex arrangement MX produces a multiplex frame MR which corresponds to the multiplex frame , MR illustrated in line b) in Fig. 3. In dependence upon a multiplex clock pulse train TM a clock pulse generator TGl produces a transmitting clock pulse train ST which is supplied to the terminal devices El and E2 (not shown in Fig. 4). The texminal devices El and E2 transmit items of data SDl and SD2 to respective shift registers Rl and R2.
With the aid of clock pulses Tl from the clock pulse generator TGl, the items of transmitted data SDl and SD2 are input in serial fashion into the shift registers R1 and R2.
The outputs of the shift registers Rl and R2 are connected to a synchronising stage SYl which is controlled by means of clock pulses T2. If a complete envelope is stored in ,.
t :1~3385 one of the registers Rl or R2, the data bits Dll to D22 and the status bits S are input as signals Dl and D2 respectively into intermediate stores ZSl and ZS2 respectively under the control of clock pulses TEl to TE4 produced in the synchronising device SYl. Firstly the envelopes ENl and EN2 are input into the registers Rl and R2. Then the envelopes EN3 and EN4 are input so that then the multiplex rame MR is complete. The synchronising device SYl produces the assignment bits Z which determine the assignment of the data bits Dll to D22 in the multiplex frame MR to the data channels Kl and K2. These assignment bits Z, the status bits S, and the data bits Dll to D22 are consecutively'input into a shift register SRl with the aid of clock pulses T3. Then they are read out in serial fashion ~ 15 from the shift register SRl using clock pulses T4, are inter-C; mediately stored in a flip-flop Fl, and are transmitted ~ia the connecting line AM, as transmitted data SM, to the appropriate demultiplexer.
The demultiplexer illustrated in Fig. 5 contains a shift register SR2 which corresponds to the shit register SRl shown in Fig. 4 and the serial input of the regis~er SR2 is supplied with data signals EM which correspond to the data signals SM. From the clock pulses TM a clock pulse generator TG2 produces clock pulses T5 with the aid of which the data signals EM are input in serial fashion into the shift register SR2. The assignment bits Z are conducted to a synchronising device SY2 which recognises ~ ~33~5 the complete multiplex frame MR. With the aid of clock pulses T6 the synchronising device SY2 produces synchron-ising bits A and clock pulses RT by means of which the synchronising bits A, the status bits S and the data bits Dll to D22 are consecutively input into shift registers R3 and R4~ Thus the envelopes ENl to EN4 assigned to the terminal devices El and E2 are stored consecutively in ... .
( these shift registers R3 and R4. With the aid of clock pulses T7 from the clock pulse generator TG2, the shift registers R3 and R4 are read out in serial fashion and the envelopes ENl to EN4 are returned to the appropriate ones of the data channels Kl and K2 via flip-flops F2 and F3 as received data EDl and ED2. At the same time the clock pulse generator TG2 produces clock pulses ET assigned to the received data EDl and ED2.
On the side of the multiplex arrangement MX
directly associated with the data network, a further intermediate store can be inserted in the demultiplexer between the shift register SR2 and the shift registers R3 and R4 in order to achieve adaptation to the timing provided by a node pulse train of the data networkO
The embodiments described above have the advantage that the substitution of some of the control.bits . with the assignment bits means that in a simple manner, and without the use of additional bits, it is possible to synchronise the multiplex frames and to redistribute the data bits of the multiplex frames between the data channels.
This requires only a low outlay and can be used advantageously particularly when there is only a small number of subscribers.
.
.
t 1~;338~
information for the data terminal devices.
As regards the formation of the envelopes, in accordance with CCITT
X.50, two stnlctures are known, namely a 6-~2 structure and an 8~2 structure.
In the former case the envelopes are formed from six data bits, one synchronis-ing bit, and one status bit. In the latter case the envelopes are formed from eight data bits, one synchronising bit and one status bit. Since, during the transmission of data from the subscriber station, the formation of the envelop-es takes place in the connecting devices, the envelopes are transmitted via the subscriber connection lines to the assigned exchange. As a result of the additional control bits, the gross bit Elow which is to be transmitted is 30%
or 25% higher than the net bit flow between the terminal device and the connect-ing device.
Known connecting devices which operate with one channel can exchange data only with one terminal device. It is conceivable to precede a connecting deyice with an interface multipler, although such an arrangement would have the disadvantage that during a predetermined length of time only one data terminal device can emit data to the data network.
From our German specification AS 28 28 602 published Dec. 13, 1979, it is known to use the envelope itself as a multiplex frame. In this case the individual data ~its of the envelope are assigned to various data channels.
The assignment of the data channels to the data bits is effected by means of ~ !16.~3~
. .
control bits of the envelopes.
It would also be conceivable to connect a -; plurality of data terminal devices via a channel divider which, in accordance with a known t.d.m. process, connects the terminal devices to the data network. When a ; conventional t.d.m. process is used, here again additional ` ! synchronising devices are required to establish the correct assignment between the data channels at the transmitting subscriber station and at the receiving subscriber station.
Thus an arrangement of this kind would have the disadvantage that it necessitates a relatively high initial outlay which is not viable unless a large number of data channels are provided. Furthermore additional bits have to be inserted to characterise the assignment of the individual envelopes to the data channels.
,~ According to a fixst aspect of this invention ~,,, there is provided a method o transmitting data in a synchronous data network in which a plurality of terminal devices supplying data envelopes including control bits are to be connected to the remainder of the data network via a t.d.m. link, said method including the steps of, at the transmitting end, forming a multiplex frame from a plurality of the data envelopes supplied via a plurality of input data channels, substituting for some of the control bits, assignment bits indicating the assignment of the data bits in each multiplex frame to the input data channels, and at the receiving end, using the received ~ 1~333~
assignment bits to allocate the associated data bits to envelopes in respective corresponding output data channels and reproducing the substituted control bits and reinserting them into the appropriate envelopes.
According to a second aspect of this invention - there is provided apparatus for transmitting data in a '~ synchronous data network in which a plurality of terminal ; devices supplying data envelopes including control bits are to be connected to the remainder of the data network via a t.d.m. link, said apparatus comprising transmitting means arranged to form a multiplex frame from a plurality of the data envelopes supplied via a plurality of input data channels, means for substituting for some of the control bits, assignment bits indicating the assignment of the data bits in each multiplex frame to the input data channelsl and receiving means arranged for using the received assign-~, ment bits to allocate the associated data bits to envelopes in respective corresponding output data channels, means for reproducing the substituted control bits and means for reinserting them into the appropriate envelopes.
A particularly low outlay is required when the control bits substituted by the assignment bits are synchronising bits, and those control bits comprising status bits are trans~erred unaltered into the multiplex frame.
If the synchronisation of the multiplex frame requires more assignment bits than synchronising bits are available in the envelopes, it is favourable that the i l~3385 control bits s~stituted by the assignment bits comprise synchronising bits and some status bits and the remainder of the status bits are transferred unaltered into the multiplex frame.
It is possible to contrive the multiplex frame to be such that the data bits are arranged ` consecutively in the multiplex frame. However it can also be advantageous for the assignment bits to be distributed in the multiplex frame between data bits.
In one embodiment of the apparatus the transmitting means comprises a number of shift registers corresponding to the number of input data channels and into which the envelopes of the input data channels are respectively input in serial fashion, a synchronising stage which is connected to parallel outputs of the shift C registers and which produces the assignment bits and a further shift register into whi~h the data bits of the envelopes, the assignment bits and the remainder of the control bits are input in parallel a~d which emits the multiplex frames from its serial output.
The receiving means may include a shift register into which the received multiplex frames are input in serial fashion, a synchronising stage to which the assignment bits of the multiplex ~rame are supplied and which reproduces the substituted control bits of the envelopes, and a num~er of further shift registers correspondin~ to the number of output data channels and ~ ~338~
which are supplied with the data bits and the control bits and which at their serial outputs emit the envelopes assigned to the respective output data channels.
Embodiments of this invention will now be described, by way of example, with reerence to the accompanying drawings in which:
Fig. 1 is a block circuit diagram of a part of a known data transmission apparatus;
Fig. 2 is a block circuit diagram of data transmission apparatus embodying this invention;
Fig. 3 is a set of diagrams illustrating data envelopes and multiplex frames that can be used in the apparatus shown in Fig. 2;
Fig~ 4 is a block circuit diagram o~ the transmitting end of a multiplex axrangement used in the c~ apparatus shown in Fig. 2; and Fig. 5 is a block circuit diagram of the receiving end of the multiplex arrangement.
In the portion of a known data transmission arrangement illustrated in Fig. 1, items o~ data are transmitted from a plurality of terminal devices E,El to En via data channels K,K1 to Kn. The terminal device E
is directly connected, for example by means of its data channel K in the orm of a subscriber line, to a main node HK of a synchronous data network which node is itself connected to a trunk line FL. The terminal devices El to En are connected via the data channels Kl to Kn to a 1 ~63385 peripheral node PK and via a trunk line FLl to the main node HK. The peripheral node PK and the main node HK
comprise, for example, components of a t.d.m. system in a synchronous data network. The terminal devices E,El to En include connecting devices which combine the data character-wise and form envelopes. For example each six data bits are provided with two control bits, namely one synchronising bit and one status bit. It can be seen that the terminal devices E,El to En illustrated in Fig. 1 are connected via separate respective lines to the main node HK and to the peripheral node PK.
In the apparatus illustrated in Fig. 2 and embodying this invention, between terminal devices El to En and peripheral node PK there is provided a multiplex arrangement MX which, at each end, consists of a multiplexer Ml,M2 and a demultiplexer Dl,D2. Only one sin~le connecting line AM is required between the multiplexers and the de-multiplexers.
In Fig. 3 there is shown in line a) a ; 20 plurality of envelopes ENl to EN4 which each consist of data bits Dll to D22 and control bits S and A. Each envelope may, for example, contain a group of six data bits D. The control bits are ormed by one status bit S and one synchronising bit A. The envelopes EN1 to EN4 are assigned to the terminal devices El and E2 (for example) and are transmitted via the data channels Kl and K2. The groups of data bits Dll and D12 are transmitted via the channel Kl, ~ 1~338~
whereas the groups of data bits D21 and D22 are transmitted via the channel X2.
Line b) in Fig. 3 represents a multiplex frame MR which is produced by the multiplex arrangement MX. The multiplex frame MR is formed from the groups of data bits Dll to D22 of the envelopes ENl to EN4, the status bits S
of the envelopes ENl to EN4, and four assignment bits ~
which determine the assignment of the groups of data bits Dll to D22 to the data channels Kl and K2 and which make possible the synchronisation of the multiplex frame MR.
For the formation of the multiplex frame MR, the synchronising bits A of the envelopes ENl to EN4 are stripped off in the multiplex device MX and, in accordance with the synchronisation criteria of the multiplex device MX, assignment bits Z are produced instead and are inserted in place of the synchron-isi~g bits A. At the receiving end (D2 in arrangement MX), when the data bits Dll to D22 of the multiplex frame MR are distributed between the envelopes ENl to EN4 assigned to the data channels Kl and K2, these assignment bits Z are again stripped off and new synchronising bits A are produced and are attached to the data bits Dll to D22 in addition to the status bits S.
The substitution of the four synchronising bits A by four new assignment bits has the advantage that now, corresponding to the two channels, not only two identical synchronising bits but four~assignment bits suitable for assignment are available.
~ ~338$
In Fig. 3 c) there is shown a multiplex frame which differs rom the multiplex frame illustrated in line b) in that the number of the status bits S has been reduced in favour of the assignment bits Z in order to achieve a synchronisation of the multiplex frame which is better than in the case illustrated in line b).
The multiplex frame shown in line d) is basically the same as that illustrated in line c), except that the assignment bits Z have been insertedr as assignment bits Zl to Z3, between the groups of data bits Dll to D22 in order to achieve a substantially uniform distribution of the assignment bits Z.
Referring to Fig. 4 it has been assumed that the multiplexer of the multiplex arrangement MX produces a multiplex frame MR which corresponds to the multiplex frame , MR illustrated in line b) in Fig. 3. In dependence upon a multiplex clock pulse train TM a clock pulse generator TGl produces a transmitting clock pulse train ST which is supplied to the terminal devices El and E2 (not shown in Fig. 4). The texminal devices El and E2 transmit items of data SDl and SD2 to respective shift registers Rl and R2.
With the aid of clock pulses Tl from the clock pulse generator TGl, the items of transmitted data SDl and SD2 are input in serial fashion into the shift registers R1 and R2.
The outputs of the shift registers Rl and R2 are connected to a synchronising stage SYl which is controlled by means of clock pulses T2. If a complete envelope is stored in ,.
t :1~3385 one of the registers Rl or R2, the data bits Dll to D22 and the status bits S are input as signals Dl and D2 respectively into intermediate stores ZSl and ZS2 respectively under the control of clock pulses TEl to TE4 produced in the synchronising device SYl. Firstly the envelopes ENl and EN2 are input into the registers Rl and R2. Then the envelopes EN3 and EN4 are input so that then the multiplex rame MR is complete. The synchronising device SYl produces the assignment bits Z which determine the assignment of the data bits Dll to D22 in the multiplex frame MR to the data channels Kl and K2. These assignment bits Z, the status bits S, and the data bits Dll to D22 are consecutively'input into a shift register SRl with the aid of clock pulses T3. Then they are read out in serial fashion ~ 15 from the shift register SRl using clock pulses T4, are inter-C; mediately stored in a flip-flop Fl, and are transmitted ~ia the connecting line AM, as transmitted data SM, to the appropriate demultiplexer.
The demultiplexer illustrated in Fig. 5 contains a shift register SR2 which corresponds to the shit register SRl shown in Fig. 4 and the serial input of the regis~er SR2 is supplied with data signals EM which correspond to the data signals SM. From the clock pulses TM a clock pulse generator TG2 produces clock pulses T5 with the aid of which the data signals EM are input in serial fashion into the shift register SR2. The assignment bits Z are conducted to a synchronising device SY2 which recognises ~ ~33~5 the complete multiplex frame MR. With the aid of clock pulses T6 the synchronising device SY2 produces synchron-ising bits A and clock pulses RT by means of which the synchronising bits A, the status bits S and the data bits Dll to D22 are consecutively input into shift registers R3 and R4~ Thus the envelopes ENl to EN4 assigned to the terminal devices El and E2 are stored consecutively in ... .
( these shift registers R3 and R4. With the aid of clock pulses T7 from the clock pulse generator TG2, the shift registers R3 and R4 are read out in serial fashion and the envelopes ENl to EN4 are returned to the appropriate ones of the data channels Kl and K2 via flip-flops F2 and F3 as received data EDl and ED2. At the same time the clock pulse generator TG2 produces clock pulses ET assigned to the received data EDl and ED2.
On the side of the multiplex arrangement MX
directly associated with the data network, a further intermediate store can be inserted in the demultiplexer between the shift register SR2 and the shift registers R3 and R4 in order to achieve adaptation to the timing provided by a node pulse train of the data networkO
The embodiments described above have the advantage that the substitution of some of the control.bits . with the assignment bits means that in a simple manner, and without the use of additional bits, it is possible to synchronise the multiplex frames and to redistribute the data bits of the multiplex frames between the data channels.
This requires only a low outlay and can be used advantageously particularly when there is only a small number of subscribers.
Claims (10)
1. A method of transmitting data in a synchronous data network in which a plurality of terminal devices supplying data envelopes including control bits are to be connected to the remainder of the data network via a t.d.m. link, said method including the steps of, at the transmitting end, forming a multiplex frame from a plurality of the data envelopes supplied via a plurality of input data channels, substituting for some of the control bits, assignment bits indicating the assignment of the data bits in each multiplex frame to the input data channels, and at the receiving end, using the received assignment bits to allocate the associated data bits to envelopes in respective corresponding output data channels and reproducing the substituted control bits and reinserting them into the appropriate envelopes.
2. A method as claimed in claim 1, wherein the control bits substituted by the assignment bits are synchronising bits and those control bits comprising status bits are transferred unaltered into the multiplex frame.
3. A method as claimed in claim 1, wherein the control bits substituted by the assignment bits comprise synchron-ising bits and some status bits and the remainder of the status bits are transferred unaltered into the multiplex frame.
4. A method as claimed in any one of claims 1 to 3, wherein the data bits are arranged consecutively in the multiplex frame.
5. A method as claimed in any one of claims 1 to 3, wherein the assignment bits are distributed in the multiplex frame between data bits.
6. Apparatus for transmitting data in a synchronous data network in which a plurality of terminal devices supplying data envelopes including con-trol bits are to be connected to the remainder of the data network via a t.d.m.
link, said apparatus comprising transmitting means arranged to form a multiplex frame from a plurality of the data envelopes supplied via a plurality of input data channels, means for substituting for some of the control bits, assignment bits indicating the assignment of the data bits in each multiplex frame to the input data channels, and receiving means arranged for using the received assign-ment bits to allocate the associated data bits to envelopes in respective corresponding output data channels, means for reproducing the substituted control bits and means for reinserting them into the appropriate envelopes.
link, said apparatus comprising transmitting means arranged to form a multiplex frame from a plurality of the data envelopes supplied via a plurality of input data channels, means for substituting for some of the control bits, assignment bits indicating the assignment of the data bits in each multiplex frame to the input data channels, and receiving means arranged for using the received assign-ment bits to allocate the associated data bits to envelopes in respective corresponding output data channels, means for reproducing the substituted control bits and means for reinserting them into the appropriate envelopes.
7. Apparatus according to claim 6, said apparatus including a multi-plex arrangement which is connected on the one hand to the terminal devices and on the other hand to the remainder of the data network.
8. Apparatus as claimed in claim 6, wherein the transmitting means comprises a number of shift registers corresponding to the number of input data channels and into which the envelopes of the input data channels are respectively input in serial fashion, a synchronising stage which is connected to parallel outputs of the shift registers and which produces the assignment bits and a further shift register into which the data bits of the envelopes, the assignment bits and the remainder of the control bits are input in parallel and which emits the multiplex frames from its serial output.
9. Apparatus as claimed in claim 6 wherein the receiving means includes a shift register into which the received multiplex frames are input in serial fashion, a synchronising stage to which the assignment bits of the multiplex frame are supplied and which reproduces the substituted control bits of the envelopes, and a number of further shift registers corresponding to the number of output data channels and which are supplied with the data bits and the control bits and which at their serial outputs emit the envelopes assigned to the respective output data channels.
10. A synchronous data network in which a plurality of terminal devices supplying data envelopes including control bits are to be connected to the re-mainder of the data network via a t.d.m. link, said network including apparatus according to claim 6.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DEP3002929.9 | 1980-01-28 | ||
| DE19803002929 DE3002929A1 (en) | 1980-01-28 | 1980-01-28 | METHOD AND CIRCUIT ARRANGEMENT FOR TRANSMITTING DATA IN A SYNCHRONOUS DATA NETWORK |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1163385A true CA1163385A (en) | 1984-03-06 |
Family
ID=6093074
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000369294A Expired CA1163385A (en) | 1980-01-28 | 1981-01-26 | Method of and apparatus for transmitting data in a synchronous data network |
Country Status (6)
| Country | Link |
|---|---|
| EP (1) | EP0033122A1 (en) |
| AU (1) | AU6662081A (en) |
| BR (1) | BR8100445A (en) |
| CA (1) | CA1163385A (en) |
| DE (1) | DE3002929A1 (en) |
| NO (1) | NO810259L (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3248566C2 (en) * | 1982-12-30 | 1986-08-21 | Philips Kommunikations Industrie AG, 8500 Nürnberg | Method and circuit arrangement for the transmission of data signals |
| JPH0681113B2 (en) * | 1987-09-21 | 1994-10-12 | 日本電気株式会社 | Time division multiplex wireless communication system |
| US5784362A (en) * | 1995-04-17 | 1998-07-21 | Telefonaktiebolaget Lm Ericsson | Temporary frame identification for ARQ in a reservation-slotted-ALOHA type of protocol |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2652038C2 (en) * | 1976-11-15 | 1978-10-26 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | System for the central generation of an envelope interleaved time division multiplex signal |
| DE2727912C2 (en) * | 1977-06-21 | 1979-03-29 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Method for the transmission of data and switching criteria between the subscribers and a switching office of a data network for time division multiplex transmission |
| DE2828602C2 (en) * | 1978-06-29 | 1983-02-24 | Siemens AG, 1000 Berlin und 8000 München | Method for transmitting data in a synchronous data network |
-
1980
- 1980-01-28 DE DE19803002929 patent/DE3002929A1/en not_active Withdrawn
-
1981
- 1981-01-20 EP EP81100392A patent/EP0033122A1/en not_active Withdrawn
- 1981-01-26 NO NO810259A patent/NO810259L/en unknown
- 1981-01-26 CA CA000369294A patent/CA1163385A/en not_active Expired
- 1981-01-27 BR BR8100445A patent/BR8100445A/en unknown
- 1981-01-27 AU AU66620/81A patent/AU6662081A/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| AU6662081A (en) | 1981-08-06 |
| EP0033122A1 (en) | 1981-08-05 |
| BR8100445A (en) | 1981-08-11 |
| NO810259L (en) | 1981-07-29 |
| DE3002929A1 (en) | 1981-07-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5103447A (en) | High-speed ring LAN system | |
| US4805165A (en) | Time division multiplex data transmission method and apparatus | |
| KR920004129B1 (en) | Channel selection in a switching system having clustered remote switching modules | |
| FI58416B (en) | REFERENCE TO A MULTIPLEXERING AV SIGNALER I EN TERMINAL VID ETT TIDSMULTIPLEXSYSTEM | |
| JPH0648870B2 (en) | Optical communication network and method of synchronizing optical communication network | |
| JPH06284141A (en) | Bi-directional transmission line changeover ring network | |
| US5757806A (en) | Data multiplexing system having at least one low-speed interface circuit connected to a bus | |
| JPS6120443A (en) | Tdma-1 ground point pair multipoint communication system | |
| GB2092412A (en) | Method and apparatus for distributing control signals | |
| CA1242264A (en) | Switching system having capability for telecommunication conferences | |
| CA1163385A (en) | Method of and apparatus for transmitting data in a synchronous data network | |
| GB1331547A (en) | Multiplexing and demultiplexing system for telegrphic or data transmission channels | |
| US3602647A (en) | Control signal transmission in time division multiplex system communications | |
| US5430708A (en) | Control channel terminating interface and its testing device for sending and receiving signal | |
| JP2889027B2 (en) | Time division switch and connection module constituting such switch | |
| CA1168392A (en) | Data transmission | |
| US4953158A (en) | Switch system for circuit and/or packet-switched communications | |
| US6285687B1 (en) | Timing system and method for distributing a timing signal | |
| US4769809A (en) | Method of and circuit arrangement for through-switching broadband digital signals without phase jump in a synchronous broadband communication network | |
| JPS62193495A (en) | Switching device for transmission of digital signal such as pcm signal | |
| US6700892B1 (en) | Communication system for E1/T1 | |
| US5892771A (en) | System for establishing a TDM information protocol over a communications path | |
| US4160126A (en) | Modular multiplex/demultiplex apparatus | |
| JP2878073B2 (en) | Data transmission method and system | |
| JP2000022723A (en) | Transmitter, data multiplexer demultiplexer and cross connector |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |