CA1163020A - High voltage semiconductor device having improvements to the dv/dt capability and plasma spreading - Google Patents
High voltage semiconductor device having improvements to the dv/dt capability and plasma spreadingInfo
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- CA1163020A CA1163020A CA000377573A CA377573A CA1163020A CA 1163020 A CA1163020 A CA 1163020A CA 000377573 A CA000377573 A CA 000377573A CA 377573 A CA377573 A CA 377573A CA 1163020 A CA1163020 A CA 1163020A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 230000007480 spreading Effects 0.000 title abstract description 5
- 230000006872 improvement Effects 0.000 title description 4
- 238000001465 metallisation Methods 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 14
- 230000000737 periodic effect Effects 0.000 claims description 5
- 230000005855 radiation Effects 0.000 claims description 2
- 239000003990 capacitor Substances 0.000 abstract description 8
- 230000001052 transient effect Effects 0.000 description 18
- 238000000034 method Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 230000035945 sensitivity Effects 0.000 description 3
- 238000006731 degradation reaction Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000013011 mating Effects 0.000 description 2
- 235000007253 Trigonella corniculata Nutrition 0.000 description 1
- 240000004336 Trigonella corniculata Species 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- QHGVXILFMXYDRS-UHFFFAOYSA-N pyraclofos Chemical compound C1=C(OP(=O)(OCC)SCCC)C=NN1C1=CC=C(Cl)C=C1 QHGVXILFMXYDRS-UHFFFAOYSA-N 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/7302—Bipolar junction transistors structurally associated with other devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/7404—Thyristor-type devices, e.g. having four-zone regenerative action structurally associated with at least one other device
- H01L29/7408—Thyristor-type devices, e.g. having four-zone regenerative action structurally associated with at least one other device the device being a capacitor or a resistor
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Abstract
HIGH VOLTAGE SEMICONDUCTOR DEVICE HAVING
IMPROVEMENTS TO THE dv/dt CAPABILITY
AND PLASMA SPREADING
Abstract of the Disclosure A semiconductor device used for high voltage applications exhibits reduced susceptibility to being inadvertently turned on by capacitive charging currents generated by relatively high voltage transients impressed across an anode and a cathode of the device. The capacitive charging currents are manifested as gate currents which in a thyristor render the device conductive it they exceed a critical valve, and in a transistor are multiplied by the current gain. A capacitor integral with the semiconductor device structure is coupled to a gate region of the device to divert a portion of transient-generated capacitive charging currents, thereby reducing the associated gate currents and improving the dv/dt capability of the device.
IMPROVEMENTS TO THE dv/dt CAPABILITY
AND PLASMA SPREADING
Abstract of the Disclosure A semiconductor device used for high voltage applications exhibits reduced susceptibility to being inadvertently turned on by capacitive charging currents generated by relatively high voltage transients impressed across an anode and a cathode of the device. The capacitive charging currents are manifested as gate currents which in a thyristor render the device conductive it they exceed a critical valve, and in a transistor are multiplied by the current gain. A capacitor integral with the semiconductor device structure is coupled to a gate region of the device to divert a portion of transient-generated capacitive charging currents, thereby reducing the associated gate currents and improving the dv/dt capability of the device.
Description
~ RD~865 HIGH VOLTAGE SEMICONDUCTOR DEVICE HAVING
IMPROVEMENTS TO THE dv/dt CAPABILITY
AND PLASMA SPREADING
Related Patents This application is related to V.A.K. Tample United States Patent Number 4,261,000 issued April 7, 1981, and to V.A.K. Temple United States Patent Number 4,261,001 issued April 7, 1981, both of which are assigned to the instant assignee.
Background of the Invention This invention relates to semiconductor switch-ing devices, and more particularly, to high voltage semiconductor switching devices having reduced suscepti-bility to inadvertent device turn-on due to high voltage transients.
Thyristors, triacs and transistors are ; semiconductor devices often used to turn~on and turn-off high voltage sources. These devices include at least first and second main current carrying electrodes and a gate electrode. A main vol-tage is applied across the first and second electrodes, such that a main current flows therebetween upon application of a control signal to the gate electrode. The device is said to be in a turned-on state when conduction current flows between the first and second electrodes. Because the device has an internal junction capacitance, its forward-blocking capability is sensistive to the rate at which a forward voltage is applied to its main terminals. A steeply rising voltage impressed across the main terminals may cause a capacitive charging current to flow through the device. The charging ~r~. 1 ~
current (i=C,dv/dt) is a function of the inherent junction capacitive value and the rate of rise of the impressed voltage. If the rate of rise of impressed voltage exceeds a critical value, the capacitive charging current may be large enough to generate a gate current at a sufficient level and for a sufficient time to turn-on the device. The ability of the device to withstand an impressed voltage transient across its main terminals is commonly termed the dv/dt capability specified in volts/microseconds. The dv/dt capability becomes of particular importance when voltage transients are impressed across the main terminals of the device.
Voltage transients occur in electrical systems when some disturbance disrupts the normal operation of the system or even in normal circuit operation when other devices in the system switch on or off. Voltage transients generally have a fast rate of rise that may be greater than the dv/dt capability of the device.
If the rate of rise of the transient exceeds the dv/dt capability of the thyristor, for example, it may cause the device to be inadvertently turned-on.
There are a number of known methods for increasing the dv/dt capability of the semiconductor device.
One such method is the use of "emitter shorts" in a relatively large emitter area of a semiconductor device.
Disadvantages that may occur with the use of emitter shorts are that the gate current required to activate the semiconductor device is increased and the di/dt rating of the device is also decreased.
Another known method of improving the dv/dt capabil-~3~2~
ity of the semiconductor device is the use of inter-digitation. Interdigitation increases the initial turn-on area of the emitters and correspondingly reduces the turn-on sensitivity of the device to gate current.
The interdigitation approach raises problems related to packaging as well as increasing gate current requirements.
A still further known method of increasing the dv/dt capabiIity of the semiconductor device is the use of a resistor connected between the gate and the cathode of the semiconductor device, which provides a shunt path to divert a portion of the transient generated gate current away from the emitter of the cathode. The use of a resistive shunt path for the gate signal reduces the gate sensitivity of the semiconductor device as well.
The present invention concerns a high voltage semiconductor device in which the dv/dt capability ; of the device is increased by decreasing the amount of the transient capacitive charging currents conducted to the emitters of the device.
One object of the present invention is to provide circuit means externally connected to the semiconductor device to cause a re].atively large increase in the dv/dt rating of the device but with a relatively small decrease in gate sensitivity.
Another object of the present invention is to provide a semiconductor device ir which means are incor-porated for increasing the dv/dt rating of the device with but minimal effect on the other parameters o~
the device.
RD-8~54 A still further object of the present invention is to provide a semiconductor device in which the speed of a plasma created upon initial turn-on of the device is increased~
These and other objects of the invention will become apparent to those skilled in the art upon consid-eration of the following description of the invention.
Summary of the Invention In accordance with one preferred embodiment of the invention, a high voltage semiconductor device comprises at least a first cathode including a first metallization layer, a second cathode including a second metallization layer, an anode, and a gate region adapted to receive an applied signal. Each of the first and second cathodes has an emitter layer affixed thereunder and each cathode is separated from the anode by at least a first and second layer of alternating conductivity-type material. The second cathode and the anode are ; adapted to be coupled between opposite ends of a relatively high voltage potential source having periodic relatively high voltage transients. Periodic occurrences of the voltage transients between the second cathode and the anode generate capacitive charging currents within the first and second layers which are manifested as gate current ln the emitter layers of the first and second cathodes. The gate current in the emitter layer of the first cathode, if unreduced in amplitude, is of a sufficient value to cause conduction between the first cathode and the anode. The high voltage semiconductor Z~
device further comprises capacitive means coupled to the gate region to provide a capacitive shunt path for diverting a portion of transient generated capacitive charging current flowing within the gate region away from the emitter layer o~ the first cathode and that part of the first layer lying thereunder, such that the transient generated capacitive charging currents which are manifested as the gate current are reduced, thereby improving the dv/dt capability of the high voltage semiconductor device.
The features of the invention believed to be novel are set forth with particularity in the appended claims.
The invention, itself~ however, both as to its organization and operation, together with further objects and advantages thereof, may best be understood by reference to the following description taken in conjunction with the accompanying drawings.
Description of the Drawings Figure 1 illustrates a partial cross-section of one preferred embodiment of the present invention in which an impedance is employed to provide a shunt path for transient gate current; and Figure 2 is a partial cross-sectional view of a center-gated amplifying gate thyristor of the present invention in which internally insulative layers are employed to increase the dv/dt rating of the device.
Detailed Description of the Preferred Embodiment Figure 1 shows a partial cross-section of a semicon-ductor device 10 in a center-gated amplifying thyristor Z~
configuration exemplifying one embodiment of the present invention. Device 10 has an anode base layer 16 of an N-type semiconductor material and a P-type semiconductor material forming a layer 18 which is situated beneath and in contact with the layer 16. A cathode-base layer 14 of P-type semiconductor material is situated above and-in contact with the layer 16. Layers 14 and 16 have a beveled surface 38 located at their outer peripheries for improved avalanche breakdown voltage. Semiconductor layer 14 furnishes a major portion of a top surface 19 of the semiconductor device 10. Semiconductor layer J~
~& generally constitutes the substrate of the device 10 with layers 14 and 18 being formed by diffusion and/or epitaxial growth. Device 10 includes a pilot thyristor 13 and a main thyristor 28 each having an additional high conductivity n~ layer shown respectively as 15 and as 17. The n-~ layer 15 constitutes the emitter of the pilot thyristor 13. Similarly, the n~ layer 17 constitutes the emitter of the main thyristor 28.
The emitter 15 is overlaid with a metallization layer 26, herein termed the pilot stage cathode electrode or first cathode electrode. Similarly, the emitter 17 is overlaid with a metallization layer 30, herein termed the main stage cathode electrode or second cathode ~5 electrode. Emitter 15 and layer 26 comprise the pilot stage cathode while emitter 17 and layer 30 comprise the main stage cathode.
Metallization layer 30 provides a contact for connecting one end of a relatively high voltage source Z~
~D-8654 via terminal 34. Metallization layers 26 and 30, if desired, have conventional emitter shorts 32 formed in their top portions and extending into region 14.
A further metallization layer 24, herein termed the gate of device lO, overlays cathode-base layer 14.
Gate 24 may be connected to an electrical gate signal source via terminal 22. In one form of a photo-sensitive amplifying gate thyristor 10 a light signal may impinge upon part or all of gate region 47. For this purpose, electrode 24 ls selected to be transparent to the incident light radiation, or maintained with small area to allow '~' 3~ sufficient light to impinge on surface-~ in gate region 47 in order to trigger the device.
A still further metallization layer 20 is positioned under layer 18 and provides a means for connecting the other end of the high voltage source to the device 10 via terminal 36. Metallization layer 20 is herein termed the anode of device 10.
Semiconductor device 10, as shown in Figure 1, includes a gate region 47 extending from a centerline 12 to a leading edge, or turn on line, 70 of pilot thyristor 13, a pilot thyristor region 49 extending from the termination of gate region 47 to the termination of emitter 15 of pilot thyristor 13, and a main thyristor region 51 beginning at a turn-on line 80 and spanning the emitter 17 of the main thyristor 28. The leading edge of the pilot thyristor on the side closest to gate region 47, and thereby being leading relative to the gate region.
As previously discussed, occurrences of voltage li63~
transients impressed across the cathode and anode of a semiconductor device, such as device 10, may cause capacitive charging currents to flow within device 10. The capacitive charging currents are shown in Figure 1 as a plurality of arrows 41 emerging from anode 20 and flowing upward through layers 18, 16, ' and 14 towards the top portion 19 of device 10. A
portion of the transient capacitive charging currents may be manifested as a gate current of sufficient value to exceed a critical value and render the main thyristor 28 conductive, thus inadvertently turning on device 10. Similarly, a portion of the transient generated capacitive charging currents 41 may also intercept and render conductive the pilot thyristor 13, thus also inadvertently turning on device 10.
In the embodiment of Figure l, an impedance means 11 is provided to reduce the susceptibility of device 10 to inadvertent turn on by voltage transients. Reducing.
the susceptibility of inadvertent turn on correspondingly increases the dv/dt capability of device 10.
Impedance means 11 is connected between gate 24 and second cathode electrode 30 to provide a shunt path for a portion of the transient capacitive charging currents. Thus impedance means 11 provides a shunt or parallel path to conduct a portion of the transient generated capacitive charging currents away from emitters 15 and 17, and thereby provides the shunt path for most of the transient capacitive charging currents flowing within gate region 47.
3~D2~
Impedance means 11 is comprised of a capacitor having a substantially non-dissipating energy characteristic and a relatively low impedance to fast transients.
Use of a capacitive shunt increases the dv/dt capability of the semiconductor device but increases the turn-on delay time of device 10, and, in general, somewhat reduces the di/dt rating of device 10. For reasons explained infra, the value of capacitor for impedance means 11 is selected with consideration given to the increased dv/dt capability obtained and also to the resulting increased turn-on delay and correspondingly decreased di/dt rating of device 10.
It will be appreciated that use of capacitive shunt 11 having a low impedance to rapid transient currents diverts a portion of the capacitive charging ; currents 41 away from the emitters 15 and 17 and thereby decreases the dv/dt derived gate current that is applied to the pilot thyristor 13 and main thyristor 28. The gate current as a function of time, herein termed IG(t), is approximately represented by the following relationship:
IG(t) - CJ dv/dt (1-e G ) (l) where CJ = the junction capacitance of the gate region 47;
t - elapsed time during the voltage transient;
CJ dv/dt = the capacitive charging currents generated by the voltage transients;
~G~ = (CJ ~ C11). RGK for the time duration t, wherein C11 = capacitive value of impedance means 11; and R = resistance value between gate electrode
IMPROVEMENTS TO THE dv/dt CAPABILITY
AND PLASMA SPREADING
Related Patents This application is related to V.A.K. Tample United States Patent Number 4,261,000 issued April 7, 1981, and to V.A.K. Temple United States Patent Number 4,261,001 issued April 7, 1981, both of which are assigned to the instant assignee.
Background of the Invention This invention relates to semiconductor switch-ing devices, and more particularly, to high voltage semiconductor switching devices having reduced suscepti-bility to inadvertent device turn-on due to high voltage transients.
Thyristors, triacs and transistors are ; semiconductor devices often used to turn~on and turn-off high voltage sources. These devices include at least first and second main current carrying electrodes and a gate electrode. A main vol-tage is applied across the first and second electrodes, such that a main current flows therebetween upon application of a control signal to the gate electrode. The device is said to be in a turned-on state when conduction current flows between the first and second electrodes. Because the device has an internal junction capacitance, its forward-blocking capability is sensistive to the rate at which a forward voltage is applied to its main terminals. A steeply rising voltage impressed across the main terminals may cause a capacitive charging current to flow through the device. The charging ~r~. 1 ~
current (i=C,dv/dt) is a function of the inherent junction capacitive value and the rate of rise of the impressed voltage. If the rate of rise of impressed voltage exceeds a critical value, the capacitive charging current may be large enough to generate a gate current at a sufficient level and for a sufficient time to turn-on the device. The ability of the device to withstand an impressed voltage transient across its main terminals is commonly termed the dv/dt capability specified in volts/microseconds. The dv/dt capability becomes of particular importance when voltage transients are impressed across the main terminals of the device.
Voltage transients occur in electrical systems when some disturbance disrupts the normal operation of the system or even in normal circuit operation when other devices in the system switch on or off. Voltage transients generally have a fast rate of rise that may be greater than the dv/dt capability of the device.
If the rate of rise of the transient exceeds the dv/dt capability of the thyristor, for example, it may cause the device to be inadvertently turned-on.
There are a number of known methods for increasing the dv/dt capability of the semiconductor device.
One such method is the use of "emitter shorts" in a relatively large emitter area of a semiconductor device.
Disadvantages that may occur with the use of emitter shorts are that the gate current required to activate the semiconductor device is increased and the di/dt rating of the device is also decreased.
Another known method of improving the dv/dt capabil-~3~2~
ity of the semiconductor device is the use of inter-digitation. Interdigitation increases the initial turn-on area of the emitters and correspondingly reduces the turn-on sensitivity of the device to gate current.
The interdigitation approach raises problems related to packaging as well as increasing gate current requirements.
A still further known method of increasing the dv/dt capabiIity of the semiconductor device is the use of a resistor connected between the gate and the cathode of the semiconductor device, which provides a shunt path to divert a portion of the transient generated gate current away from the emitter of the cathode. The use of a resistive shunt path for the gate signal reduces the gate sensitivity of the semiconductor device as well.
The present invention concerns a high voltage semiconductor device in which the dv/dt capability ; of the device is increased by decreasing the amount of the transient capacitive charging currents conducted to the emitters of the device.
One object of the present invention is to provide circuit means externally connected to the semiconductor device to cause a re].atively large increase in the dv/dt rating of the device but with a relatively small decrease in gate sensitivity.
Another object of the present invention is to provide a semiconductor device ir which means are incor-porated for increasing the dv/dt rating of the device with but minimal effect on the other parameters o~
the device.
RD-8~54 A still further object of the present invention is to provide a semiconductor device in which the speed of a plasma created upon initial turn-on of the device is increased~
These and other objects of the invention will become apparent to those skilled in the art upon consid-eration of the following description of the invention.
Summary of the Invention In accordance with one preferred embodiment of the invention, a high voltage semiconductor device comprises at least a first cathode including a first metallization layer, a second cathode including a second metallization layer, an anode, and a gate region adapted to receive an applied signal. Each of the first and second cathodes has an emitter layer affixed thereunder and each cathode is separated from the anode by at least a first and second layer of alternating conductivity-type material. The second cathode and the anode are ; adapted to be coupled between opposite ends of a relatively high voltage potential source having periodic relatively high voltage transients. Periodic occurrences of the voltage transients between the second cathode and the anode generate capacitive charging currents within the first and second layers which are manifested as gate current ln the emitter layers of the first and second cathodes. The gate current in the emitter layer of the first cathode, if unreduced in amplitude, is of a sufficient value to cause conduction between the first cathode and the anode. The high voltage semiconductor Z~
device further comprises capacitive means coupled to the gate region to provide a capacitive shunt path for diverting a portion of transient generated capacitive charging current flowing within the gate region away from the emitter layer o~ the first cathode and that part of the first layer lying thereunder, such that the transient generated capacitive charging currents which are manifested as the gate current are reduced, thereby improving the dv/dt capability of the high voltage semiconductor device.
The features of the invention believed to be novel are set forth with particularity in the appended claims.
The invention, itself~ however, both as to its organization and operation, together with further objects and advantages thereof, may best be understood by reference to the following description taken in conjunction with the accompanying drawings.
Description of the Drawings Figure 1 illustrates a partial cross-section of one preferred embodiment of the present invention in which an impedance is employed to provide a shunt path for transient gate current; and Figure 2 is a partial cross-sectional view of a center-gated amplifying gate thyristor of the present invention in which internally insulative layers are employed to increase the dv/dt rating of the device.
Detailed Description of the Preferred Embodiment Figure 1 shows a partial cross-section of a semicon-ductor device 10 in a center-gated amplifying thyristor Z~
configuration exemplifying one embodiment of the present invention. Device 10 has an anode base layer 16 of an N-type semiconductor material and a P-type semiconductor material forming a layer 18 which is situated beneath and in contact with the layer 16. A cathode-base layer 14 of P-type semiconductor material is situated above and-in contact with the layer 16. Layers 14 and 16 have a beveled surface 38 located at their outer peripheries for improved avalanche breakdown voltage. Semiconductor layer 14 furnishes a major portion of a top surface 19 of the semiconductor device 10. Semiconductor layer J~
~& generally constitutes the substrate of the device 10 with layers 14 and 18 being formed by diffusion and/or epitaxial growth. Device 10 includes a pilot thyristor 13 and a main thyristor 28 each having an additional high conductivity n~ layer shown respectively as 15 and as 17. The n-~ layer 15 constitutes the emitter of the pilot thyristor 13. Similarly, the n~ layer 17 constitutes the emitter of the main thyristor 28.
The emitter 15 is overlaid with a metallization layer 26, herein termed the pilot stage cathode electrode or first cathode electrode. Similarly, the emitter 17 is overlaid with a metallization layer 30, herein termed the main stage cathode electrode or second cathode ~5 electrode. Emitter 15 and layer 26 comprise the pilot stage cathode while emitter 17 and layer 30 comprise the main stage cathode.
Metallization layer 30 provides a contact for connecting one end of a relatively high voltage source Z~
~D-8654 via terminal 34. Metallization layers 26 and 30, if desired, have conventional emitter shorts 32 formed in their top portions and extending into region 14.
A further metallization layer 24, herein termed the gate of device lO, overlays cathode-base layer 14.
Gate 24 may be connected to an electrical gate signal source via terminal 22. In one form of a photo-sensitive amplifying gate thyristor 10 a light signal may impinge upon part or all of gate region 47. For this purpose, electrode 24 ls selected to be transparent to the incident light radiation, or maintained with small area to allow '~' 3~ sufficient light to impinge on surface-~ in gate region 47 in order to trigger the device.
A still further metallization layer 20 is positioned under layer 18 and provides a means for connecting the other end of the high voltage source to the device 10 via terminal 36. Metallization layer 20 is herein termed the anode of device 10.
Semiconductor device 10, as shown in Figure 1, includes a gate region 47 extending from a centerline 12 to a leading edge, or turn on line, 70 of pilot thyristor 13, a pilot thyristor region 49 extending from the termination of gate region 47 to the termination of emitter 15 of pilot thyristor 13, and a main thyristor region 51 beginning at a turn-on line 80 and spanning the emitter 17 of the main thyristor 28. The leading edge of the pilot thyristor on the side closest to gate region 47, and thereby being leading relative to the gate region.
As previously discussed, occurrences of voltage li63~
transients impressed across the cathode and anode of a semiconductor device, such as device 10, may cause capacitive charging currents to flow within device 10. The capacitive charging currents are shown in Figure 1 as a plurality of arrows 41 emerging from anode 20 and flowing upward through layers 18, 16, ' and 14 towards the top portion 19 of device 10. A
portion of the transient capacitive charging currents may be manifested as a gate current of sufficient value to exceed a critical value and render the main thyristor 28 conductive, thus inadvertently turning on device 10. Similarly, a portion of the transient generated capacitive charging currents 41 may also intercept and render conductive the pilot thyristor 13, thus also inadvertently turning on device 10.
In the embodiment of Figure l, an impedance means 11 is provided to reduce the susceptibility of device 10 to inadvertent turn on by voltage transients. Reducing.
the susceptibility of inadvertent turn on correspondingly increases the dv/dt capability of device 10.
Impedance means 11 is connected between gate 24 and second cathode electrode 30 to provide a shunt path for a portion of the transient capacitive charging currents. Thus impedance means 11 provides a shunt or parallel path to conduct a portion of the transient generated capacitive charging currents away from emitters 15 and 17, and thereby provides the shunt path for most of the transient capacitive charging currents flowing within gate region 47.
3~D2~
Impedance means 11 is comprised of a capacitor having a substantially non-dissipating energy characteristic and a relatively low impedance to fast transients.
Use of a capacitive shunt increases the dv/dt capability of the semiconductor device but increases the turn-on delay time of device 10, and, in general, somewhat reduces the di/dt rating of device 10. For reasons explained infra, the value of capacitor for impedance means 11 is selected with consideration given to the increased dv/dt capability obtained and also to the resulting increased turn-on delay and correspondingly decreased di/dt rating of device 10.
It will be appreciated that use of capacitive shunt 11 having a low impedance to rapid transient currents diverts a portion of the capacitive charging ; currents 41 away from the emitters 15 and 17 and thereby decreases the dv/dt derived gate current that is applied to the pilot thyristor 13 and main thyristor 28. The gate current as a function of time, herein termed IG(t), is approximately represented by the following relationship:
IG(t) - CJ dv/dt (1-e G ) (l) where CJ = the junction capacitance of the gate region 47;
t - elapsed time during the voltage transient;
CJ dv/dt = the capacitive charging currents generated by the voltage transients;
~G~ = (CJ ~ C11). RGK for the time duration t, wherein C11 = capacitive value of impedance means 11; and R = resistance value between gate electrode
2~Kand second cathode electrode 30.
The symbol ~G is herein termed the gate 24-to-c.thode 30 time constant. It should be recognized that the value of TG for device 10 having an inherent capacitive CJ and resistance RGK may be chosen by appro~
priate selection of a capacitive value for C11.
After a time duration tramp when the voltage transient generating the capacitive charging current ceases, IG may be approximately represented by the following relationship for times greater than tramp:
IG(t) = IG(tramp) exp (~(t~tramP)/ a (2) where ta is the time constantmeasurin~ the decay of IG~
Equation (1) may be integrated over the tramp time duration to determine the charge delivered to the gate during tramp and then the result of equation (1) may be added to the integral of equation (2) for time durations greater than tramp to determine the total charge delivered to gate 24, having impedance means 11 attached, by the dv/dt gate current. The determined charge may then be compared to a charge that would have been developed without the capacitance of impedance means 11 connected between gate 24 and second cathode electrode 30. The resulting comparison would be representative of an improved dv/dt factor F, which may be approximately represented by the follow-ing relationship:
F =
l - e~(tramp/ G) (3) As previously mentioned, while impedanee 11 improves the dv/dt capability of device 10 it also increases C~
TABLE I
Anode Voltages Delay di/dt di/dt and ll Approxima-te l'ime (A/~sec.) (A/~sec.) Gate Currents (~d) F Values ~sec.) _yristor (2a) Thyristor (13) 01.00 6.8 200 llO
.021.29 8.4 200 110 VA = 400V.041.77 10.0 200 100 IG = 200ma.062.35 11.6 200 100 .082.93 13.2 200 100 .103.53 14.8 200 100 .206.50 20.3 ~00 100 .309.50 ~6.5 200 100 .4012.50 32.2 200 lO0 .5015.50 38.0 200 100 _ 01.00 3.6 230 VA = 400V.052.06 6.2 225 IG = 400ma.103.53 8.0 225 .155.02 9.8 220 .206.50 11.3 220 110 .309~50 14.2 215 100 _ 40l2.50 l6.9 210 100 01.00 5.1 1100 550 VA = 800V.011.05 6.0 1150 500 IG = 200ma.021.29 6.8 1100 480 .041.77 8.3 1050 440 .052.06 9.0 1000 440 .06, 35 9.8 1000 440 .082.93 11.3 1000 420 .103.53 12.5 950 410 .20 6.5 18.3 900 400 .30 9.5 24.0 880 360 .4012.5 29~5 850 360 .6018.5 40.5 850 360 , ., ,~ --1 1 --~, .
~`iL63~2~
the turn-on time of device 10 to the degree that impedance means 11 takes away gate current from gate 24. In most thyristor applications for relatively low speed switching, such as <lkHz, a TG in the order of 20~
seconds will not substantially dégrade the performance of device 10r If the switching speed needed for the thyristor's use is ~1kHz, then~G should normally be chosen to be no more than a few microseconds.
It should be recognized that impedance means 11 reduces the rise-time of the normal gate current signal applied to gate 24 under normal Piring conditions.
Hence, the turn-on speed and the di/dt rating of device 10 may be affected under normal firing conditions.
To investigate the degree of reduction in turn-on di/dt of an amplifying gate thyristor corresponding to improved dv/dt factors F, experiments were per~orrned, the results of which are shown in Table I. These results present measured turn-on speeds in units of di/dt.
The values given in Table I were derived using equation (3) for a tramp = 1llsec., and ~= RGKC11 where RGK ~ 30Q and C11 is as shown in Table I for each corresponding value of F. The turn-on di/dt in the column for thyristor (28) are those that occurred during turn~on of main thyristor 28. Similarly, the di/dt reading in the column for thyristor (13) are those that occurred during turn-on of pilot thyristor 13. The first four readings of di/dt for pilot thyristor 13 associated with VA = 400V and IG = 400ma were not determined.
From review of Table I, in particular for VA-800V
and IG=200ma., it, is evident that the largest percent reduction in the turn-on di/dt occurs for thyristor 13 changing from 550 to 360. However, the cor~responding F value shows an increase from 1.00 to 18.5. Thus, for a relatively low decrease in the turn-on di/dt a corresponding relatively high improvement to the dv/dt capability of the device is realized as a consequence of utilizing capacitor ll, without any substantial degradation in the other capabilities of device 10.
A second embodiment of the present invention that uses built--in insulative layers to perform a function similar to that of externally connected lmpedance means 11 is shown in Figure 2, which illustrates a partial cross-section of a center-gated amplifying gate thyristor 40 having a pilot thyristor 21 and a main thyristor 33. The layers 14, 16 and 18, transient capacitive charging currents 41, be~e~-Y~, anode 20, and gate .~b ' 24 have a similar structure and function as described for device lO of Figure 1.
Pilot thyristor 21 includes an emitter 37 formed of a high conductivity n+ layer upon which is overlaid a metallization layer 44, herein termed the pilot stage cathode electrode or first cathode electrode. Similarly, main thyristor 33 fncludes an emitter 39 formed of a high conductivity n+ layer upon which is overlaid a metalli2ation layer 45, herein termed the main stage cathode electrode or second cathode electrode.
An insulating layer 46, preferably comprising an oxide of semiconductor layers 14 and 37, is formed ~:IL63~
within layer 14 and emitter 37, and is located to contact and overlap turn-on line 70 of pilot thyristor 21 under the leading edge 48 of first cathode electrode 44.
The mating of leading edge 48 with insulating layer 46 forms a layered arrangement 50. An insulating material 54 is formed within layer 14 and emitter 39 and located to contact and overlap turn-on line 80 of main thyristor 33 under the leading edge 56 of second cathode electrode 45. The mating of leading edge 56 with insulating layer 54 forms a layered arrangement 57.
With further regard to main thyristor 33, an insulating layer 60, preferably comprising an oxide of semiconductor layers 39 and 14, is formed within layar 14 and emitter 39, and is located in a complementary arrangement with a local region 58 of second cathode electrode 45 under which layer 39 has been etched away or otherwise removed.
An alternative to local region 58 and insulator 60 is an ~nsulating layer 62, preferably comprisin~ an oxide of semiconductor layer 14 which is formed beneath second cathode electrode 45 and located in a local region 68 in which emitter 39 was intentionally not diffused or epitaxially grown. lnsulating layers 46, 54, .60 and 62 have a thickness and area predetermined to control the capacitance of regions 53, 57, 58 and 25 68, respectively, in the same manner that capacitance C11 was chosen or varied in the embodiment shown in Figure 1.
The layered arrangements 50 and 57 provide built-in bypass capacitors for pilot thyristor 21 and main 2~ -RD-~65 thyristor 33 respectively. These capacitors provide means for shunting the capacitive charging currents 4i generated by voltage transients impressed across the anode and second cathode, away from emitters 37 and 39 of pilot thyristor 21 and main thyristor 33 respectively. The shunt path for pilot thyristor 21 is provided by layered arrangement 50 diverting a portion of transient capacitive charging cur.rents 41 to first cathode electrode 44. Similarly, the shunt path for main thyristor 33 is provided by layered arrangement 57 diverting a portion of transient capacitive charging currents 41 to second cathode electrode 45.
~ Device 40, shown in Figure 2, having built-in bypass capacitors 50 and 57 within pilot thyristor 21 and main thyristor 33, respectively, accomplishes the same result as device 10 having impedance means 11, as shown in Figure l. Built-in capacitive values ~or layered arrangements 50 and 57 of device 40 in Figure 2 provide approximately the same dv/dt improvement factor F, listed in Table I for corresponding capacitance values C11, with the same degree of increase in turn-on time and reduction in di/dt rating, as for device 10.
The combination of local region 58 and insulating layer 60 provide a capacitive type "emitter short"
in an etched defined type of emitter, as shown in Figure 2. Similarly, the combination of insulating layer 62 positioned under second cathode electrode 45 in an area 68 in which the highly conductive material of emitter 39 has been removed provides a capacitive type "emitter short" in a diffusion defined type of emitter. These capacitive type emitter shorts positioned in main thyristor 33 reduce susceptibility to inadvertent turn-on of amplifying gate thyristor 40 in a manner similar to that occurring as a result of conventional emitter shorts as previously discussed. However, the capacitive emitter shorts of main thyristor 33 do not inhibit spreading of a plasma created upon initial turn-on of a thyristor, as compared to what occurs as a result of conventional emitter shorts. The capacitive emitter shorts of main thyristor 33 increase plasma spreading speed and thus are likely to increase the di/dt capability oP device 40 while maintaining a high dv/dt capability.
It should be recognized that the density and area of local region 60 or 62 should be adjusted so that the dv/dt current flowing into each ~esults in no more than a one-half band gap of voltage across the built-in inJ ec~
capacitor. This will assure little ~4~e~t-K~ from the adjacent n+ emitter P-base junctions. Note that some of the emitter shorts could be conventional ones. For example, conventional shorts could be alternated with capacitive shorts.
Although arnplifying gate thyristors have been described herein, it should be recognized that the described embodiments bf this invention are also applicable to other semiconductor devices, such as thyristors and high voltage transistors. For a thyristor not having a pilot thyristor stage for amplifying the gate current, the described embodiments need only be utilized for the main thyristor stage. Similarly, z~
for a high voltage transistor having two layers of alternating conductivity-type rnaterial similar to layers 14 and 16, the described embodiments need only be utilized to divert the capacitive charging current away from the emitter layers of the transistor whereby they are not amplified by the gain of the transistor.
It ~will now be appreciated that the described embodiments herein concern high voltage semiconductor devices allowing for relatively large improvement to the dv/dt rating of the devices and relatively low degradation to the other parameters of the devices. Still further, the described embodiment utilizing capacitive emitter shorts in the main thyristor emitter layer improves the di/dt capability of the device while maintaining the relatively high dv/dt capability of the device.
While the invention has been particularly shown and described with reference to several preferred ~mbodiments thereo~, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the true spirit and scope of the invention as defined by the appended claims.
The symbol ~G is herein termed the gate 24-to-c.thode 30 time constant. It should be recognized that the value of TG for device 10 having an inherent capacitive CJ and resistance RGK may be chosen by appro~
priate selection of a capacitive value for C11.
After a time duration tramp when the voltage transient generating the capacitive charging current ceases, IG may be approximately represented by the following relationship for times greater than tramp:
IG(t) = IG(tramp) exp (~(t~tramP)/ a (2) where ta is the time constantmeasurin~ the decay of IG~
Equation (1) may be integrated over the tramp time duration to determine the charge delivered to the gate during tramp and then the result of equation (1) may be added to the integral of equation (2) for time durations greater than tramp to determine the total charge delivered to gate 24, having impedance means 11 attached, by the dv/dt gate current. The determined charge may then be compared to a charge that would have been developed without the capacitance of impedance means 11 connected between gate 24 and second cathode electrode 30. The resulting comparison would be representative of an improved dv/dt factor F, which may be approximately represented by the follow-ing relationship:
F =
l - e~(tramp/ G) (3) As previously mentioned, while impedanee 11 improves the dv/dt capability of device 10 it also increases C~
TABLE I
Anode Voltages Delay di/dt di/dt and ll Approxima-te l'ime (A/~sec.) (A/~sec.) Gate Currents (~d) F Values ~sec.) _yristor (2a) Thyristor (13) 01.00 6.8 200 llO
.021.29 8.4 200 110 VA = 400V.041.77 10.0 200 100 IG = 200ma.062.35 11.6 200 100 .082.93 13.2 200 100 .103.53 14.8 200 100 .206.50 20.3 ~00 100 .309.50 ~6.5 200 100 .4012.50 32.2 200 lO0 .5015.50 38.0 200 100 _ 01.00 3.6 230 VA = 400V.052.06 6.2 225 IG = 400ma.103.53 8.0 225 .155.02 9.8 220 .206.50 11.3 220 110 .309~50 14.2 215 100 _ 40l2.50 l6.9 210 100 01.00 5.1 1100 550 VA = 800V.011.05 6.0 1150 500 IG = 200ma.021.29 6.8 1100 480 .041.77 8.3 1050 440 .052.06 9.0 1000 440 .06, 35 9.8 1000 440 .082.93 11.3 1000 420 .103.53 12.5 950 410 .20 6.5 18.3 900 400 .30 9.5 24.0 880 360 .4012.5 29~5 850 360 .6018.5 40.5 850 360 , ., ,~ --1 1 --~, .
~`iL63~2~
the turn-on time of device 10 to the degree that impedance means 11 takes away gate current from gate 24. In most thyristor applications for relatively low speed switching, such as <lkHz, a TG in the order of 20~
seconds will not substantially dégrade the performance of device 10r If the switching speed needed for the thyristor's use is ~1kHz, then~G should normally be chosen to be no more than a few microseconds.
It should be recognized that impedance means 11 reduces the rise-time of the normal gate current signal applied to gate 24 under normal Piring conditions.
Hence, the turn-on speed and the di/dt rating of device 10 may be affected under normal firing conditions.
To investigate the degree of reduction in turn-on di/dt of an amplifying gate thyristor corresponding to improved dv/dt factors F, experiments were per~orrned, the results of which are shown in Table I. These results present measured turn-on speeds in units of di/dt.
The values given in Table I were derived using equation (3) for a tramp = 1llsec., and ~= RGKC11 where RGK ~ 30Q and C11 is as shown in Table I for each corresponding value of F. The turn-on di/dt in the column for thyristor (28) are those that occurred during turn~on of main thyristor 28. Similarly, the di/dt reading in the column for thyristor (13) are those that occurred during turn-on of pilot thyristor 13. The first four readings of di/dt for pilot thyristor 13 associated with VA = 400V and IG = 400ma were not determined.
From review of Table I, in particular for VA-800V
and IG=200ma., it, is evident that the largest percent reduction in the turn-on di/dt occurs for thyristor 13 changing from 550 to 360. However, the cor~responding F value shows an increase from 1.00 to 18.5. Thus, for a relatively low decrease in the turn-on di/dt a corresponding relatively high improvement to the dv/dt capability of the device is realized as a consequence of utilizing capacitor ll, without any substantial degradation in the other capabilities of device 10.
A second embodiment of the present invention that uses built--in insulative layers to perform a function similar to that of externally connected lmpedance means 11 is shown in Figure 2, which illustrates a partial cross-section of a center-gated amplifying gate thyristor 40 having a pilot thyristor 21 and a main thyristor 33. The layers 14, 16 and 18, transient capacitive charging currents 41, be~e~-Y~, anode 20, and gate .~b ' 24 have a similar structure and function as described for device lO of Figure 1.
Pilot thyristor 21 includes an emitter 37 formed of a high conductivity n+ layer upon which is overlaid a metallization layer 44, herein termed the pilot stage cathode electrode or first cathode electrode. Similarly, main thyristor 33 fncludes an emitter 39 formed of a high conductivity n+ layer upon which is overlaid a metalli2ation layer 45, herein termed the main stage cathode electrode or second cathode electrode.
An insulating layer 46, preferably comprising an oxide of semiconductor layers 14 and 37, is formed ~:IL63~
within layer 14 and emitter 37, and is located to contact and overlap turn-on line 70 of pilot thyristor 21 under the leading edge 48 of first cathode electrode 44.
The mating of leading edge 48 with insulating layer 46 forms a layered arrangement 50. An insulating material 54 is formed within layer 14 and emitter 39 and located to contact and overlap turn-on line 80 of main thyristor 33 under the leading edge 56 of second cathode electrode 45. The mating of leading edge 56 with insulating layer 54 forms a layered arrangement 57.
With further regard to main thyristor 33, an insulating layer 60, preferably comprising an oxide of semiconductor layers 39 and 14, is formed within layar 14 and emitter 39, and is located in a complementary arrangement with a local region 58 of second cathode electrode 45 under which layer 39 has been etched away or otherwise removed.
An alternative to local region 58 and insulator 60 is an ~nsulating layer 62, preferably comprisin~ an oxide of semiconductor layer 14 which is formed beneath second cathode electrode 45 and located in a local region 68 in which emitter 39 was intentionally not diffused or epitaxially grown. lnsulating layers 46, 54, .60 and 62 have a thickness and area predetermined to control the capacitance of regions 53, 57, 58 and 25 68, respectively, in the same manner that capacitance C11 was chosen or varied in the embodiment shown in Figure 1.
The layered arrangements 50 and 57 provide built-in bypass capacitors for pilot thyristor 21 and main 2~ -RD-~65 thyristor 33 respectively. These capacitors provide means for shunting the capacitive charging currents 4i generated by voltage transients impressed across the anode and second cathode, away from emitters 37 and 39 of pilot thyristor 21 and main thyristor 33 respectively. The shunt path for pilot thyristor 21 is provided by layered arrangement 50 diverting a portion of transient capacitive charging cur.rents 41 to first cathode electrode 44. Similarly, the shunt path for main thyristor 33 is provided by layered arrangement 57 diverting a portion of transient capacitive charging currents 41 to second cathode electrode 45.
~ Device 40, shown in Figure 2, having built-in bypass capacitors 50 and 57 within pilot thyristor 21 and main thyristor 33, respectively, accomplishes the same result as device 10 having impedance means 11, as shown in Figure l. Built-in capacitive values ~or layered arrangements 50 and 57 of device 40 in Figure 2 provide approximately the same dv/dt improvement factor F, listed in Table I for corresponding capacitance values C11, with the same degree of increase in turn-on time and reduction in di/dt rating, as for device 10.
The combination of local region 58 and insulating layer 60 provide a capacitive type "emitter short"
in an etched defined type of emitter, as shown in Figure 2. Similarly, the combination of insulating layer 62 positioned under second cathode electrode 45 in an area 68 in which the highly conductive material of emitter 39 has been removed provides a capacitive type "emitter short" in a diffusion defined type of emitter. These capacitive type emitter shorts positioned in main thyristor 33 reduce susceptibility to inadvertent turn-on of amplifying gate thyristor 40 in a manner similar to that occurring as a result of conventional emitter shorts as previously discussed. However, the capacitive emitter shorts of main thyristor 33 do not inhibit spreading of a plasma created upon initial turn-on of a thyristor, as compared to what occurs as a result of conventional emitter shorts. The capacitive emitter shorts of main thyristor 33 increase plasma spreading speed and thus are likely to increase the di/dt capability oP device 40 while maintaining a high dv/dt capability.
It should be recognized that the density and area of local region 60 or 62 should be adjusted so that the dv/dt current flowing into each ~esults in no more than a one-half band gap of voltage across the built-in inJ ec~
capacitor. This will assure little ~4~e~t-K~ from the adjacent n+ emitter P-base junctions. Note that some of the emitter shorts could be conventional ones. For example, conventional shorts could be alternated with capacitive shorts.
Although arnplifying gate thyristors have been described herein, it should be recognized that the described embodiments bf this invention are also applicable to other semiconductor devices, such as thyristors and high voltage transistors. For a thyristor not having a pilot thyristor stage for amplifying the gate current, the described embodiments need only be utilized for the main thyristor stage. Similarly, z~
for a high voltage transistor having two layers of alternating conductivity-type rnaterial similar to layers 14 and 16, the described embodiments need only be utilized to divert the capacitive charging current away from the emitter layers of the transistor whereby they are not amplified by the gain of the transistor.
It ~will now be appreciated that the described embodiments herein concern high voltage semiconductor devices allowing for relatively large improvement to the dv/dt rating of the devices and relatively low degradation to the other parameters of the devices. Still further, the described embodiment utilizing capacitive emitter shorts in the main thyristor emitter layer improves the di/dt capability of the device while maintaining the relatively high dv/dt capability of the device.
While the invention has been particularly shown and described with reference to several preferred ~mbodiments thereo~, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the true spirit and scope of the invention as defined by the appended claims.
Claims (7)
1. A high voltage semiconductor device comprising:
a first cathode including a first metallization layer and a first emitter layer thereunder, a second cathode including a second metallization layer and a second emitter layer thereunder; a gate region adapted to receive an applied signal; and an anode; said first cathode having a turn-on line located approximately at a leading edge of said first emitter layer with respect to said gate region; said second cathode having a turn-on line located approximately at a leading edge of said second emitter layer with respect to said gate region; said first and second cathodes being separated from said anode by a plurality of layers of alternating conductivity-type material and being coupled to said gate region by a first of said layers of alternating conductivity-type material; said second cathode and said anode being adapted to be coupled between opposite ends of a relatively high voltage potential source having periodic relatively high voltage transients so that occurrences of said periodic voltage transients between said second cathode and said anode generate capacitive charging currents within said layers of alternating conductivity-type material which are manifested as gate currents in said first and second emitter layers, said high voltage semiconductor device further comprising:
capacitive means coupled to said gate region to provide a capacitive shunt path for diverting a portion of transient-generated capacitive charging currents within said gate region away from said second emitter layer and the portion of said first layer of alternating conductivity-type material lying thereunder, such that the transient-generated capacitive charging currents which are manifested as gate currents are reduced thereby improving the dv/dt capability of said device;
said capacitive means comprising: a first insulating layer disposed within said first emitter layer and a portion of said first layer adjacent said leading edge of said first emitter layer and overlapping said turn-on line of said first cathode, said first metallization layer overlying said first insulating layer and also overlying said leading edge of said first emitter layer and overlapping said turn-on line of said first cathode; and a second insulating layer disposed within said second emitter layer and a portion of said first layer adjacent said leading edge of said second emitter layer and overlapping said turn-on line of said second cathode, said second metallization layer overlying said second insulating layer and also overlying said leading edge of said second emitter layer and overlapping said turn-on line of said second cathode.
a first cathode including a first metallization layer and a first emitter layer thereunder, a second cathode including a second metallization layer and a second emitter layer thereunder; a gate region adapted to receive an applied signal; and an anode; said first cathode having a turn-on line located approximately at a leading edge of said first emitter layer with respect to said gate region; said second cathode having a turn-on line located approximately at a leading edge of said second emitter layer with respect to said gate region; said first and second cathodes being separated from said anode by a plurality of layers of alternating conductivity-type material and being coupled to said gate region by a first of said layers of alternating conductivity-type material; said second cathode and said anode being adapted to be coupled between opposite ends of a relatively high voltage potential source having periodic relatively high voltage transients so that occurrences of said periodic voltage transients between said second cathode and said anode generate capacitive charging currents within said layers of alternating conductivity-type material which are manifested as gate currents in said first and second emitter layers, said high voltage semiconductor device further comprising:
capacitive means coupled to said gate region to provide a capacitive shunt path for diverting a portion of transient-generated capacitive charging currents within said gate region away from said second emitter layer and the portion of said first layer of alternating conductivity-type material lying thereunder, such that the transient-generated capacitive charging currents which are manifested as gate currents are reduced thereby improving the dv/dt capability of said device;
said capacitive means comprising: a first insulating layer disposed within said first emitter layer and a portion of said first layer adjacent said leading edge of said first emitter layer and overlapping said turn-on line of said first cathode, said first metallization layer overlying said first insulating layer and also overlying said leading edge of said first emitter layer and overlapping said turn-on line of said first cathode; and a second insulating layer disposed within said second emitter layer and a portion of said first layer adjacent said leading edge of said second emitter layer and overlapping said turn-on line of said second cathode, said second metallization layer overlying said second insulating layer and also overlying said leading edge of said second emitter layer and overlapping said turn-on line of said second cathode.
2. The high voltage semiconductor device of claim 1, wherein said plurality of layers of alternating con-ductivity-type material further includes a second layer and a third layer, so that said periodic voltage transients between said second cathode and said anode generate capacitive charging currents within said first and second and third layers which are manifested as gate currents in said first and second emitter layers.
3. The high voltage semiconductor device of claim 2, wherein said second cathode is located adjacent said gate region.
4. The high voltage semiconductor device of claim 1, 2 or 3, wherein a portion of said gate region is arranged to receive incident light radiation impinging on said gate region.
5. The high voltage semiconductor device of claim 1 or 2, wherein said second cathode comprises at least one insulating layer and at least one metallization layer;
said second emitter layer of said second cathode being interrupted at a location; one side of said insulating layer abutting the underside of said metallization layer at said location where said second emitter layer is interrupted;
and another side of said insulating layer abutting only said first layer and said second emitter layer of said second cathode; so as to enhance the speed at which a plasma spreads when said plasma is created upon initial turn-on of said device and thereby improve di/dt capability of said device.
said second emitter layer of said second cathode being interrupted at a location; one side of said insulating layer abutting the underside of said metallization layer at said location where said second emitter layer is interrupted;
and another side of said insulating layer abutting only said first layer and said second emitter layer of said second cathode; so as to enhance the speed at which a plasma spreads when said plasma is created upon initial turn-on of said device and thereby improve di/dt capability of said device.
6. The high voltage semiconductor device of claim 1 or 2, wherein said second emitter layer of said second cathode is interrupted at a location; said second cathode comprising at least one insulating layer extending into a cavity portion of said first layer of alternating conductivity-type material and at least one metallization layer overlying and abutting said insulating layer at said location where said second emitter layer is interrupted;
and one side of said insulating layer within said cavity portion abutting only said first layer; so as to enhance the speed at which a plasma spreads when said plasma is created upon initial turn-on of said device and thereby improve di/dt capability of said device.
7. The high voltage semiconductive device of claim 1, 2 or 3, wherein said first insulating layer comprises an oxide of the semiconductor material of said first emitter layer and of the semiconductor material of said first layer; and said second insulating layer comprises an oxide of the
and one side of said insulating layer within said cavity portion abutting only said first layer; so as to enhance the speed at which a plasma spreads when said plasma is created upon initial turn-on of said device and thereby improve di/dt capability of said device.
7. The high voltage semiconductive device of claim 1, 2 or 3, wherein said first insulating layer comprises an oxide of the semiconductor material of said first emitter layer and of the semiconductor material of said first layer; and said second insulating layer comprises an oxide of the
Claim 7 continued:
semiconductor material of said second emitter layer and of the semiconductor material of said first layer.
semiconductor material of said second emitter layer and of the semiconductor material of said first layer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15274280A | 1980-05-23 | 1980-05-23 | |
| US152,742 | 1980-05-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1163020A true CA1163020A (en) | 1984-02-28 |
Family
ID=22544224
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000377573A Expired CA1163020A (en) | 1980-05-23 | 1981-05-14 | High voltage semiconductor device having improvements to the dv/dt capability and plasma spreading |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS5710972A (en) |
| CA (1) | CA1163020A (en) |
| CH (1) | CH656485A5 (en) |
| DE (1) | DE3120254A1 (en) |
| SE (1) | SE457837B (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5810656B2 (en) * | 1977-01-25 | 1983-02-26 | 矢崎総業株式会社 | Solar heating/cooling/water heating equipment |
| JPS58134470A (en) * | 1982-02-05 | 1983-08-10 | Meidensha Electric Mfg Co Ltd | Gate turn-off thyristor of amplifying gate structure |
| JPH0680821B2 (en) * | 1989-05-01 | 1994-10-12 | 株式会社東芝 | High sensitivity triac |
| US5592118A (en) * | 1994-03-09 | 1997-01-07 | Cooper Industries, Inc. | Ignition exciter circuit with thyristors having high di/dt and high voltage blockage |
| US5970324A (en) * | 1994-03-09 | 1999-10-19 | Driscoll; John Cuervo | Methods of making dual gated power electronic switching devices |
| US5981982A (en) * | 1994-03-09 | 1999-11-09 | Driscoll; John Cuervo | Dual gated power electronic switching devices |
| US5656966A (en) * | 1994-03-09 | 1997-08-12 | Cooper Industries, Inc. | Turbine engine ignition exciter circuit including low voltage lockout control |
| US7355300B2 (en) | 2004-06-15 | 2008-04-08 | Woodward Governor Company | Solid state turbine engine ignition exciter having elevated temperature operational capability |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5917863B2 (en) * | 1976-11-04 | 1984-04-24 | 三菱電機株式会社 | thyristor |
| JPS5942991B2 (en) * | 1977-05-23 | 1984-10-18 | 株式会社日立製作所 | thyristor |
| DE2855265A1 (en) * | 1978-12-21 | 1980-07-10 | Bbc Brown Boveri & Cie | THYRISTOR |
-
1981
- 1981-05-14 CA CA000377573A patent/CA1163020A/en not_active Expired
- 1981-05-21 DE DE19813120254 patent/DE3120254A1/en active Granted
- 1981-05-21 SE SE8103222A patent/SE457837B/en not_active IP Right Cessation
- 1981-05-22 CH CH337481A patent/CH656485A5/en not_active IP Right Cessation
- 1981-05-22 JP JP7680781A patent/JPS5710972A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| SE457837B (en) | 1989-01-30 |
| SE8103222L (en) | 1981-11-24 |
| CH656485A5 (en) | 1986-06-30 |
| DE3120254C2 (en) | 1993-09-23 |
| DE3120254A1 (en) | 1982-05-27 |
| JPS5710972A (en) | 1982-01-20 |
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