1 1 622~0 SoIid state mage pickup device The present invention relates to a solid state image pickup device for use in a television camera.
Such a device involves a predetermined number of photoelectric converting elements, each of which consists o a photodiode and a MOS transistor using the photodiode as its source portion, arranged to correspond to respective picture cells. The photoelectric converting elements are arranged in a row vertically of an image pickup frame and :`10 are generalized by a signal line, each row being connected with an output terminal through a switching MOS transistor.
Additionally provided are horizontal and vertical scanning circuits constructed of MOS shi~t registers. The horizontal :~ scanning circuit controls the gates of the MOS transistors ~: : 15 through a signal line whereby to perform the horizontal scanning operation. The vertical scanning circuit general-izes and directly controls the gates of the MOS transistors of the respective photoelectric converting elements, which are arranged in a line horizontally of the image pickup frame, whereby to perform the vextical scanning operation :for each line.
! ~he following description is directed to an n-channel type.device using electrons as its signal charge, but an entirely similar description can be applied to a p-channel type device using positive holes as its signal charge by inverting the conduction types and polarities.
The electrons generated by light are stored in the ~' -- i 1 6228~
junction capacitors of the photodiodes. During the reading operation, the MOS transistors are rendered conductive through the signal lines by the positive scanning pulses generated by the vertical scanning circuit, and the MOS
transistors are consecutively rendered conductive through the signal lines by the positive scanning pulses generated by the horizontal scanning circuit. Thus for the time period after one scanning operation and before the next scanning operation, the charges, which have been generated by the photodiodes from -the light incident upon the picture cells and stored in the junction capacitors of the photo-diodes, are consecutively read out as signal charges.
In the image pickup device to be described, a parasitic capacitance exists between the gate and drain of each switching MOS transistor. Through that capacitance, the scanning pulses from the scanning circuits appear in the form of a noise spike. The intensity of this noise spike disperses due to unevennesses in the threshold voltages of the transistors and in the capacitances. This results in establishment of noise that has a pattern which is fixed horizontally of the image to be picked up. In a solid state image pickup device or image pickup tube, since the capaci-tance appearing at the output terminal generally has a value as high as about 10 pF, the high-frequency component of the image information leaks through that capacitance to the substrate. In order to compensate for this leak, it is necessary to raise the high-frequency gain of a preamplifier that is connected to the output terminal of the device. On the other hand, since an element to be used as the input terminal of the preamplifier, e.g., a junction field effect transistor, generates white noise having an intensity distribution with no relationship to the frequency, the high-frequency noise is highly amplified if the high-frequency gain of the preamplifier is so raised, with the result that the S/N ratio of the device deteriorates.
An image pickup device has an additional but major problem. This is the phenomenon of blooming, in which a 1 ~ ~2280 vertical white band appears from the hrighter portion of the image pickup frame when a strongly lit image is picked up .
The presert invention has the object of providing improvements in respect of these disadvantages and consists of a device in which each photoelectric converting element unit is no~ connected directly to a switching MOS transistor but indirectly to the switching MOS transistor through an amplifying MOS transistor.
More specifically, the invention consists of a solid state image pickup device comprising a group of photoelectric converting solid state elements comprising a two-dimensional array on a semiconductor substrate of a plurality of solid state elements corresponding to respective picture cells and each including a photoelectric converting element, and first, second and third field effect transistors such that said photoelectric converting element has its first electrode connected to the gate electrode of said second field effect transistor, the source electrode of said second field effect transistor is connected to the drain electrode of said first field effect transistor, the drain electrode of said second field effect transistor is either grounded or connected to a power supply, said third field effect transistor has its drain electrode connected to the gate electrode of said second field effect transistor, and the source electrode of said third field effect transistor is either grounded or connected to a power supply; said array being such that a predetermined number of the gate electrodes of said first field effect transistors are commonly connected to provide a first selection line, the source electrodes of said first field effect transistors are commonly connected to provide a second selection line, and the gate electrodes of said third field effect transistors are connected with a reset pulse generator.
Embodiments of the invention are illustrated by way of example in the accompanying drawings, in which:
Fig. 1 is a diagram showing a circuit equi~alent to 1 1 ~2280 a solid state image pickup device according to the prior art;
Fig. 2 is a sectional view showing a light receiving portion of the ~ame;
Fig. 3 is a diagram showing an equivalent circuit of an example of a solid state image pickup device according to an embodiment of the present invention;
Fig. 4 is a chart illustrating the operating timings of the same device;
Figs. 5a and 5b are equivalent circuit diagrams of a signal reading portion, but show those of the devices according to the prior art and the present invention, respectively;
Fig. 6 is a chart illustrating the changes in a potential V30' and an output current I'7';
Figs. 7 and 8 are sectional views respectively showing a solid state image pickup device according to an embodiment of the present invention;
Figs. 9 and 10 are equivalent circuit diagrams respectively showing the signal reading portion;
Fig. 11 is a diagram showing an equivalent circuit to an amplifying transistor when it is reset;
Fig. 12 is a graphical presentation showing the relation-ship between the drain voltage - current of the amplifying transistor;
Figs. 13~ 14 and 15 are equivalent circuit diagrams respectively showing the major portions of a solid state image pickup device according to an embodiment of the present invention;
Fig. 16 is a chart illustrating the operation timings of the device, the equivalent circuit of which is shown in Fig. 15;
Figs. 17 and 21 are diagrams respectively showing the equivalent circuits of solid state image pickup devices according to embodiments of the present invention;
Figs. 18 to 20 are charts illustrating the operation of these devices; and Fig. 22 is a graphical presentation illustrating the ~ ~ 62~80 characteristics of an output signal current.
Fig. 1 is a circuit diagram explaining a typical solid state image pickup device. A predetermined number o~ photo-electric conver-ting elements, each of which consists of a photodiode 1 and a MOS transistor 2, using the photodiode 1 as its source, are arranged to correspond to respective picture cells. These converting elements are arranged in rows 4 disposed vertically of an image pickup frame, being generalized vertically by a signal line 5 connected to an output terminal 7 through a switching MOS transistor 3 and a signal line 6. Horizontal and vertical scanning circuits 9 and 10 comprise MOS shift registers. The circuit 9 controls the gates of the MOS transistors 3 through a line 8 to perform the horizontal scanning operation. The circuit 10 directly controls the gates of the MOS transistor 2 to perform the vertical scanning operation.
Electrons generated by lig~ht are stored in the junction capacitors of the photodiodes 1. During the reading opera-tion, the MOS transistors 2 are rendered conductive throughthe lines ~ by positive scanning pulses from the vertical scanning circuit 1~, and the MOS transistors 3 are consecu-tively rendered conductive through the lines 8 by positive scanning pulses from the horizontal scanning circuit 9. Thus, after each scanning operation and before the next, the charges which have been generated by the photodiodes 1 from the light incident upon the picture cells are stored in the junction capacitors of the photodiodes 1 and are consecutively read out as signals.
As described above, such a prior art device has failed to be free from such defects as (1) production of a noise pattern in the image picked up, (2) reduction in the S/N
ratio caused by the preamplifier, and (3) blooming.
The causes for blooming will now be explained with reference to Fig. 2 showing the light receiving portion of the device in section. Numeral 21 indicates a semiconductor substrate and numeral 1 an impurity region form~ng the photodiode and acting as the source of the MOS transistor.
~ ~ ~2~8~, Numerals 17 and 16 indicate a drain and a channel portion, respectively. If strong light irradiates the photodiode 1, numerous pairs of electrons and holes are generated to drop the potential at the cathode of the photodiode 1 and render conductive the transverse parasitic transistor 18 that consists of the source 15, channel 16 and drain 17 of the MOS transistor 2, so that electrons are transmitted to a vertical signal line 14 in spite of the fact that another picture cell is being read out and said MOS transistor is thus non-conductive. As a result, even though the other picture cell connected to the vertical signal line 14 is not irradiated with light, a false signal caused by the electron leak appears vertically of the image pickup frame.
The noise problem and blooming phenomenon thus far described raise severe disadvantages to the practical use of this type of device.
Fig. 3 is a circuit diagram showiny one embodiment of the presenk invention. The ca~thode of each photodiode 1 is connected with the gate of an amplifylng MOS transistor 20 which has its drain and source connected with a power supply 23 and the source of the transistor 2, respectively.
In order to return ~or reset) the potential at the cathode of the photodiode after a signal reading operation, on the other hand, there is provided a resetting transistor 2~
which has its drain, source and gate respectively connected to the gate of the transistor 20, grounded to earth or connected to a constant voltage power supply 25, and connec~
ted to a reset control line 26. The scanning circuits 9 and 10 are equivalent to those shown in Fig. 1, the output of the vertical scanning circuit 10 being connected to the scanning line 4 and the reset control line 26 of each picture cell through a vertical scan control circuit 27. ~umeral 28 in Fig. 3 indicates a capacitor of the vertical signal line.
Fig. 4 illustrates the operating timing chart of this device. Here, the numerals affixed to the respective voltages and current designate the voltages (V~ or the
2~0 current (I) at the nodes indicated by the corresponding numerals in Fig. 3. From a time t0 to tl, the voltage V26 takes a high level H so that the clearing transistor 24 is rendered conductive to reset the cathode potential V29 of the photodiode 1 to a voltage E25 of the power suppl~ 25.
When~the voltage V26 is dropped to a low level L at time tl, the charges that have been stored in the photodiode are released due to the photocurrent that flows through the photodiode, so that the potential V29 is gradually reduced.
After a storage time of one field or about 16 ms, the voltage of the scanning line is raised to the high level H, and the source of the amplifying MOS transistor is connected to the vertical signal line so that the voltage thereat varies, as shown, in accordance with the gate voltage V29 of the amplifying transistor. If the transistor 2Q is operated within its saturation region by making the drain voltage E23 thereof higher than the value (V29 - Vth), which is determined by subtracting the threshold voltage Vth of said transistor from the voltage V29 to be impressed upon the gate of said transistor, the following appears as the voltage V30:
V30 = V29 - Vth - - - - - - - - - - - - (1).
This voltage is obtained as a result of the fact that the parasitic capacitor C28 (which is indicated at numeral 28 in Fig. 3) of the vertical signal line is charged by the amplifying transistor 20. Thus, the parasitic capacitor C28 is charged with the following charges Qs:
Qs = Q28 V30 = C28(V29 - Vth) - - - - - (2).
Operations during the time period (t2 - t3) are performed during the horizontal erasing period, After that, at a time t4, the voltage V26 is raised to the level H, and the photodiode is reset. At a time t5, the scanning pulses from the horizontal scanning circuit take the high leve~ H, as i.ndicated at V8, so that a signal current I7 is read out through a.load resistor 31. Here, the current Is to be obtained as the output is expressed by the following Equation:
Is = Qs / Tr - - - - - - - - - - - - - (3) wherein Tr designates the period of the horizontal scanning pulses.
The following description is directed to the fact that the device of the present invention is superior to that of the prior art in S/N ratio and in its blooming restraining capability. Figs. 5a and 5b respectively show an equivalent circuit of the signal reading unit of the device of the prior art and of a device using the amplifier according to the present embodiment. Reference numerals 1' and 1" indicate an equivalent capacitor Cl' of the photodiode and a photo-current supply Iph which varies with the intensity of the incident light. In either case, the cathode voltages V29 and V29' of the photodiode 1 after the signal reading opera-tion become the voltage E25 of the bias voltage supply 25, which is stored in the capacito`r 1'. In the construction shown in Fig. 5a, the terminal 29 is set at E25 simultane-ously with the reading operation, rendering transistors 2 and 3 conductive. The resetting transistor 24 is rendered conductive after the reading operation in the construction shown in Fig. 5b whereby to set the terminal 29' at E25.
After that, the charges in the capacitor 1' are released through the photocurrent supply 1" for one field time period Ts (which is usually about 17 ms). Both the voltages at the terminals 29 and 29' after one field time period are expressed by the followin~ Equation:
V29 = V29l = E25 - Iph-Ts/Cl 7 - - - - - (4) In the case of Fig. 5a, the switching transistor 2 is first rendered conductive to distribute the voltage V29 to the vertical signal line capacitor C28. The potential at the terminal 30 at that time is expressed by the following Equation:
Cl' + C28 (V29 - E25) ~ E25 - - -o The signal charge to be transferred to the capacitor C2~ is expressed by the following Equation:
C30 = C28(V30 - E25) C28 Cl' _ph Ts C28 -~ C1' Cl' Here, since the capacitances C28 and Cl' are about 5 pF and about 0.1 pF, respectively, the Equation (6) can be approximated, as follows:
Q30 ~ - Iph-Ts - - - - - - - - - - - - (7).
In short, the charges stored by the photocurrent supply Iph are transferred as they are to the capacitor 28. These charges are detected as the current flowing through the load resistor 31 or the preamplifier as a result of the fact tha-t the hori-zontal switching transistor is rendered conductive. The signal current I7 has a spike shape similar to that shown in Fig. 4 and is fed through a low-pass filter so that an average current value I7, in which the signal charge Q30 flows on an average for the reading time period, is obtained to provide a video signal. The level of that current is expressed by the following Equation:
I7 = Q30/Tr = -Iph-Ts/Tr - - - - - - (8).
In the device having the built-in amplifier, on the contrary, the voltage to be stored in the capacitor 28 is determined in accordance with the voltage V29', as in the following Equation:
2~ V30' = V29' - Vth = tE25 - Iph-Ts/Cl') - Vth - - - - (9).
Hence, the charges to be stored in the capacitor 28 are expressed by the following Equation:
Q30' - C28 V30' = C28-(E25 - Iph Ts/Cl' - Vth).
The signal current after having passed t:hrough the low-pass filter is expressed by the following Equation:
I7 = C28-(E25 - Vth) - C28 Iph Ts/Cl'/Tr - - - - ~ (10), wherein the first term is a portion having no relationship with the optical signal. Hence, the effective signal current I7s is expressed by the following Equation:
I7s = - Iph ~s/Tr-C28/Cl' - - - ~ - - - (11).
The signal is increased C28/Cl' times that of Equation (8 using no amplifier. Since C28 > Cl' usually holds, e.g., C2~ and Cl', are about 5 pF and about O.lpF, respectively, this amplifier acquires a gain of about 50. As a result, since the signal is 50 times as high as the noise which is produced after amplification by the switching transistor
3 or the preamplifier, the S/N ratio is improved by a value of 50 times, i.e., about 34 ds, so that a device is realized having a performance that exceeds not only that of a conven-tional solid state image pickup device but also the S/N ratioof an image pickup tube.
Next, as to the~second point of blooming, even if strong light causes the cathode potential of the photodiode 1 to be dropped, the aforementioned transverse parasitic trans-istor is neither rendered conductive nor does the bloomingphenomenon appear, because the photodiode 1 is isolated from the source of the switching transistor 2 by the gate oxide film of the amplifying transistor 20.
The drain of the amplifying transistor 20 is connected to the power supply 23 but may be grounded to earth, as indicated at 34 by a broken line in Fig. 3. In this modi-fication, a power supply voltage 33 is supplied to the 1 3 ~ 0 output terminal 7 thxough a load resi.stor 32. This power supply voltage is stored in the capacitor 28 of the vertical signal line simultaneously with the reading operation and is released by the amplifying transistor when the switching transistor 2 is rendered conductive. The potential V30' at a node 30' and the output current I7' at that time are illustrated in Fig. 6.
Fig. 7 is a sectional view showing an example of the picture cell portion of a solid state image pickup device according to an embodiment of the present invention.
- Reference numerals l, 20 and ~ indicate the areas of the photodiode, the amplifying transistor and the switching transistor, respectively; and reference numerals 35, 36, 37 and 38 indicate the impurity regions providing the sources and drains of the photodiode and the respective transistors, respectively. All of those areas and regions have the conduction type opposite that of the substrate 21. ~umerals 101 and 102 indicate gate elect~odes. Although omitted from Fig. 7, the drain of the resetting transistor 24 is connected `D 20 to the portion 35, and the power supply voltage 23 is connected ;to the portion 36. On the other hand, numeral 39 indicates wiring connecting the amplifying transistor 20 and the photo-diode 1. In the device so constructed, the area to be used for photoelectric conversion in one picture cell is the portion indicated at 40 in Fig. 7.
Fig. 8 is a sectional view showing the picture cell according to another embodiment of the present invention~
The construction of this embodiment is useful for increasing the effective area to be used for photoelectric conversion of a solid state image pickup device having a built-in amplifier. An example of a device of this kind is disclosed in Japanese Patent Publication No. 51-10715.
Needless to say, the present invention can also be applied to a solid state image pickup device using a photoconductive film. In this example, there is overlaid on the wiring 39 a metal electrode 42, which is insulated by means of an insulator 41, such as SiO2, from the underlying circuit except for a connecting portion to the wiring 39, the ~ :~ 62~80 constructlon of the substrate portion being similar to that of the aforementioned example. The metal electrode 42 generally covers one picture cell and is formed of metal such as AQ, Mo or Ta by a meta] evaporation or sputtering process. There is further overlaid on a metal electrode 42 a single- or poly-crystalline or amorphous thin film having photoconduc-tivity. The single-crystalline material may be Si t Ge or HgCdTe; the polycrystalline material may be PbTe, CdSe, ZnCdTe or In2Te3; and the amorphous material may be amorphous ~i, As2Se3 or a ~e-As-Te chalcogenide thin film. Although the metal electrode is isolated for each picture cell, it is necessary that even the photoelectric converting film having a resistivity less than 101 Qcm be subjected to that isolation for each picture cell. Even if the other thin films are not subjected to isolation for each picture cell, as indicated by a photoelectric converting film 43 in Fig. 8, no problem arises in transverse flow of the signal. Overlaid on the photoelectric converting film 43 is a transparent electrode 44 made of indium oxide containing SnO2 or Sn. As a result, the effective area to be used for photoelectric conversion substantially occupies all of one picture cell, as indicated at 45, so that a higher sensitivity than that of Fig. 7 can be attained. Moreover, since the amplifier portion is shielded by the metal electrode 42 and the photoelectric converting film 43, no charge due to photoelec-tric conversion is generated at the portions 35 to 38 so that stable operation can be realized.
The equivalent circuit for the signal reading operation is shown in Fig~ 9. Of the reference numerals, those the same as Fig. 5 indicate the same elements. In Fig. 9, reference numerals 43' and 43" indicate the equivalent capacitor C43' of the photoelectric converting film and the photocurrent supply Iph, respectively. Numeral 46 indicates a bias power supply impressed upon the photoelectric converting film 43 through the transparent electrode 44 and which may be grounded, as indicated at 47. In the present device, the potential at the terminal 29 after storage of ~ ~ B7,~,8~
one frame is expressed by the following Equation:
V29 E25 ~ Iph-Ts _ _ _ _ _ (12), This potential is expressed by the following E~uation when the transparent electrode is grounded as indicated at 47:
V29 E25 Cl' + C43' (13).
The signal reading operations of the device so far described are not different from those of Fig. 4.
In a device of this kind, an improved image can be obtained by constructing the signal reading circuit as shown in Fig. 10. ~ere, the resetting transistor 24 is so connected that it can short-circuit the gate and source of the amplifying transistor 20. In Fig. 10, the same reference numerals as those in Fig. 9 indicate the same elements. On the other hand, the voltage impressed upon 15 the drain of the transistor 20 is so switched that it is supplied to the voltage E23 during the amplifying operation and is grounded during the resetting operation. The circuit under consideration is characterized in that the potential at the node 29 after the resetting operation becomes the 20 threshold voltage Vth of the amplifying transistor 20.
This will be described with reference to Fig. 11 showing the equivalent circuit when in the resetting operation. A
capacitor 49 is composed of the capacitors 43' and 1' of Fig. 10 in parallel. The capacitor 49 is discharged by the 25 amplifying transistor 20 which has its source and gate short~
circuited. The relationship between the drain current Id of the MOS transistor thus connected and a voltage Vd is made t as shown in Fig. 12, such that the drain current Id flows only when the drain voltage Vd exceeds the threshold voltage 30 Vth. The drain current exhibits the square characteristics expressed by the following E~uation:
Id = ~(Vd - Vth)2 ~ - - - (14), wherein ~ is a coefficient ~etermined by the mobility of carriers, the capacitance of the gate oxide film and so on.
1 :~ 622~
secause of these I-V characteristics, no current flows to stop the discharge when the voltage at 2g of the circuit of Fig. 11 reaches the threshold voltage Vth. In other wordsl the voltage at the node 29 is xeset at the threshold voltage Vth of the amplifying MOS txansistox 20 itself.
Reverting to the circuit of Fig. 10, after the resetting operation, the carxiers generated by the light are stored in the capacitors C43', and Cl', and the potential at that point is expressed similarly to the Equation (12), as follows:
V29 Vth + C1' + C43' (15) Hence, the voltage to be stored in the capacitor C28 is expressed by the following Equation:
V30 - Iph-Ts - - ~ ~ ~ ~ ~ ~ ~ ~ (16~.
And, the output current`I7' is expressed by the following 15 Equation: ~ -I7' = _ C28 ;TTS-Iph - - ~ 17).
As will be understood fxom this Equation, the output current I7' is free from the influence of the threshold voltage Vth.
In the cixcuit shown in Fig. 10, the timing for ampli-20 fication is coincident with that fox turning on the switch2. Hence, as shown in Fig. 13, if the drain of the transistor 20 is connected to the gate of the transistor 20 and further with the power pulse voltage 51 which is used to act as both the power supply voltage and the scanning voltage, the number 25 of wirings is so reduced as to contribute highly to the improvement in integxation.
Moreovex, there is a case in which the resetting operation of the picture cells belonging to the horizontal scanning line that has been previously read can be performed 30 simultaneousIy with the amplification of the picture cells belonging to one horizontal scanning line, e.g., an image pickup device in which interlaced scanning is not performed.
In this case, as shown in Fig. 14, the resetting transistox ~ 3 ~2280 24 of the already read picture cell can be rendered conductive by the power supply pulses 51' to be supplied to an amplifier 20'. ~ere, reference numeral 52 indicates the vertical scanning directlon. As a result, the number of wirings can be reduced to a remarkable extent.
If the resetting operation is to be performed in the circuit structure shown in Fig. 10, the potential at the node 29 has to be equal to or higher than the threshold voltage Vth before the resetting operation. Incidentally, lO if the present circuit is assembled in an IC substrate, there exists a parasitic capacitor C50 which is indicated at 50 in Fig. 10. Since the drain of the amplifying trans-istor 20 is grounded before the resetting operation and since the voltage V29 at the gate is equal to or higher 15 than the threshold voltage, the transistor 20 is rendered conductive to discharge the capacitor C50. At the time when the resetting operation is started, the capacitors Cl', C43' and C50 are connected so that the charges are distributed among these three parallel capacitors. However, since no 20 charge exists in the capacitor C50, there arises a risk that the potential at V29 should become equal to or lower than the threshold voltage Vth. As shown in Fig. 15, therefore, a presetting transistor 54 is made to have its drain, source and gate connected to the vertical signal line 30, a pre-25 setting pulse power supply 66 and a preset pulse generator53.
Fig. 16 is a chart illustrating the operating timings of the present circuit. First of all, during the time period tl to t2, the transistors 2, 54 and 24 are rendered conductive 30 to set the potential V29 of the capacitor C29 and at the node 29 at the voltage E66 of the preset voltage supply. After that, for the subsequent horizontal reading operation, it becomes necessary to release the charges of the vertical signal line 30 in advance. For this necessity, during the 35 time period t2 to t3, the voltage of the preset power supply 66 is dropped to zero to discharge the capacitor C28. After that, the potential at 53 is dropped to render the transistor 54 nonconductive. During the time period t3 to t4, the ~ ~ ~2~
capacitor 28 is charged with the signal charge by the amplifying transistor 20'. Incidentally, the resetting operation of the node 29 is simultaneously performed during the time period t0 to t4.
Examples of the whole circuit construction of devices embodying the detailed constructions thus far described are shown in Figs. 17 and 21. The elements indicated by the same reference numerals as those used in the foregoing description are -~he same. The circuit enclosed by broken 1~ lines 27 in Fig. 17 indicates the vertical scanning control circuit, and the control of one scanning line is effected by four MOS transistors 55, 56, 57 and 58. The other circuit-constructing elements are the same as those already described.
The operation of this circuit will be described with reference to Fig. 18, dealing firs-t with the operation of the circuit 27. The vertical scanning circuit is first scanned in the direction 52 to consecutively generate scanning pulses at output terminals 60 to 60"', 61 and 61' at the timings illustrated in Fig. 19. When the voltage at the point 60 takes the H level (which is sufficient to render ~a MOS transistor conductive), the transistor 56 is rendered conductive so that a voltage 65 is impressed upon the gate of the transistor 57 to render the same conductive. The conducting state of the transistor 57 continues until the scanning circuit output 60" takes the H level to ground the gate of the transistor 57. This behaviour is illustrated at V59 in Fig. 19. After that, the voltages indicated at V59' to V59"' are generated with an overlapped half period even at other points 59' to 59"'. If the drain of the transistor in the conducting state is supplied with the pulses indicated at V62 and V63 from 62 or 63, the scanning and resetting pulses indicated at V51 to V51"' are generated at the scanning lines 51 to 51"'. The internal operations of the device, as controlled by the scanning pulses so far described, will now be described with reference to Fig. 20. First of all, when the scanning line 51' takes the H level, the amplifying and switching transistors 20' and 2' connected 1 ~ 62~
therewith operate to feed out the voltage to the vertical signal line 30 in accordance with ~he voltage at the node 29'.
This behavior is illustrated at time t-2 of the voltage V30.
At time t-l, the pulses indicated at V8 are generated from the horizontal scanning pulses so that the potential at the node 30 is read out and dropped, as indicated at V30. At time t0, the scanning lines 51' and 51" simultaneously take the H level together with the preset control pulses V53 so that the termi.nal 29 is preset at the voltage E66 of the terminal 66 through the vertical signal line 30. At time tl, the scanning line 51' is dropped to the L level so that the node 29' is reset at the threshold voltage Vth of the transistor 20' by the transistor 20' having its gate and drain short-circuited by a transistor 24'. After that, at time tl, the voltage V66 is released to ground so that the voltage of the vertical scanning line is dropped to a level about zero, as indicated at V30. After that, during the time period t2 to t3, an amplifying transistor 20" belonging to the subsequent scanning line 51" is operated to generate the voltage on the vertical scanning line. These operations are subsequently repeated to effect the scanning Gperations of all the picture cells.
The fundamental structure of the present example i5 shown in section in Fig. 8 so that its fabrication steps will now be described with reference to the same Figure.
On principle, it is sufficient to apply the usual method . .
of fabricating a semiconductor device. A SiO2 film to be used as the gate insulating film is formed on the p-type silicon substrate 21 by the usual CVD process. Then, there are formed the respective gate portions (101, 102 and so on) - of polysilicon and the impurity regions (35, 36, 37, 38 and so on). On these gate portions and impurity regions, there is further formed another SiO2 film. This film is etched to form the electrode leading openings for the respective impurity regions. The SiO2 insulating film 41 is formed after the electrodes (30, 14 and so on) have been formed.
After that, in a manner to correspond to the gate portions or the like of the transistor connected with the photodiode ~ 1 62~0 1, the SiO2 insulating film ~1 is formed with an opening, in which the metal electrode 42 ls provided. This electrode 42 is overlaid by the photoelectric converting film 43.
This photoelectric converting film is made as an amorphous film of Se-As-Te chalcogenide having a thickness of ~ ~m (which may be replaced by an amorphous silicon film or the like) by the heating evaporation process. Finally, the transparent electrode of indium oxide containing Sn is formed to a thickness of about 30 nm by the sputtering process, thus finishing the fundamental portion. Inciden-tally, one picture cell is sized to ~e 40 x 40 ~m , and the n-channel ~OS transistor has a minimum channel length of 5 ~m.
Fig. 21 is a whole circuit diagram oE another embodiment which is identical to that of Fig. 17 except that the sources of the amplifying transistors 20 are commonly connected to a terminal 67 and that the voltage 33 is impressed upon the output terminal 7 through the load resistor 32. The major difference of the present circuit from that shown in Fig. 17 resides in that the circuit of Fig. 17 charges the vertical signal line 30 with a voltage in accordance with the potential at the terminal 29, whereas the present circuit drops the potential of the signal line 30 from E33 by the discharge in accordance with the voltage at the terminal 29.
The operation of the circuit of Fig. 20 is illustrated in Fig. 18. As shown, the voltage V30 is dropped during the time period t2 to t3 by the amplification and is returned to E33 each time it is read out at time t~ by the horizontal switch 3. On the other hand, the output current is inverted from that of the foregoing circuit of Fig. 17, as indicated at I7 in Fig. 18.
Fig. 22 illustrates the output signal current character-istics of the device thus fabricated. In Fig. 22: a curve 110 indicates the characteristics of the prior art device having the circuit construction shown in Fig. l; a curv~
111 indicates those of the device shown in Fig. 17; and a curve 112 indicates those of the device shown in Fig. 21.
2 ~ ~) For incident light having an intensity of 1 lux, the device with the characteristics of curve 111 can produce an output about 70 times as high as that of the prior art, and the device with the characteristics of curve 112 can produce an output about 40 times as high as those of the prior art.
Moreover, the noise characteristics indicate a low value of about 0.008 nA for all illumination intensities, as indicated by a flat line 113 in Fig. 22 (wherein the level of the noise is plotted ten times), so that a remarkably high S/N ratio can be attained.