CA1159964A - Apparatus for converting serial input sparse vector format to parallel unpacked format for input to tandem arithmetic logic units - Google Patents

Apparatus for converting serial input sparse vector format to parallel unpacked format for input to tandem arithmetic logic units

Info

Publication number
CA1159964A
CA1159964A CA000379616A CA379616A CA1159964A CA 1159964 A CA1159964 A CA 1159964A CA 000379616 A CA000379616 A CA 000379616A CA 379616 A CA379616 A CA 379616A CA 1159964 A CA1159964 A CA 1159964A
Authority
CA
Canada
Prior art keywords
operands
bits
vector
order
group
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000379616A
Other languages
English (en)
French (fr)
Inventor
James W. Kelley
Raymond C. Kort
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Control Data Corp
Original Assignee
Control Data Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Control Data Corp filed Critical Control Data Corp
Application granted granted Critical
Publication of CA1159964A publication Critical patent/CA1159964A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Complex Calculations (AREA)
CA000379616A 1980-09-29 1981-06-12 Apparatus for converting serial input sparse vector format to parallel unpacked format for input to tandem arithmetic logic units Expired CA1159964A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US191,808 1980-09-29
US06/191,808 US4371951A (en) 1980-09-29 1980-09-29 Apparatus for converting serial input sparse vector format to parallel unpacked format for input to tandem arithmetic logic units

Publications (1)

Publication Number Publication Date
CA1159964A true CA1159964A (en) 1984-01-03

Family

ID=22707017

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000379616A Expired CA1159964A (en) 1980-09-29 1981-06-12 Apparatus for converting serial input sparse vector format to parallel unpacked format for input to tandem arithmetic logic units

Country Status (6)

Country Link
US (1) US4371951A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0049039B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS5760461A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
AU (1) AU535431B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
CA (1) CA1159964A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3164722D1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (18)

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Publication number Priority date Publication date Assignee Title
JPS58214963A (ja) * 1982-06-09 1983-12-14 Hitachi Ltd ベクトル処理装置
US4630192A (en) * 1983-05-18 1986-12-16 International Business Machines Corporation Apparatus for executing an instruction and for simultaneously generating and storing related information
US4589067A (en) * 1983-05-27 1986-05-13 Analogic Corporation Full floating point vector processor with dynamically configurable multifunction pipelined ALU
JPH0731669B2 (ja) * 1986-04-04 1995-04-10 株式会社日立製作所 ベクトル・プロセツサ
US5179680A (en) * 1987-04-20 1993-01-12 Digital Equipment Corporation Instruction storage and cache miss recovery in a high speed multiprocessing parallel processing apparatus
US5057837A (en) * 1987-04-20 1991-10-15 Digital Equipment Corporation Instruction storage method with a compressed format using a mask word
US5113507A (en) * 1988-10-20 1992-05-12 Universities Space Research Association Method and apparatus for a sparse distributed memory system
US5369773A (en) * 1991-04-26 1994-11-29 Adaptive Solutions, Inc. Neural network using virtual-zero
US5717616A (en) * 1993-02-19 1998-02-10 Hewlett-Packard Company Computer hardware instruction and method for computing population counts
US6049864A (en) * 1996-08-20 2000-04-11 Intel Corporation Method for scheduling a flag generating instruction and a subsequent instruction by executing the flag generating instruction in a microprocessor
US7600104B2 (en) * 2006-08-15 2009-10-06 Peter Neumann Method and system for parallel vector data processing of vector data having a number of data elements including a defined first bit-length
CA2884096C (en) * 2012-09-05 2021-01-26 Element, Inc. System and method for biometric authentication in connection with camera-equipped devices
CN106489248A (zh) 2014-05-13 2017-03-08 埃利蒙特公司 用于与移动设备相关的电子钥匙供应和访问管理的系统和方法
JP6415607B2 (ja) 2014-06-03 2018-10-31 エレメント，インク． モバイル・デバイスに関連する出退認証および管理
AT519514B1 (de) 2017-01-13 2021-07-15 Blum Gmbh Julius Führungssystem zur Führung eines bewegbar gelagerten Möbelteiles
EP3685185A4 (en) 2017-09-18 2021-06-16 Element, Inc. METHODS, SYSTEMS AND MEDIA FOR DETECTING MYSTIFICATION DURING MOBILE AUTHENTICATION
BR112021018149B1 (pt) 2019-03-12 2023-12-26 Element Inc Método implementado por computador para detectar falsificação de reconhecimento de identidade biométrica usando a câmera de um dispositivo móvel, sistema implementado por computador e meio de armazenamento legível por computador não transitório
US11507248B2 (en) 2019-12-16 2022-11-22 Element Inc. Methods, systems, and media for anti-spoofing using eye-tracking

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5737885B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1973-12-22 1982-08-12
JPS5435743B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1973-12-24 1979-11-05
US3919534A (en) * 1974-05-17 1975-11-11 Control Data Corp Data processing system
JPS5615534B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1974-10-25 1981-04-10
US4128880A (en) * 1976-06-30 1978-12-05 Cray Research, Inc. Computer vector register processing
JPS5852265B2 (ja) * 1977-01-12 1983-11-21 株式会社日立製作所 デ−タ処理装置
US4162534A (en) * 1977-07-29 1979-07-24 Burroughs Corporation Parallel alignment network for d-ordered vector elements

Also Published As

Publication number Publication date
AU7433681A (en) 1982-04-08
AU535431B2 (en) 1984-03-22
DE3164722D1 (en) 1984-08-16
US4371951A (en) 1983-02-01
JPS5760461A (en) 1982-04-12
JPS6141027B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1986-09-12
EP0049039A1 (en) 1982-04-07
EP0049039B1 (en) 1984-07-11

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