CA1158366A - Semiconductor device of the high frequency field effect transistor type and charge coupled device using such a semiconductor - Google Patents
Semiconductor device of the high frequency field effect transistor type and charge coupled device using such a semiconductorInfo
- Publication number
- CA1158366A CA1158366A CA000363129A CA363129A CA1158366A CA 1158366 A CA1158366 A CA 1158366A CA 000363129 A CA000363129 A CA 000363129A CA 363129 A CA363129 A CA 363129A CA 1158366 A CA1158366 A CA 1158366A
- Authority
- CA
- Canada
- Prior art keywords
- layer
- gate
- field effect
- source
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 230000005669 field effect Effects 0.000 title claims description 9
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 239000003990 capacitor Substances 0.000 claims description 2
- 239000012777 electrically insulating material Substances 0.000 claims description 2
- 229910052681 coesite Inorganic materials 0.000 claims 1
- 229910052906 cristobalite Inorganic materials 0.000 claims 1
- 238000002513 implantation Methods 0.000 claims 1
- 235000012239 silicon dioxide Nutrition 0.000 claims 1
- 229910052682 stishovite Inorganic materials 0.000 claims 1
- 229910052905 tridymite Inorganic materials 0.000 claims 1
- 239000000463 material Substances 0.000 abstract description 5
- 230000010287 polarization Effects 0.000 abstract description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 27
- 238000009825 accumulation Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000002674 ointment Substances 0.000 description 2
- 241001253177 Anisotes Species 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 125000005842 heteroatom Chemical group 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229920000136 polysorbate Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/432—Heterojunction gate for field effect devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
The invention relates to high-speed semicon-ductor devices, whose control region has a junction between two different materials; the junction is formed between an n-doped AlxGa1-CAs layer and a p-doped GaAs layer in which appears a charge reversal layer for a zero polarization of AlXGa1-XAs. In addition, an insulating layer placed between the AlXGa1-XAs gate and its metal covering restricts the leakage current between the gate and the reversal layer. One application of the present invention is ultra-high frequency transistors and charge coupled devices.
The invention relates to high-speed semicon-ductor devices, whose control region has a junction between two different materials; the junction is formed between an n-doped AlxGa1-CAs layer and a p-doped GaAs layer in which appears a charge reversal layer for a zero polarization of AlXGa1-XAs. In addition, an insulating layer placed between the AlXGa1-XAs gate and its metal covering restricts the leakage current between the gate and the reversal layer. One application of the present invention is ultra-high frequency transistors and charge coupled devices.
Description
~ 5~3~
S~ICONDUC~OR ~)~ C~ T}~F_ JGH ~'RE~
~ELD ~ C'T '~R~ SISTOR rllY~E
~SING SUCH A S~IlCO~ C lroR
~ACYGRO~D O~ IE~ V~TION
The present invention relates to improve~ents to serniconduc~or devices of the field e~ect transistor type and rnore specifically those having a high cutoff frequency A field effect semiconductor device is known ~hich COJnpriseS a semi insulating substrate, source a~d drain regions,-- an active GaAs layer and a gate ~hich, with the active layer~ forms an isotope n-n heterojunction ~he AlxGa1 xAs ~ate can be of limited thickness and covered with an insulating layer in order to reduce the leakage current through -the ~rate.
This type of semicond~ctor represents an important advance in the sense O:r increasing the cutoff frequencies of field ef~ect iransistors, but it still has two limitations, namely its output impedence and its "no-rmally conductive' operating mo~e.
~ irstly the active GaAs layer is constituted by two regions. ~he first highly doped n type region is the electron accumulation region, whilst the other much less doped region~ which is also of then -t~pe9 occupies most of the thickness of the GaAs layer. ~his second, slightly doped region behaves like a resistor connected in parallel with that constituted by the accumulation region : these two parallel resistors form a low output resistor~
Secondly this type of transistor is in the "normally conducti~re" position, i.e. without any~
~5 polari~ation of the control gate a cuxrent passes ~ ~8~
bet~een the s~uxce and -the drain, when the latter is polarized relative to the source. The fact that the transistor is conductive in the absence of a control voltage can be prejudicial in cer~in applications.
~RIEF S~V~lARY 0~ TH~ ~V~TlON
_, nle object o~ the present invention is to increase the output resistance of the transistor ~nd to make it "normally non-conductive", i,e.
it does not permit the passage of the current when the gate is not polari~,ed. ~oth these objects are simultaneously achieved by the use of a weakly doped p-type GaAs layer in place of the n-type GaAs layer described hereinbefore. ~us, the he~erojunc-tion used is p-n anisotype (P GaAs/n AlxGa1 ~As )O Power transmission is now ensured by a charge reversal region and not by an electron accw~ulation region, ~ore specifically the present invention relates to a ~ield ef~ect semiconductor ~or high frequencies comprising, supported by a semi-insulating substrate, a control region constituted by a heterojunction J wherein the ; anisotropic heterojunction is formed by a weakly doped p-type GaAs ac-tive layer and by a type n AlxGa1 xAs layer serving as a transistor control gate and wherein an elec-trically insulating material layer is interposed between the gate layer and the contacting metal covering on the ~ate~
~RIEF DESCRIPTION 0~ ~HE RAWINGS
The i~vention is described in greater detail hereinafter relative to non limitative embodiments and the attached drawings, wherein show:
~5 ~ig~ 1 a section through the prior art n-n
S~ICONDUC~OR ~)~ C~ T}~F_ JGH ~'RE~
~ELD ~ C'T '~R~ SISTOR rllY~E
~SING SUCH A S~IlCO~ C lroR
~ACYGRO~D O~ IE~ V~TION
The present invention relates to improve~ents to serniconduc~or devices of the field e~ect transistor type and rnore specifically those having a high cutoff frequency A field effect semiconductor device is known ~hich COJnpriseS a semi insulating substrate, source a~d drain regions,-- an active GaAs layer and a gate ~hich, with the active layer~ forms an isotope n-n heterojunction ~he AlxGa1 xAs ~ate can be of limited thickness and covered with an insulating layer in order to reduce the leakage current through -the ~rate.
This type of semicond~ctor represents an important advance in the sense O:r increasing the cutoff frequencies of field ef~ect iransistors, but it still has two limitations, namely its output impedence and its "no-rmally conductive' operating mo~e.
~ irstly the active GaAs layer is constituted by two regions. ~he first highly doped n type region is the electron accumulation region, whilst the other much less doped region~ which is also of then -t~pe9 occupies most of the thickness of the GaAs layer. ~his second, slightly doped region behaves like a resistor connected in parallel with that constituted by the accumulation region : these two parallel resistors form a low output resistor~
Secondly this type of transistor is in the "normally conducti~re" position, i.e. without any~
~5 polari~ation of the control gate a cuxrent passes ~ ~8~
bet~een the s~uxce and -the drain, when the latter is polarized relative to the source. The fact that the transistor is conductive in the absence of a control voltage can be prejudicial in cer~in applications.
~RIEF S~V~lARY 0~ TH~ ~V~TlON
_, nle object o~ the present invention is to increase the output resistance of the transistor ~nd to make it "normally non-conductive", i,e.
it does not permit the passage of the current when the gate is not polari~,ed. ~oth these objects are simultaneously achieved by the use of a weakly doped p-type GaAs layer in place of the n-type GaAs layer described hereinbefore. ~us, the he~erojunc-tion used is p-n anisotype (P GaAs/n AlxGa1 ~As )O Power transmission is now ensured by a charge reversal region and not by an electron accw~ulation region, ~ore specifically the present invention relates to a ~ield ef~ect semiconductor ~or high frequencies comprising, supported by a semi-insulating substrate, a control region constituted by a heterojunction J wherein the ; anisotropic heterojunction is formed by a weakly doped p-type GaAs ac-tive layer and by a type n AlxGa1 xAs layer serving as a transistor control gate and wherein an elec-trically insulating material layer is interposed between the gate layer and the contacting metal covering on the ~ate~
~RIEF DESCRIPTION 0~ ~HE RAWINGS
The i~vention is described in greater detail hereinafter relative to non limitative embodiments and the attached drawings, wherein show:
~5 ~ig~ 1 a section through the prior art n-n
2 --i1~ , ~ ~5~6~
isotype hetero~unction F~T transistorO
~igs~2 & 3 er,er~y b~1nd di~1F,l-arns of an n-n isotype heterojunction for zero and positive ~ate polarizations.
5 ~igs,4 & 5 energy ban~ diagram~ oi arl anisotype pGaAs/n AlyGa1 xAs he~teroj~lcti.on ~or zero and positive ~ate. ~olarizations, ~ig. 6 a sec-tion througll an anisotype p GaAs /n AlXGa1_xAs he-terojunc~ion ~ transistor according to the inven-tion, ~igJ 7 a section through another e~bodi~ent of an ~ET transistor according to the invention~
DETAIlED DES~RIP~ION OF IHE PREF~RRED ~OD~E~S
~ ig~ 1 shows the structure of a prior art n-n isotype heterojunc-tlon transistor. It comprises a semi-insulating gallium arsenide GaAs substrate 1 on ~hich there is a weakly doped n-type GaAs active layer 2 ~hich supports a type n AlxGa1 xAs control gate 3, The n* source region.
4 and drain region 5 are dif~used or implanted in the GaAs substrate. ~he output resistance 6 - be-tween the source a~d -the drain is located in 2~ the weakly doped active.region 20 ~ igs, 2 and 3 show ener~y band dia~rams of a n GaAs - n AlxGal x A~ heterojunction.
~he GaAs layer is at the potential V1 and the - AlxGa1 xAs layer at potential V2~ ~he ~ermi 30 - level is represented by the straight line 7, the conduction band by curve 8 and the valence band by curve 9. In ~ig. 2 where -the t,wo materials are at the same po-te~-tial V1 - V2 the band curves are such that on the Ga.As side there is ~n electron accumulation~region 10 at the : ~, . . .
~ ~ 5 ~
heterojunction interface. ln ~ig. 3 where AlxGa1 xAs is positively polarized ~elative to GaAs, ~2,~V1, said electron accumulation area 10 is extre~ely pronounced. ~igs. 2 and 5 3 sho~ing the band diagrams o~ r.-n isotype heterojunction provide a better unders-tanding of the ~ transistor ~ith a p-~-, anisotype heterojunction and charge reversal according -to the present invention.
~igs. 4 and 5 show energy band dia~rarns o~ a p type AlXGa1 xAs anisotype heterojunction of the n-type in accordance with the Anderson model. ~he same references identify the same elements as in ~igs~ 2 and 3. In ~ig. 4 where the two materials are at the same potential V1 = Y2 the band curves reveal a region which is Iree from holes 11. ~en AlxGa1 xAs is ' positively polarized ~elative to GaAs (~ig. 5) the depopulation of holes is accen~uated and if the polarization voltage is sufficiently high the - concentration of holes becomes smaller than t,he electron concentration, so that at the heterojunction interface there is an in~ially p.-doped n type GaAs layerr ~his layer is called the charge reversal layer or more simply reversal layer 12. In much the same way as at the accumulation layers existing in the n-n isotype heterojunctions the reversal layers have a high electron mobility if ~the P type GaAs material contains few impurities, i,e.
is weakl~ ~-dopedO
In view of the fact that the source-drain current is ensured by the reversal layer in the absence of gate polari~,ation and with no reversal layer the source-drain curren-t i9 zeroO ~husg . , . .. . . _ .... . ., ... .. . .. . _ . . , _ . . . _ -- . . . .
1 ~583~`6 the transistor ~unction~s in the no~ally non-conductive mode.
The source-drain current flo~rs i.n a preferred manner in the reversal laye.r ~ld the output resistance of the transi~tor is higher than in the case o~ n-~l isotype heterojunction, However~ a leakage current phenomenon can occur between the reversal layer on the GaAs side and AlxGa1 ~As~ In the case of thisp-n anisotype heterojunction the leakage current is prevented by interposing an insulant between the AlxGa1 xAs layer and the metal covering of the ~ate.
~ig~ 6 is a sectional view o~ a first embodime~t of the transistor according to the invention~ taking account of the a.forementioned means for increasing the output resistance and eliminating the leaXage currents, ~he anisotype p-n he-terojl~ction ~
transistor of ~ig. 6 comprises a semi-insulating GaAs substrate 1, a weakly doped) p-type GaAs active layer 2, a n-type AlxGa1 xAs layer ~, a source region 4 and a drain region 5. A layer ~3 of insula~ing material, such as silica, is .25 deposited on the AlxGa1 xAs layer and beneath the gate contacting metal coveri~g 14. ~he source and drain regions 4, 5 respectively are n+ doped and penetrate the p-doped GaAs layer up to the charge reversal zone, The processes for producing the source and drain regions are . -known, as are the processes~for depositing insulating material on the AlxGa1 xAs, ~ he second embodiment of thep-n anisot~pe he-terojunction ~ET transistor is shown in ~ig.
~ As previously it comprise~ a semi-insulating L 1 $8~6 substrate 1, a ~:eakly doped ~-type GaAs layer 2, an AlxGa1 xAs layer 3 and an insulating oxide layer ~3. Ho~lever, the source and drain are obtained directly by the source metal oovering 15 and drain metal covering 16 on the side~ of the projec~ing part constituted by t~e stack of GaAs and AlxGa1 xAs layers called a mesa. No other precautions being taken, tnese metal coverings cover the sides of the GaAs and AlxGa1 xAs layers and as they are of the type used for ohmic contacting on type n GaAs with a doping level of approxi~ately 10~7 e ~ cm ~, they form ohmic c~ntacts with the ~eversal layer located in layer 2 in the vicinity of the heterojunctionO To prevent them creati~g a lea~age current bet~een the source and the~rain across the AlxGa1 xAs layer ~, the latter is insulated from the metal coverings by oxide grooves 17 and 18 havi~g a thickness be~een a Iew dozen to a few hundred hngstrUms and which su~round the AlxGa1 xAs layer 3.
~he reversal layer is formed in an anisotype . heterojunction in the same way as the reversal layer in a reversal MOS structure. ~rthermore, the addition of an insulating layer to the Al~Gal xAs layer makes the structures of ~.igs~ 6 and 7 very similar to MIS or MOS structures.
Howevert the interposition of a n type. Al.xGa1 xAs layer between the p type GaAs layer and -the insulating layer give the anisotype heterojunc-tion struc~ures the property of high electron mobility in the reversal layer, whereas the electron mobility . in the reversal layer of an MOS structure is low.
~hus, p-n anisotype heterojunction ~ transistors have higher cutoff frequencies than MOS tran.sistors~
_ ~ _ 1 ~5~6 '~he applications utilizing the reversal ].ayer of a p-~ anisotype heterojunction are not limited only to field effect tra~sistorsO In much the same way as MOS the .heterojl~ction st~cture with reversal layer can also be used in charge coupled devices constituted by a sequence of MOS capacitor.s, ~.Thereof each is formed by a j~-lction bet~een a ~ate and a substrate.
,~,.. .
isotype hetero~unction F~T transistorO
~igs~2 & 3 er,er~y b~1nd di~1F,l-arns of an n-n isotype heterojunction for zero and positive ~ate polarizations.
5 ~igs,4 & 5 energy ban~ diagram~ oi arl anisotype pGaAs/n AlyGa1 xAs he~teroj~lcti.on ~or zero and positive ~ate. ~olarizations, ~ig. 6 a sec-tion througll an anisotype p GaAs /n AlXGa1_xAs he-terojunc~ion ~ transistor according to the inven-tion, ~igJ 7 a section through another e~bodi~ent of an ~ET transistor according to the invention~
DETAIlED DES~RIP~ION OF IHE PREF~RRED ~OD~E~S
~ ig~ 1 shows the structure of a prior art n-n isotype heterojunc-tlon transistor. It comprises a semi-insulating gallium arsenide GaAs substrate 1 on ~hich there is a weakly doped n-type GaAs active layer 2 ~hich supports a type n AlxGa1 xAs control gate 3, The n* source region.
4 and drain region 5 are dif~used or implanted in the GaAs substrate. ~he output resistance 6 - be-tween the source a~d -the drain is located in 2~ the weakly doped active.region 20 ~ igs, 2 and 3 show ener~y band dia~rams of a n GaAs - n AlxGal x A~ heterojunction.
~he GaAs layer is at the potential V1 and the - AlxGa1 xAs layer at potential V2~ ~he ~ermi 30 - level is represented by the straight line 7, the conduction band by curve 8 and the valence band by curve 9. In ~ig. 2 where -the t,wo materials are at the same po-te~-tial V1 - V2 the band curves are such that on the Ga.As side there is ~n electron accumulation~region 10 at the : ~, . . .
~ ~ 5 ~
heterojunction interface. ln ~ig. 3 where AlxGa1 xAs is positively polarized ~elative to GaAs, ~2,~V1, said electron accumulation area 10 is extre~ely pronounced. ~igs. 2 and 5 3 sho~ing the band diagrams o~ r.-n isotype heterojunction provide a better unders-tanding of the ~ transistor ~ith a p-~-, anisotype heterojunction and charge reversal according -to the present invention.
~igs. 4 and 5 show energy band dia~rarns o~ a p type AlXGa1 xAs anisotype heterojunction of the n-type in accordance with the Anderson model. ~he same references identify the same elements as in ~igs~ 2 and 3. In ~ig. 4 where the two materials are at the same potential V1 = Y2 the band curves reveal a region which is Iree from holes 11. ~en AlxGa1 xAs is ' positively polarized ~elative to GaAs (~ig. 5) the depopulation of holes is accen~uated and if the polarization voltage is sufficiently high the - concentration of holes becomes smaller than t,he electron concentration, so that at the heterojunction interface there is an in~ially p.-doped n type GaAs layerr ~his layer is called the charge reversal layer or more simply reversal layer 12. In much the same way as at the accumulation layers existing in the n-n isotype heterojunctions the reversal layers have a high electron mobility if ~the P type GaAs material contains few impurities, i,e.
is weakl~ ~-dopedO
In view of the fact that the source-drain current is ensured by the reversal layer in the absence of gate polari~,ation and with no reversal layer the source-drain curren-t i9 zeroO ~husg . , . .. . . _ .... . ., ... .. . .. . _ . . , _ . . . _ -- . . . .
1 ~583~`6 the transistor ~unction~s in the no~ally non-conductive mode.
The source-drain current flo~rs i.n a preferred manner in the reversal laye.r ~ld the output resistance of the transi~tor is higher than in the case o~ n-~l isotype heterojunction, However~ a leakage current phenomenon can occur between the reversal layer on the GaAs side and AlxGa1 ~As~ In the case of thisp-n anisotype heterojunction the leakage current is prevented by interposing an insulant between the AlxGa1 xAs layer and the metal covering of the ~ate.
~ig~ 6 is a sectional view o~ a first embodime~t of the transistor according to the invention~ taking account of the a.forementioned means for increasing the output resistance and eliminating the leaXage currents, ~he anisotype p-n he-terojl~ction ~
transistor of ~ig. 6 comprises a semi-insulating GaAs substrate 1, a weakly doped) p-type GaAs active layer 2, a n-type AlxGa1 xAs layer ~, a source region 4 and a drain region 5. A layer ~3 of insula~ing material, such as silica, is .25 deposited on the AlxGa1 xAs layer and beneath the gate contacting metal coveri~g 14. ~he source and drain regions 4, 5 respectively are n+ doped and penetrate the p-doped GaAs layer up to the charge reversal zone, The processes for producing the source and drain regions are . -known, as are the processes~for depositing insulating material on the AlxGa1 xAs, ~ he second embodiment of thep-n anisot~pe he-terojunction ~ET transistor is shown in ~ig.
~ As previously it comprise~ a semi-insulating L 1 $8~6 substrate 1, a ~:eakly doped ~-type GaAs layer 2, an AlxGa1 xAs layer 3 and an insulating oxide layer ~3. Ho~lever, the source and drain are obtained directly by the source metal oovering 15 and drain metal covering 16 on the side~ of the projec~ing part constituted by t~e stack of GaAs and AlxGa1 xAs layers called a mesa. No other precautions being taken, tnese metal coverings cover the sides of the GaAs and AlxGa1 xAs layers and as they are of the type used for ohmic contacting on type n GaAs with a doping level of approxi~ately 10~7 e ~ cm ~, they form ohmic c~ntacts with the ~eversal layer located in layer 2 in the vicinity of the heterojunctionO To prevent them creati~g a lea~age current bet~een the source and the~rain across the AlxGa1 xAs layer ~, the latter is insulated from the metal coverings by oxide grooves 17 and 18 havi~g a thickness be~een a Iew dozen to a few hundred hngstrUms and which su~round the AlxGa1 xAs layer 3.
~he reversal layer is formed in an anisotype . heterojunction in the same way as the reversal layer in a reversal MOS structure. ~rthermore, the addition of an insulating layer to the Al~Gal xAs layer makes the structures of ~.igs~ 6 and 7 very similar to MIS or MOS structures.
Howevert the interposition of a n type. Al.xGa1 xAs layer between the p type GaAs layer and -the insulating layer give the anisotype heterojunc-tion struc~ures the property of high electron mobility in the reversal layer, whereas the electron mobility . in the reversal layer of an MOS structure is low.
~hus, p-n anisotype heterojunction ~ transistors have higher cutoff frequencies than MOS tran.sistors~
_ ~ _ 1 ~5~6 '~he applications utilizing the reversal ].ayer of a p-~ anisotype heterojunction are not limited only to field effect tra~sistorsO In much the same way as MOS the .heterojl~ction st~cture with reversal layer can also be used in charge coupled devices constituted by a sequence of MOS capacitor.s, ~.Thereof each is formed by a j~-lction bet~een a ~ate and a substrate.
,~,.. .
Claims (7)
1. A field effect semiconductor for high frequencies comprising, supported by a semi-insulating substrate, source and drain access regions, and a control region constituted by a heterojunction, wherein the heterojunction is anisotype and formed by a weakly doped p-type GaAs active layer and by an n-type AlxGa1-xAs layer serving as a transistor control gate and wherein an electrically insulating material layer is interposed between the gate layer and a contacting metal covering on the gate.
2. A field effect semiconductor device according to Claim 1, comprising a type n charge reversal zone which is conductive when a positive voltage is applied to the control grid, said reversal zone being constituted by the type p GaAs active layer region located in the vicinity of the heterojunction between the active layer and the control gate.
3. A field effect semiconductor device according to Claim 1, wherein, for the purpose of reducing leakage currents, the layer deposited on the AlxGa1-xAs gate is constituted by silica SiO2.
4. A field effect transistor, wherein the semiconductor according to Claim 1 is completed by source and drain access regions obtained by ionic implantation in the semi-insulating substrate.
5. A field effect transistor, wherein a semiconductor according to Claim 1 is completed by source and drain access regions produced by metal cover-ings deposited on the free face of the substrate and on the sides of the active layer, the sides of the gate being separated from said metal coverings by an insulat-ing groove interposed between the gate and source and between the gate and drain.
6. A field effect transistor according to Claims 4 or 5 wherein the charge reversal zone is in ohmic contact with the source and drain regions.
7. A charge coupled device, wherein each of the capacitors constituting the same is formed by an anisotype heterojunction semiconductor according to any one of the Claims 1 to 3.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR7926611 | 1979-10-26 | ||
| FR7926611A FR2469002A1 (en) | 1979-10-26 | 1979-10-26 | HIGH FREQUENCY FIELD EFFECT SEMICONDUCTOR DEVICE AND TRANSISTOR AND CHARGE TRANSFER DEVICE USING SUCH A SEMICONDUCTOR |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1158366A true CA1158366A (en) | 1983-12-06 |
Family
ID=9231080
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000363129A Expired CA1158366A (en) | 1979-10-26 | 1980-10-23 | Semiconductor device of the high frequency field effect transistor type and charge coupled device using such a semiconductor |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP0027761B1 (en) |
| JP (1) | JPS5685871A (en) |
| CA (1) | CA1158366A (en) |
| DE (1) | DE3067774D1 (en) |
| FR (1) | FR2469002A1 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5953714B2 (en) * | 1979-12-28 | 1984-12-26 | 富士通株式会社 | semiconductor equipment |
| FR2489045A1 (en) * | 1980-08-20 | 1982-02-26 | Thomson Csf | GAAS FIELD EFFECT TRANSISTOR WITH NON-VOLATILE MEMORY |
| FR2497603A1 (en) * | 1981-01-06 | 1982-07-09 | Thomson Csf | TRANSISTOR WITH LOW SWITCHING TIME OF NORMALLY BLOCKING TYPE |
| FR2520157B1 (en) * | 1982-01-18 | 1985-09-13 | Labo Electronique Physique | SEMICONDUCTOR DEVICE OF THE HETEROJUNCTION TRANSISTOR TYPE (S) |
| GB2172742B (en) * | 1985-03-21 | 1988-08-24 | Stc Plc | Photoconductor |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4075652A (en) * | 1974-04-17 | 1978-02-21 | Matsushita Electronics Corporation | Junction gate type gaas field-effect transistor and method of forming |
| US4065781A (en) * | 1974-06-21 | 1977-12-27 | Westinghouse Electric Corporation | Insulated-gate thin film transistor with low leakage current |
| US4160261A (en) * | 1978-01-13 | 1979-07-03 | Bell Telephone Laboratories, Incorporated | Mis heterojunction structures |
| FR2465317A2 (en) * | 1979-03-28 | 1981-03-20 | Thomson Csf | FIELD EFFECT TRANSISTOR WITH HIGH BREAKAGE FREQUENCY |
-
1979
- 1979-10-26 FR FR7926611A patent/FR2469002A1/en active Granted
-
1980
- 1980-10-14 EP EP19800401467 patent/EP0027761B1/en not_active Expired
- 1980-10-14 DE DE8080401467T patent/DE3067774D1/en not_active Expired
- 1980-10-23 CA CA000363129A patent/CA1158366A/en not_active Expired
- 1980-10-24 JP JP14924680A patent/JPS5685871A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH028453B2 (en) | 1990-02-23 |
| EP0027761A1 (en) | 1981-04-29 |
| DE3067774D1 (en) | 1984-06-14 |
| FR2469002A1 (en) | 1981-05-08 |
| JPS5685871A (en) | 1981-07-13 |
| FR2469002B1 (en) | 1984-02-17 |
| EP0027761B1 (en) | 1984-05-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4422089A (en) | Semiconductor device having a reduced surface field strength | |
| US4172260A (en) | Insulated gate field effect transistor with source field shield extending over multiple region channel | |
| US4835581A (en) | Electron gas hole gas tunneling transistor device | |
| KR100542963B1 (en) | Field effect transistor | |
| JPH0371776B2 (en) | ||
| JPH027532A (en) | Laminated channel field effect transistor | |
| US5359220A (en) | Hybrid bipolar/field-effect power transistor in group III-V material system | |
| US4213140A (en) | Insulated-gate semiconductor device | |
| US3263095A (en) | Heterojunction surface channel transistors | |
| GB1393792A (en) | Field effect transistor | |
| CA1158366A (en) | Semiconductor device of the high frequency field effect transistor type and charge coupled device using such a semiconductor | |
| JPS62274783A (en) | Semiconductor device | |
| JPH03248436A (en) | Field effect transistor of schottky barrier junction gate type | |
| US4652896A (en) | Modulation doped GaAs/AlGaAs field effect transistor | |
| US4903091A (en) | Heterojunction transistor having bipolar characteristics | |
| US4771324A (en) | Heterojunction field effect device having an implanted region within a device channel | |
| US4910562A (en) | Field induced base transistor | |
| JPH0521762A (en) | Semiconductor device with fet and manufacture method | |
| JPS61147577A (en) | Complementary semiconductor device | |
| US4965645A (en) | Saturable charge FET | |
| JPS6242569A (en) | Field effect transistor | |
| JPS626352B2 (en) | ||
| JPS58100456A (en) | Ultraspeed transistor | |
| US4616242A (en) | Enhancement and depletion mode selection layer for field effect transistor | |
| JP2721513B2 (en) | Method for manufacturing compound semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |