CA1145060A - Thyristor having improved switching behavior - Google Patents
Thyristor having improved switching behaviorInfo
- Publication number
- CA1145060A CA1145060A CA000364265A CA364265A CA1145060A CA 1145060 A CA1145060 A CA 1145060A CA 000364265 A CA000364265 A CA 000364265A CA 364265 A CA364265 A CA 364265A CA 1145060 A CA1145060 A CA 1145060A
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- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 101100168115 Neurospora crassa (strain ATCC 24698 / 74-OR23-1A / CBS 708.71 / DSM 1257 / FGSC 987) con-6 gene Proteins 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/7404—Thyristor-type devices, e.g. having four-zone regenerative action structurally associated with at least one other device
- H01L29/742—Thyristor-type devices, e.g. having four-zone regenerative action structurally associated with at least one other device the device being a field effect transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/744—Gate-turn-off devices
- H01L29/745—Gate-turn-off devices with turn-off by field effect
- H01L29/7455—Gate-turn-off devices with turn-off by field effect produced by an insulated gate structure
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
A thyristor has a semiconductor body which includes first and second base layers which are adjacent and contacting one another. An n-emitter layer contacts the first base layer and carries a first electrode. A p-emitter layer contacts the second base layer and carries a second electrode. Controllable metal-insulator-semiconductor emitter short circuit structures are located at at least one boundary surface of the semiconductor body and each include first and second semiconductor regions of a first conductivity type, the first semi-conductor region contacting the first electrode, the second semiconductor region contacting the first base layer, and an intermediate third semiconductor region of the second, opposite conductivity type between the first and second regions adjacent the boundary surface. An insulated gate covers the intermediate third region. The metal-insulator-semiconductor structures comprise at least one depletion type structure and at least one enhancement type structure. A first common terminal is connected to the gate of each depletion type structure and a second common terminal is connected to the gate of each enhancement type struc-ture. In a particular embodiment, a third common emitter terminal is connected to the first and second common emitter terminals.
A thyristor has a semiconductor body which includes first and second base layers which are adjacent and contacting one another. An n-emitter layer contacts the first base layer and carries a first electrode. A p-emitter layer contacts the second base layer and carries a second electrode. Controllable metal-insulator-semiconductor emitter short circuit structures are located at at least one boundary surface of the semiconductor body and each include first and second semiconductor regions of a first conductivity type, the first semi-conductor region contacting the first electrode, the second semiconductor region contacting the first base layer, and an intermediate third semiconductor region of the second, opposite conductivity type between the first and second regions adjacent the boundary surface. An insulated gate covers the intermediate third region. The metal-insulator-semiconductor structures comprise at least one depletion type structure and at least one enhancement type structure. A first common terminal is connected to the gate of each depletion type structure and a second common terminal is connected to the gate of each enhancement type struc-ture. In a particular embodiment, a third common emitter terminal is connected to the first and second common emitter terminals.
Description
o BACKGROUND OF THE INVENTION
Field of the Invention The invention relates to a thyristor and to a method of operating the same, in which the thyristor has a semiconductor body which contains an outside n-emitter layer provided with a cathode, an external p-emitter layer provided ~ith an anode and two base layers respectively adjacent to the cathode and anode layers, and more particularly to such a thyristor in which controllable emitter circuits are designed as MIS structures and are arranged at at least one boundary surface of the semiconductor body, the emitter short circuits respec-tively exhibiting a first semiconductor region of a first conductivity type connected to the cathode ~anode), a second semiconductor region of the first conductivity type connected to a base layer, and an intermediate layer of the second conductivity type positioned between these regions, the intermediate layer being covered by a gate which is electrically insulated with respect to the semi-conductor body.
Description of the Prior Art Thyristors of the type generally mentioned above are known in the art from United States 3,243,669. Upon application of a control voltage to the gate of a MIS structure, a short circuit path is activated which bridges the pn junc-tion between the emitter layer connected to the cathode (anode) and the adjacent base layer. This results in a transfer of the thyristor from the current-con-ducting state into the blocked state in which practically no current flows bet-~een the cathode and the anode despite the voltage adjacent in the forward con-ducting direction. The change from the blocked state into the current-conduct-ing state occurs by applying a further control voltage to the gate of a further MIS structure which bridges the pn junction between the two base layers in a low-resistance manner. At the same time, the control voltage switching the -- 1 -- i ~gL5~6~
short circuit path on is switched off for the duration of the current-conducting state.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a thyristor of the type generally mentioned above which can be triggered, and again blocked, in a controlled manner by simple control operations.
The above object is achieved, in apparatus o-f the type described above, in that at least one MIS structure of the depletion type and at least one MIS
structure of the enhancement type are provided and in that a common control voltage terminal is provided for the gates of the MIS structures of the one type <~ld a common control voltage terminal are provided for the gates of the MIS
structures of the other type.
The advantage attainable in practicing the present invention particu-larly lies in that, after supply of first control pulse to the gate of at least one MIS structure of the enhancement type ~depletion type), the thyristor locat-ed in the current-conducting state is blocked until it agai-n triggers upon occurrence of a second control pulse which is supplied to the gate of at least one MIS structure of the depletion type (enhancement type). It is not necessary for retaining the blocked or current-conducting state to supply a control voltage ~O to the MIS structures, as is the case in known thyristors with MIS short circuit paths. Thereby, the MIS structures of the one type which are only temporarily shut off during the triggering operation determine the stability of a thyristor constructed iTI accordance with the invention, i.e. its reliability against un-intentional triggering operations upon occurrence of voltages poled in the for-ward-conducting direction at the anode-cathode path. Finally, a control of the pn junction between the two base layers which is undertaken in the known thyris-tors of the type initially mentioned is also eliminated.
~5~
Thus, in accordance with one broad aspect of the invention, there is provided, in a thyristor structure of the type in which a semiconductor body in-cludes first and second base layers adjacent and contacting one another, an n-emitter layer contacting the first base layer, a first electrode contacting the n-emitter layer, a p-emitter layer contacting the second base layer, a second electrode contacting the p-emitter layer, and controllable metal-insulator-semi-conductor emitter short circuit structures located at at least one boundary surface of the semiconductor body, each of the short circuit structures includ-ing a first semiconductor region of a first conductivity type contacting the ~irst electrode, a second semiconductor region of the first conductivity type contacting the adjacent base layer, an intermediate third semiconductor region of a second, opposite conductivity type between said first and second regions adjacent the boundary surface, and an insulated gate carried over the interme-diate third region, the improvement wherein: ~he metal-insulator-semiconductor structures comprise at least one depletion type structure and at least one enhancement type structure; a first common terminal is connected to the gate of each depletion type structure; and a second common terminal is connected to the gate of each enhancement type structure.
In accordance with another broad aspect of the invention there is provided a method of operating a thyristor structure of the type in which a semiconductor body includes first and second base layers adjacent and contact-ing one another, an n-emitter layer contacting the first base layer, a first electrode contacting the n-emitter layer, a p-emitter layer contacting the second base layer, a second electrode contacting the p-emitter layer~ and con-trollable metal-insulator semiconductor emitter short circuit structures located at at least one boundary surface of the semiconductor body, each of the short circuit structures including a first semiconductor region of a first _ 2a -, ~
1~5~6~
conductivity type contacting the first electrode, a second semiconductor region of the first conductivity type contacting the adjacent base layer, an intermediate third semiconductor region of a second, opposite conductivity type between said first and second regions adjacent the boundary surface, and an insulated gate carried over the intermediate third region, and in which the metal-insulator-semiconductor structures comprise at least one depletion type structure and at least one enhancement type structure, a first common terminal is connected to the gate of each depletion type structure, and a second common terminal is connected to the gate of each enhancement type structure, comprising the steps of: applying a first voltage pulse of a first polarity to the first common terminal; and applying a second voltage pulse of a second polarity to the second common terminal.
- 2b -~ " i ~S~6~
BRIEF DESCRIPTION OF THE DRAWINGS
Other objects, features and advantages of the invention, its organiza-tion, construction and operation will be best understood from the following detailed description, taken in conjunction with the accompanying drawings, on which:
Figure 1 is a cross sectional view of a first exemplary embodiment of the invention;
Figure 2 is a plan view of the embodiment of Figure l;
Figure 3 is a cross sectional view of a second exemplary embodiment of the invention; and Figure 4 is a cross sectional view of a third exemplary embodiment of the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring to Figures 1 and 2, a semiconductor body comprises semicon-ductor layers 1--4 of alternating conductivity type and includes, for example, doped silicon. The outer n-conductive layer 1 is designated as the n-emitter layer and the outer p-conduc~ive layer 4 is designated as the p-emitter layer.
The p-conductive layer 2 and the n-conductive layer 3 represent the base layers.
The p-emitter layer 4 is provided with an anode 5 which has an anode terminal A, wllereas the n-emitter layer 1 is contacted by the cathode 6 which is provided with a cathode terminal K. The n-emitter layer 1 is advantageously designed as a strip and can be seen in the plan view of Figure 2 as a vertically-extending ~trip.
In Figure 1, which illustrates a cross-sectional view taken along the line I--I of Figure 2~ p-conductive semiconductor regions 7 and 8 are illustrat-ed which are provided in the n-emitter layer 1 in such a manner that they extend up to the boundary surface la of the semiconductor body. In Figure 2, the sur-~5~36~
faces of the semiconductor regions are illustrated with hatching for the purpose of greater clarity. The regions 7 and 8 are respectively contacted, edge-wise, by the cathode 6. Individual zones 9, 10 and 11 of the base layer 2 extend up to the boundary surface la. The regions 7 and 8 are separated from one another by the zone 9.
The region 7 forms a first p-region; the zone 10 forms a second p-region; and the portion of the emitter layer 1 lying inbetween forms an n-inter-mediate layer. A thin, electrically-insulating layer 12 comprising, for example, SiO2 is provided on the boundary surface la, a gate 13 being arranged on the electrically insulating layer 12 in such a manner that it covers the n-inter-mediate layer. The portions 7, 9, 10, 12 and 13 form a MIS s~ructure. If it belongs to the depletion type, then, without influence of a voltage at the gate 13, a p-conductive inversion channel 14 is located at the boundary surface la between the regions 7 and 10, the p-conductive inversion channel 14 conductively connecting the regions with one another. If one applies a positive control vol-tage to a control voltage terminal Gl of the gate 13, the inversion channel 14 is eliminated. If the MIS structure is of the depletion type, then there is no inversion channel 14 given a voltage-free gate 13. This is only constructed upon application of a negative control voltage to the terminal Gl by means of in-version of the emitter layer 1. The inversion channel 14, therefore, represents a controllable emitter short circuit which either connects or does not connect the base layer 2 to the region 7 and, therefore, to the cathode 6 as a function of a control voltage supplied to the ~erminal Gl, the connection being a low-resiStance connection.
A corresponding MIS structure 8, 9, 11, 15 and 16 is produced at the right edge of the n-emitter layer 1 by means of the arrangement of an electri-cally-insulating layer 15 comprising, for example, SiO2, on which a gate 16 con-6(~
nected to a terminal G2 is provided, the MIS structure 8, 9, 11, 15 and 16 representing an emitter short circuit controllable by way of the terminal G2.
It is an essential feature of the invention that the one of the two MIS structures, for example the structure 7, 9, 10, 12 and 13, belongs to the depletion type and the other MIS structure, i.e. the structure 8, 9, 11, 12 and 16 in the exemplary embodiment, belongs to the enhancement type. A feature equivalent to this, however, can be seen in that both structures are of the depletion type and a positive bias voltage is supplied to one of the structures, for example to the structure 8, 9, 11, 15 and 16 via the terminal G2 assigned l~ thereto. Thereby, the bias voltage first prevents a channel formation. A short circuit channel only becomes effective when a further control voltage which ex-hibits a polarity opposite to that of the bias voltage is supplied to the termi-nal. On the other hand, both MIS structures can be of the enhancement type, whereby a negative bias voltage is then supplied to one of the structures which effects the formation of an inversion channel. What is essential to all of these variations is that, under certain conditions upon incorporation of a bias voltage supplied to the terminal Gl or the terminal G2, one of the two MIS structures cxhibits an inversion channel, for example the channel 14, without the supply of a further control voltage and, therefore, exhibits an activated emitter short circuit, whereas the other structure does not have such a response.
Let it be assumed for the following considerations that the inversion channel 14 exists beneath the gate 13, whereas no inversion channel exists bet-~een the gate 16. Thereby, the channel 14 causes the thermally-generated hole electrons to be diverted from the base layer 2 to the cathode 6, so that no charge carriers are injected into the base layer 2 from the n-emitter layer 1.
This means that the thyristor is conditioned into its blocked state in which, despite a voltage poled in the forward-conducting direction adjacent to the ter-~S~6~
minals A and K, practically no current flows between the terminals A and K.
If one supplies a positive voltage pulse Pl to the terminal Gl, then the only existing emitter short circuit is shut off for the duration of the pulse Pl, whereby the triggering of the thyristor occurs. Subsequently, a load cur-rent of a load circuit connected to the terminals A and K flows across the thyristor switch in a low-resistance manner. In order to block the thyristor, a negative voltage pulse P2 is supplied to the terminal G2, without the voltage poled in the forward-conducting direction adjacent to the terminals A and K re-quiring switching off. During the application of a pulse P2, both emitter short circuits are activated, so that the hole electrons flooding the base regions 2 and 3 are diverted to the cathode by way of these short circuits. By so doing, the injection of the charge carriers from the n-emitter layer 9 into the base layer 2 is suppressed, so that the thyristor again arrives in the blocked state.
In the embodiments of the MIS structures described above, which re-quire the employment of a bias voltage, there derives the same manner of opera-tion when one respectively sees to it that the pulses Pl or P2 supplied to the terminals Gl and G2 exhibit a polarity opposite to that of the appertaining bias voltage.
Instead of the n-emitter layer 1, a p-emitter layer ~ can also be op-tionally bridged in a low resistance manner by means of two MIS structures of differing type which form controllable short circuits between the base layer 3 and the anode 5. Figure 1 can be employed for explaining this embodiment if one interprets the electrode 5 as a cathode and the electrode 6 as an anode, replaces the conductivity of all semiconductor portions by the opposite conductivities, reverses the polarities of the voltages or, respectively, voltage pulses, and interchanges the reference characters A and K. The described operating behavior of the thyristor is not thereby changed.
~S~
The thyristor illustrated in Figure 3 differs from that of Figure 1 and that the n-emitter layer is subdivided into a plurality of emitter zones lb--le which are respectively provided with portions Kb--Ke of the cathode con-ductively connected amongst one another which lie at a common cathode terminal K, n~O respective MIS structures Sbl, Sb2, Scl, Sc2, Sdl, Sd2, and Sel, Se2 of the type already described are provided edge-wise with respect to the emitter zones lb--le. The gate at the structure Sbl is referenced 17, whereas the gate of the structures Sbl and Scl are connected to a common gate 18, the gates of Sc2 and Scl are connected to a common gate 19, and the gates Sd2 and Sel are connected to a common gate 20. The MIS structure Se2 exhibits a gate 21.
The manner of operation of the thyristor according to Figure 3 cor-responds to that of the thyristor according to Figure 1, whereby short circuit channels exists in the MIS structures Sbl, Sc2, Sdl and Se2 connected to the terminal Gl upon a lack of a pulse Pl, whereas no short circuit channels exists in the MIS structures Sb2, Scl, Sd2 and Sel connected to the terminal G2 without a pulse P2. ~hen a pulse Pl is applied, due to a brief neutralization of ~he ex-isting short circuits, the thyristor goes from the block state into the current-conducting state in which it remains until it is again blocked by an applied pulse P2, which also allows short circuits to arise in the latter MIS structures which add up in their effect to the short circuits in the former MIS structures.
In order to achieve a good stability of the thyristor according to Figure 3, i.e. in order to achieve a great insensitivity to voltages poled in the forward-conducting direction which are adjacent to the block state between the anode and the cathode, which, of course, should not cause undesired trigger-ing operations, it is advantageous that those MIS structures which exhibit short circuit channels without adjacent -pulses Pl and P2 cover approximately between 0.01%--3.0% of the lateral thyristor surface covered by the n-emitter zones ..
~ ~ ~ S ~36 ~
lb--le. The paths a9 b, and c are indicated in Figure 3, the sum of which re-presents a measure for the lateral thyristor surface covered by these MIS struc-tures. The path 1 represents a measure for the total lateral thyristor surface covered by the emitter zones lb--le. According to the above, there derives a good stability when the condition 3 : 100 ( a + b + c) : 1 1 : 10 000 is met. Thereby, the values of approximately 2--3 ~m comes into consideration for the length of an individual short circuit channel, particularly given a short circuit coverage of the lateral thyristor surface covered by the emitter zones which lie between 2% and 3%.
On the other hand, for the secure transfer of the thyristor from the current-conductive state into the blocked state, it is advantageous that the emitter short circuits active during the occurrence of the pulse P2 occupy ap-proximately between 3% and 10% of the overall lateral thyristor surface covered by the emitter zones lb--le. This is the case when the ratio 1 : 10 (a + b + c + d + e) : 1 3 : 100 applies to the paths a--c and 1 indicated in Figure 3. Thereby, the paths d and e correspond to the surface of those MIS structures which are provided with short circuit paths only upon the occurrence of the pulse P2. For reasons o-f clarity, the schematic illustration of Figure 3 leaves the actual size relation-ships out of consideration.
The thyristor described immediately above can also be varied in such a manner that the controllable emitter short circuits optionally bridge the p-emitter layer 4 in a low resistance manner. Figure 3 serves ~o illustrate that this radiation, if one interprets lb--le as p-emitter zones, the portions Kb--Ke as portions of the anode and the electrode S as the cathode, replaces the con-ductivity types of all semiconductor portions by those which are respectively opposite and respectively reverses the voltages or, respectively, voltage pulses.
Figure 3 illustrates a further development of the invention which provides that a traditional trigger electrode 22 is arranged on a portion of the base layer 2 lying in the boundary surface la. This is connected to a traditional trigger circuit Zl via a terminal Z. A very rapid course of the trigger operation is achieved by means of the trigger current flowing over the electrode 22.
According to another further development of the invention, the ter-minals Gl and G2 are connected to a common terminal G to which a pulse voltage with the pulses Pl' and P2' is supplied. By so doing, the described manner of operation of the thyristor is not changed.
Figure 4 illustrates a further exemplary embodiment of ~he invention which partially corresponds to that of Figure 3. In contrast to Figure 3, the p-emitter layer is also subdivided into emitter zones 4a--4e which are respec-tively provided with portions 5a--5e of the anode which are connected amongst one another. These are connected to the common anode terminal A. MIS structures Sa2', Sbl', Sb2', Scl', Sc2', Sdl', Sd2', Sel', and Se2' are provided edge-wise with respect to the emitter zones 4a--4e, the MIS structure being driven by way of a terminal G2' and a pulse P2 " which chronologically coincides with the pulse P2 but exhibits the opposite polarity. These MIS structures exhibit emitter short circuits which are respectively activated only during the transfer from the current-conductive state into the block state. If, in accordance with the coverage rules presented on a basis of Figure 3, approximately 3%--10% of the overall lateral thyristor surface covered by the p-emitter zones are covered with these emitter short circuits, then a very rapid and secure transfer opera-tion is achieved.
In Figure 4, the MIS structures arranged on the boundary surface la whose emitter short circuits are activated only during the transfer from the ~513~
current-conducting into the block state can also be emitted.
Figure 4 illustrates yet another embodiment of the invention. Accord-ing to Figure 4, another further n-emitter zone lc which is contacted by a further portion P' of the cathode is provided adjacent the n-emitter zones already described with respect to Figure 3. It has included therein zones 23--25 of the base layer 2 which extend up to the boundary surface la and which are likewise contacted by a terminal K'. The zones 23--25 form fixed n-emitter short circuits which prevent a decrease of the stability given the thyristor according to Figure 4 which, because of the emitter zone lz, governs greater load currents than the thyristor according to Figure 3.
As indicated in Figure 2, the emitter zones lb--lz can extend in a straight line over the entire thyristor surface, whereby a trigger electrode 22 which may be present is likewise advantageously constructed as a strip. The same applies to the emitter zones 4a--4e in Figure 4. On the other hand, the emitter zones can also be designed as concentric rings, whereby a trigger elec-trode 22 is advantageously arranged in the center of the emitter zones. Further emitter zones lz are likewise arranged as rings.
Although I have described my invention by reference to particular illustrative embodiments thereof, many changes and modifications of the invention ~0 may become apparent to those skilled in the art without departing from the spirit and scope thereof. I therefore intend to include within the patent war-ranted hereon all such changes and modifications as may reasonably and properly be included within the scope of my contribution to the art.
Field of the Invention The invention relates to a thyristor and to a method of operating the same, in which the thyristor has a semiconductor body which contains an outside n-emitter layer provided with a cathode, an external p-emitter layer provided ~ith an anode and two base layers respectively adjacent to the cathode and anode layers, and more particularly to such a thyristor in which controllable emitter circuits are designed as MIS structures and are arranged at at least one boundary surface of the semiconductor body, the emitter short circuits respec-tively exhibiting a first semiconductor region of a first conductivity type connected to the cathode ~anode), a second semiconductor region of the first conductivity type connected to a base layer, and an intermediate layer of the second conductivity type positioned between these regions, the intermediate layer being covered by a gate which is electrically insulated with respect to the semi-conductor body.
Description of the Prior Art Thyristors of the type generally mentioned above are known in the art from United States 3,243,669. Upon application of a control voltage to the gate of a MIS structure, a short circuit path is activated which bridges the pn junc-tion between the emitter layer connected to the cathode (anode) and the adjacent base layer. This results in a transfer of the thyristor from the current-con-ducting state into the blocked state in which practically no current flows bet-~een the cathode and the anode despite the voltage adjacent in the forward con-ducting direction. The change from the blocked state into the current-conduct-ing state occurs by applying a further control voltage to the gate of a further MIS structure which bridges the pn junction between the two base layers in a low-resistance manner. At the same time, the control voltage switching the -- 1 -- i ~gL5~6~
short circuit path on is switched off for the duration of the current-conducting state.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a thyristor of the type generally mentioned above which can be triggered, and again blocked, in a controlled manner by simple control operations.
The above object is achieved, in apparatus o-f the type described above, in that at least one MIS structure of the depletion type and at least one MIS
structure of the enhancement type are provided and in that a common control voltage terminal is provided for the gates of the MIS structures of the one type <~ld a common control voltage terminal are provided for the gates of the MIS
structures of the other type.
The advantage attainable in practicing the present invention particu-larly lies in that, after supply of first control pulse to the gate of at least one MIS structure of the enhancement type ~depletion type), the thyristor locat-ed in the current-conducting state is blocked until it agai-n triggers upon occurrence of a second control pulse which is supplied to the gate of at least one MIS structure of the depletion type (enhancement type). It is not necessary for retaining the blocked or current-conducting state to supply a control voltage ~O to the MIS structures, as is the case in known thyristors with MIS short circuit paths. Thereby, the MIS structures of the one type which are only temporarily shut off during the triggering operation determine the stability of a thyristor constructed iTI accordance with the invention, i.e. its reliability against un-intentional triggering operations upon occurrence of voltages poled in the for-ward-conducting direction at the anode-cathode path. Finally, a control of the pn junction between the two base layers which is undertaken in the known thyris-tors of the type initially mentioned is also eliminated.
~5~
Thus, in accordance with one broad aspect of the invention, there is provided, in a thyristor structure of the type in which a semiconductor body in-cludes first and second base layers adjacent and contacting one another, an n-emitter layer contacting the first base layer, a first electrode contacting the n-emitter layer, a p-emitter layer contacting the second base layer, a second electrode contacting the p-emitter layer, and controllable metal-insulator-semi-conductor emitter short circuit structures located at at least one boundary surface of the semiconductor body, each of the short circuit structures includ-ing a first semiconductor region of a first conductivity type contacting the ~irst electrode, a second semiconductor region of the first conductivity type contacting the adjacent base layer, an intermediate third semiconductor region of a second, opposite conductivity type between said first and second regions adjacent the boundary surface, and an insulated gate carried over the interme-diate third region, the improvement wherein: ~he metal-insulator-semiconductor structures comprise at least one depletion type structure and at least one enhancement type structure; a first common terminal is connected to the gate of each depletion type structure; and a second common terminal is connected to the gate of each enhancement type structure.
In accordance with another broad aspect of the invention there is provided a method of operating a thyristor structure of the type in which a semiconductor body includes first and second base layers adjacent and contact-ing one another, an n-emitter layer contacting the first base layer, a first electrode contacting the n-emitter layer, a p-emitter layer contacting the second base layer, a second electrode contacting the p-emitter layer~ and con-trollable metal-insulator semiconductor emitter short circuit structures located at at least one boundary surface of the semiconductor body, each of the short circuit structures including a first semiconductor region of a first _ 2a -, ~
1~5~6~
conductivity type contacting the first electrode, a second semiconductor region of the first conductivity type contacting the adjacent base layer, an intermediate third semiconductor region of a second, opposite conductivity type between said first and second regions adjacent the boundary surface, and an insulated gate carried over the intermediate third region, and in which the metal-insulator-semiconductor structures comprise at least one depletion type structure and at least one enhancement type structure, a first common terminal is connected to the gate of each depletion type structure, and a second common terminal is connected to the gate of each enhancement type structure, comprising the steps of: applying a first voltage pulse of a first polarity to the first common terminal; and applying a second voltage pulse of a second polarity to the second common terminal.
- 2b -~ " i ~S~6~
BRIEF DESCRIPTION OF THE DRAWINGS
Other objects, features and advantages of the invention, its organiza-tion, construction and operation will be best understood from the following detailed description, taken in conjunction with the accompanying drawings, on which:
Figure 1 is a cross sectional view of a first exemplary embodiment of the invention;
Figure 2 is a plan view of the embodiment of Figure l;
Figure 3 is a cross sectional view of a second exemplary embodiment of the invention; and Figure 4 is a cross sectional view of a third exemplary embodiment of the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring to Figures 1 and 2, a semiconductor body comprises semicon-ductor layers 1--4 of alternating conductivity type and includes, for example, doped silicon. The outer n-conductive layer 1 is designated as the n-emitter layer and the outer p-conduc~ive layer 4 is designated as the p-emitter layer.
The p-conductive layer 2 and the n-conductive layer 3 represent the base layers.
The p-emitter layer 4 is provided with an anode 5 which has an anode terminal A, wllereas the n-emitter layer 1 is contacted by the cathode 6 which is provided with a cathode terminal K. The n-emitter layer 1 is advantageously designed as a strip and can be seen in the plan view of Figure 2 as a vertically-extending ~trip.
In Figure 1, which illustrates a cross-sectional view taken along the line I--I of Figure 2~ p-conductive semiconductor regions 7 and 8 are illustrat-ed which are provided in the n-emitter layer 1 in such a manner that they extend up to the boundary surface la of the semiconductor body. In Figure 2, the sur-~5~36~
faces of the semiconductor regions are illustrated with hatching for the purpose of greater clarity. The regions 7 and 8 are respectively contacted, edge-wise, by the cathode 6. Individual zones 9, 10 and 11 of the base layer 2 extend up to the boundary surface la. The regions 7 and 8 are separated from one another by the zone 9.
The region 7 forms a first p-region; the zone 10 forms a second p-region; and the portion of the emitter layer 1 lying inbetween forms an n-inter-mediate layer. A thin, electrically-insulating layer 12 comprising, for example, SiO2 is provided on the boundary surface la, a gate 13 being arranged on the electrically insulating layer 12 in such a manner that it covers the n-inter-mediate layer. The portions 7, 9, 10, 12 and 13 form a MIS s~ructure. If it belongs to the depletion type, then, without influence of a voltage at the gate 13, a p-conductive inversion channel 14 is located at the boundary surface la between the regions 7 and 10, the p-conductive inversion channel 14 conductively connecting the regions with one another. If one applies a positive control vol-tage to a control voltage terminal Gl of the gate 13, the inversion channel 14 is eliminated. If the MIS structure is of the depletion type, then there is no inversion channel 14 given a voltage-free gate 13. This is only constructed upon application of a negative control voltage to the terminal Gl by means of in-version of the emitter layer 1. The inversion channel 14, therefore, represents a controllable emitter short circuit which either connects or does not connect the base layer 2 to the region 7 and, therefore, to the cathode 6 as a function of a control voltage supplied to the ~erminal Gl, the connection being a low-resiStance connection.
A corresponding MIS structure 8, 9, 11, 15 and 16 is produced at the right edge of the n-emitter layer 1 by means of the arrangement of an electri-cally-insulating layer 15 comprising, for example, SiO2, on which a gate 16 con-6(~
nected to a terminal G2 is provided, the MIS structure 8, 9, 11, 15 and 16 representing an emitter short circuit controllable by way of the terminal G2.
It is an essential feature of the invention that the one of the two MIS structures, for example the structure 7, 9, 10, 12 and 13, belongs to the depletion type and the other MIS structure, i.e. the structure 8, 9, 11, 12 and 16 in the exemplary embodiment, belongs to the enhancement type. A feature equivalent to this, however, can be seen in that both structures are of the depletion type and a positive bias voltage is supplied to one of the structures, for example to the structure 8, 9, 11, 15 and 16 via the terminal G2 assigned l~ thereto. Thereby, the bias voltage first prevents a channel formation. A short circuit channel only becomes effective when a further control voltage which ex-hibits a polarity opposite to that of the bias voltage is supplied to the termi-nal. On the other hand, both MIS structures can be of the enhancement type, whereby a negative bias voltage is then supplied to one of the structures which effects the formation of an inversion channel. What is essential to all of these variations is that, under certain conditions upon incorporation of a bias voltage supplied to the terminal Gl or the terminal G2, one of the two MIS structures cxhibits an inversion channel, for example the channel 14, without the supply of a further control voltage and, therefore, exhibits an activated emitter short circuit, whereas the other structure does not have such a response.
Let it be assumed for the following considerations that the inversion channel 14 exists beneath the gate 13, whereas no inversion channel exists bet-~een the gate 16. Thereby, the channel 14 causes the thermally-generated hole electrons to be diverted from the base layer 2 to the cathode 6, so that no charge carriers are injected into the base layer 2 from the n-emitter layer 1.
This means that the thyristor is conditioned into its blocked state in which, despite a voltage poled in the forward-conducting direction adjacent to the ter-~S~6~
minals A and K, practically no current flows between the terminals A and K.
If one supplies a positive voltage pulse Pl to the terminal Gl, then the only existing emitter short circuit is shut off for the duration of the pulse Pl, whereby the triggering of the thyristor occurs. Subsequently, a load cur-rent of a load circuit connected to the terminals A and K flows across the thyristor switch in a low-resistance manner. In order to block the thyristor, a negative voltage pulse P2 is supplied to the terminal G2, without the voltage poled in the forward-conducting direction adjacent to the terminals A and K re-quiring switching off. During the application of a pulse P2, both emitter short circuits are activated, so that the hole electrons flooding the base regions 2 and 3 are diverted to the cathode by way of these short circuits. By so doing, the injection of the charge carriers from the n-emitter layer 9 into the base layer 2 is suppressed, so that the thyristor again arrives in the blocked state.
In the embodiments of the MIS structures described above, which re-quire the employment of a bias voltage, there derives the same manner of opera-tion when one respectively sees to it that the pulses Pl or P2 supplied to the terminals Gl and G2 exhibit a polarity opposite to that of the appertaining bias voltage.
Instead of the n-emitter layer 1, a p-emitter layer ~ can also be op-tionally bridged in a low resistance manner by means of two MIS structures of differing type which form controllable short circuits between the base layer 3 and the anode 5. Figure 1 can be employed for explaining this embodiment if one interprets the electrode 5 as a cathode and the electrode 6 as an anode, replaces the conductivity of all semiconductor portions by the opposite conductivities, reverses the polarities of the voltages or, respectively, voltage pulses, and interchanges the reference characters A and K. The described operating behavior of the thyristor is not thereby changed.
~S~
The thyristor illustrated in Figure 3 differs from that of Figure 1 and that the n-emitter layer is subdivided into a plurality of emitter zones lb--le which are respectively provided with portions Kb--Ke of the cathode con-ductively connected amongst one another which lie at a common cathode terminal K, n~O respective MIS structures Sbl, Sb2, Scl, Sc2, Sdl, Sd2, and Sel, Se2 of the type already described are provided edge-wise with respect to the emitter zones lb--le. The gate at the structure Sbl is referenced 17, whereas the gate of the structures Sbl and Scl are connected to a common gate 18, the gates of Sc2 and Scl are connected to a common gate 19, and the gates Sd2 and Sel are connected to a common gate 20. The MIS structure Se2 exhibits a gate 21.
The manner of operation of the thyristor according to Figure 3 cor-responds to that of the thyristor according to Figure 1, whereby short circuit channels exists in the MIS structures Sbl, Sc2, Sdl and Se2 connected to the terminal Gl upon a lack of a pulse Pl, whereas no short circuit channels exists in the MIS structures Sb2, Scl, Sd2 and Sel connected to the terminal G2 without a pulse P2. ~hen a pulse Pl is applied, due to a brief neutralization of ~he ex-isting short circuits, the thyristor goes from the block state into the current-conducting state in which it remains until it is again blocked by an applied pulse P2, which also allows short circuits to arise in the latter MIS structures which add up in their effect to the short circuits in the former MIS structures.
In order to achieve a good stability of the thyristor according to Figure 3, i.e. in order to achieve a great insensitivity to voltages poled in the forward-conducting direction which are adjacent to the block state between the anode and the cathode, which, of course, should not cause undesired trigger-ing operations, it is advantageous that those MIS structures which exhibit short circuit channels without adjacent -pulses Pl and P2 cover approximately between 0.01%--3.0% of the lateral thyristor surface covered by the n-emitter zones ..
~ ~ ~ S ~36 ~
lb--le. The paths a9 b, and c are indicated in Figure 3, the sum of which re-presents a measure for the lateral thyristor surface covered by these MIS struc-tures. The path 1 represents a measure for the total lateral thyristor surface covered by the emitter zones lb--le. According to the above, there derives a good stability when the condition 3 : 100 ( a + b + c) : 1 1 : 10 000 is met. Thereby, the values of approximately 2--3 ~m comes into consideration for the length of an individual short circuit channel, particularly given a short circuit coverage of the lateral thyristor surface covered by the emitter zones which lie between 2% and 3%.
On the other hand, for the secure transfer of the thyristor from the current-conductive state into the blocked state, it is advantageous that the emitter short circuits active during the occurrence of the pulse P2 occupy ap-proximately between 3% and 10% of the overall lateral thyristor surface covered by the emitter zones lb--le. This is the case when the ratio 1 : 10 (a + b + c + d + e) : 1 3 : 100 applies to the paths a--c and 1 indicated in Figure 3. Thereby, the paths d and e correspond to the surface of those MIS structures which are provided with short circuit paths only upon the occurrence of the pulse P2. For reasons o-f clarity, the schematic illustration of Figure 3 leaves the actual size relation-ships out of consideration.
The thyristor described immediately above can also be varied in such a manner that the controllable emitter short circuits optionally bridge the p-emitter layer 4 in a low resistance manner. Figure 3 serves ~o illustrate that this radiation, if one interprets lb--le as p-emitter zones, the portions Kb--Ke as portions of the anode and the electrode S as the cathode, replaces the con-ductivity types of all semiconductor portions by those which are respectively opposite and respectively reverses the voltages or, respectively, voltage pulses.
Figure 3 illustrates a further development of the invention which provides that a traditional trigger electrode 22 is arranged on a portion of the base layer 2 lying in the boundary surface la. This is connected to a traditional trigger circuit Zl via a terminal Z. A very rapid course of the trigger operation is achieved by means of the trigger current flowing over the electrode 22.
According to another further development of the invention, the ter-minals Gl and G2 are connected to a common terminal G to which a pulse voltage with the pulses Pl' and P2' is supplied. By so doing, the described manner of operation of the thyristor is not changed.
Figure 4 illustrates a further exemplary embodiment of ~he invention which partially corresponds to that of Figure 3. In contrast to Figure 3, the p-emitter layer is also subdivided into emitter zones 4a--4e which are respec-tively provided with portions 5a--5e of the anode which are connected amongst one another. These are connected to the common anode terminal A. MIS structures Sa2', Sbl', Sb2', Scl', Sc2', Sdl', Sd2', Sel', and Se2' are provided edge-wise with respect to the emitter zones 4a--4e, the MIS structure being driven by way of a terminal G2' and a pulse P2 " which chronologically coincides with the pulse P2 but exhibits the opposite polarity. These MIS structures exhibit emitter short circuits which are respectively activated only during the transfer from the current-conductive state into the block state. If, in accordance with the coverage rules presented on a basis of Figure 3, approximately 3%--10% of the overall lateral thyristor surface covered by the p-emitter zones are covered with these emitter short circuits, then a very rapid and secure transfer opera-tion is achieved.
In Figure 4, the MIS structures arranged on the boundary surface la whose emitter short circuits are activated only during the transfer from the ~513~
current-conducting into the block state can also be emitted.
Figure 4 illustrates yet another embodiment of the invention. Accord-ing to Figure 4, another further n-emitter zone lc which is contacted by a further portion P' of the cathode is provided adjacent the n-emitter zones already described with respect to Figure 3. It has included therein zones 23--25 of the base layer 2 which extend up to the boundary surface la and which are likewise contacted by a terminal K'. The zones 23--25 form fixed n-emitter short circuits which prevent a decrease of the stability given the thyristor according to Figure 4 which, because of the emitter zone lz, governs greater load currents than the thyristor according to Figure 3.
As indicated in Figure 2, the emitter zones lb--lz can extend in a straight line over the entire thyristor surface, whereby a trigger electrode 22 which may be present is likewise advantageously constructed as a strip. The same applies to the emitter zones 4a--4e in Figure 4. On the other hand, the emitter zones can also be designed as concentric rings, whereby a trigger elec-trode 22 is advantageously arranged in the center of the emitter zones. Further emitter zones lz are likewise arranged as rings.
Although I have described my invention by reference to particular illustrative embodiments thereof, many changes and modifications of the invention ~0 may become apparent to those skilled in the art without departing from the spirit and scope thereof. I therefore intend to include within the patent war-ranted hereon all such changes and modifications as may reasonably and properly be included within the scope of my contribution to the art.
Claims (13)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. In a thyristor structure of the type in which a semiconductor body in-cludes first and second base layers adjacent and contacting one another, an n-emitter layer contacting the first base layer, a first electrode contacting the n-emitter layer, a p-emitter layer contacting the second base layer, a second electrode contacting the p-emitter layer, and controllable metal-insulator-semi-conductor emitter short circuit structures located at at least one boundary surface of the semiconductor body, each of the short circuit structures includ-ing a first semiconductor region of a first conductivity type contacting the first electrode, a second semiconductor region of the first conductivity type contacting the adjacent base layer, an intermediate third semiconductor region of a second, opposite conductivity type between said first and second regions adjacent the boundary surface, and an insulated gate carried over the interme-diate third region, the improvement wherein: the metal-insulator-semiconductor structures comprise at least one depletion type structure and at least one enhancement type structure; a first common terminal is connected to the gate of each depletion type structure; and a second common terminal is connected to the gate of each enhancement type structure.
2. The improved thyristor structure of claim 1, wherein: at least two of the metal-insulator-semiconductor structures of one of the types are included;
the insulated gate of one of the two metal-insulator-semiconductor structures is adapted for connection to a bias voltage which will cause the existence or non-existence of an inversion layer in the appertaining intermediate third region.
the insulated gate of one of the two metal-insulator-semiconductor structures is adapted for connection to a bias voltage which will cause the existence or non-existence of an inversion layer in the appertaining intermediate third region.
3. The improved thyristor structure of claim 1, wherein: a third common terminal connects said first and second common terminals.
4. The improved thyristor structure of claim 1, wherein: at least one of the emitter layers is divided into spaced apart strips to provide emitter zones having edges, the emitter zones being respectively provided with portions of the first or second electrode; and the metal-insulator-semiconductor struc-tures are strip-shaped and located at said edges of said emitter zones.
5. The improved thyristor structure of claim 1, wherein: the metal-in-sulator-semiconductor structures of both types are located at the same boundary surface of the semiconductor body.
6. The improved thyristor structure of claim 1, wherein: each type of metal-insulator-semiconductor structure is located at a respective boundary surface of the semiconductor body.
7. The improved thyristor structure of claim 1, wherein: metal-in-sulator-semiconductor structures of both types are located on one boundary sur-face of the semiconductor body; and metal-insulator-semiconductor structures of one of the types are located at the other boundary surface of the semiconductor body.
8. The improved thyristor of claim 1, wherein: each of the first regions are located in the respective emitter layer and extend up to the boundary sur-face of the semiconductor body; each of the second regions is a portion of the base layer contacting the respective emitter layer and extend up to the boundary surface of the semiconductor body; and each of the third regions is a portion of the respective emitter layer.
9. The improved thyristor of claim 1, wherein: a further emitter layer is located at a boundary surface of the semiconductor body and contacting to a further portion of the respective electrode; and further zones of the respec-tive base layer extend through the further emitter layer and contact the further portion of the respective electrode.
10. The improved thyristor of claim 1, wherein: a trigger electrode is carried on a zone of one of the base layers.
11. The improved thyristor of claim 10, wherein: a trigger terminal is connected to said trigger electrode and to the common terminal connected to depletion type structures.
12. A method of operating a thyristor structure of the type in which a semiconductor body includes first and second base layers adjacent and contact-ing one another, an n-emitter layer contacting the first base layer, a first electrode contacting the n-emitter layer, a p-emitter layer contacting the second base layer, a second electrode contacting the p-emitter layer, and con-trollable metal-insulator-semiconductor emitter short circuit structures located at at least one boundary surface of the semiconductor body, each of the short cir-cuit structures including a first semiconductor region of a first conductivity type contacting the first electrode, a second semiconductor region of the first conductivity type contacting the adjacent base layer, an intermediate third semi-conductor region of a second, opposite conductivity type between said first and second regions adjacent the boundary surface, and an insulated gate carried over the intermediate third region, and in which the metal-insulator-semiconductor structures comprise at least one depletion type structure and at least one en-hancement type structure, a first common terminal is connected to the gate of each depletion type structure, and a second common terminal is connected to the gate of each enhancement type structure, comprising the steps of: applying a first voltage pulse of a first polarity to the first common terminal; and apply-ing a second voltage pulse of a second polarity to the second common terminal.
13. The method of claim 12, wherein the first and second common terminals are connected together at a third common terminal, wherein the steps of apply-ing voltage pulses are further defined as: applying a voltage of alternate opposite polarity pulses to the third common terminal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DEP2945324.5 | 1979-11-09 | ||
| DE19792945324 DE2945324A1 (en) | 1979-11-09 | 1979-11-09 | THYRISTOR WITH IMPROVED SWITCHING BEHAVIOR |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1145060A true CA1145060A (en) | 1983-04-19 |
Family
ID=6085606
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000364265A Expired CA1145060A (en) | 1979-11-09 | 1980-11-07 | Thyristor having improved switching behavior |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP0028797B1 (en) |
| JP (1) | JPS609669B2 (en) |
| BR (1) | BR8007248A (en) |
| CA (1) | CA1145060A (en) |
| DE (1) | DE2945324A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5014102A (en) * | 1982-04-01 | 1991-05-07 | General Electric Company | MOSFET-gated bipolar transistors and thyristors with both turn-on and turn-off capability having single-polarity gate input signal |
Families Citing this family (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3018468A1 (en) * | 1980-05-14 | 1981-11-19 | Siemens AG, 1000 Berlin und 8000 München | THYRISTOR WITH CONTROLLABLE EMITTER SHORT CIRCUITS AND METHOD FOR ITS OPERATION |
| DE3118293A1 (en) * | 1981-05-08 | 1982-12-02 | Siemens AG, 1000 Berlin und 8000 München | THYRISTOR WITH IMPROVED SWITCHING BEHAVIOR AND METHOD FOR ITS OPERATION |
| DE3118347A1 (en) * | 1981-05-08 | 1982-11-25 | Siemens AG, 1000 Berlin und 8000 München | Thyristor having gate-controlled MISFET structures of the depletion type and method of operating it |
| DE3118365A1 (en) * | 1981-05-08 | 1982-11-25 | Siemens AG, 1000 Berlin und 8000 München | THYRISTOR WITH CONTROLLABLE EMITTER SHORT CIRCUIT INSERTED INTO THE EMITTER |
| DE3118305A1 (en) * | 1981-05-08 | 1982-12-02 | Siemens AG, 1000 Berlin und 8000 München | THYRISTOR WITH IMPROVED SWITCHING BEHAVIOR AND METHOD FOR ITS OPERATION |
| DE3138762A1 (en) * | 1981-09-29 | 1983-04-14 | Siemens AG, 1000 Berlin und 8000 München | THYRISTOR WITH CONTROLLABLE EMITTER SHORT CIRCUITS AND IGNITION AMPLIFIER |
| IE56341B1 (en) * | 1981-12-16 | 1991-07-03 | Gen Electric | Multicellular thyristor |
| CA1201214A (en) * | 1982-02-03 | 1986-02-25 | General Electric Company | Semiconductor device having turn-on and turn-off capabilities |
| DE3230760A1 (en) * | 1982-08-18 | 1984-02-23 | Siemens AG, 1000 Berlin und 8000 München | SWITCHABLE THYRISTOR |
| JPS5961962A (en) * | 1982-09-30 | 1984-04-09 | Matsushita Electric Works Ltd | Insulated gate type thyristor |
| DE3370248D1 (en) * | 1982-10-04 | 1987-04-16 | Gen Electric | Thyristor with turn-off capability |
| EP0106147A1 (en) * | 1982-10-04 | 1984-04-25 | General Electric Company | Thyristor with turn-off capability |
| DE3379302D1 (en) * | 1982-12-13 | 1989-04-06 | Gen Electric | Lateral insulated-gate rectifier structures |
| DE3447220A1 (en) * | 1983-12-30 | 1985-07-11 | General Electric Co., Schenectady, N.Y. | Thyristor with turn-off capability having an improved emitter region, and processes for the fabrication thereof |
| JPS6188563A (en) * | 1984-10-08 | 1986-05-06 | Toshiba Corp | Semiconductor switch |
| JPS624368A (en) * | 1985-06-28 | 1987-01-10 | シ−メンス、アクチエンゲゼルシヤフト | Thyristor |
| US4760432A (en) * | 1985-11-04 | 1988-07-26 | Siemens Aktiengesellschaft | Thyristor having controllable emitter-base shorts |
| US4717940A (en) * | 1986-03-11 | 1988-01-05 | Kabushiki Kaisha Toshiba | MIS controlled gate turn-off thyristor |
| CH670528A5 (en) * | 1986-03-20 | 1989-06-15 | Bbc Brown Boveri & Cie | |
| GB2190539A (en) * | 1986-05-16 | 1987-11-18 | Philips Electronic Associated | Semiconductor devices |
| US4821083A (en) * | 1986-09-30 | 1989-04-11 | Kabushiki Kaisha Toshiba | Thyristor drive system |
| US5132767A (en) * | 1986-09-30 | 1992-07-21 | Kabushiki Kaisha Toshiba | Double gate GTO thyristor |
| JPH0821713B2 (en) * | 1987-02-26 | 1996-03-04 | 株式会社東芝 | Conduction modulation type MOSFET |
| TW399774U (en) * | 1989-07-03 | 2000-07-21 | Gen Electric | FET, IGBT and MCT structures to enhance operating characteristics |
| JP2501236B2 (en) * | 1989-07-26 | 1996-05-29 | 日産自動車株式会社 | Thyristor with turn-off gate |
| DE59107127D1 (en) * | 1991-04-11 | 1996-02-01 | Asea Brown Boveri | Switchable, MOS-controlled power semiconductor component |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL293292A (en) * | 1962-06-11 | |||
| SE392783B (en) * | 1975-06-19 | 1977-04-18 | Asea Ab | SEMICONDUCTOR DEVICE INCLUDING A THYRIST AND A FIELD POWER TRANSISTOR PART |
-
1979
- 1979-11-09 DE DE19792945324 patent/DE2945324A1/en active Granted
-
1980
- 1980-11-04 EP EP19800106775 patent/EP0028797B1/en not_active Expired
- 1980-11-07 BR BR8007248A patent/BR8007248A/en unknown
- 1980-11-07 CA CA000364265A patent/CA1145060A/en not_active Expired
- 1980-11-10 JP JP15806380A patent/JPS609669B2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5014102A (en) * | 1982-04-01 | 1991-05-07 | General Electric Company | MOSFET-gated bipolar transistors and thyristors with both turn-on and turn-off capability having single-polarity gate input signal |
Also Published As
| Publication number | Publication date |
|---|---|
| BR8007248A (en) | 1981-05-19 |
| DE2945324C2 (en) | 1990-05-31 |
| EP0028797A3 (en) | 1981-06-03 |
| DE2945324A1 (en) | 1981-05-21 |
| JPS609669B2 (en) | 1985-03-12 |
| EP0028797B1 (en) | 1983-02-16 |
| EP0028797A2 (en) | 1981-05-20 |
| JPS5683067A (en) | 1981-07-07 |
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