CA1141032A - Electronic bingo system - Google Patents
Electronic bingo systemInfo
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- CA1141032A CA1141032A CA000387780A CA387780A CA1141032A CA 1141032 A CA1141032 A CA 1141032A CA 000387780 A CA000387780 A CA 000387780A CA 387780 A CA387780 A CA 387780A CA 1141032 A CA1141032 A CA 1141032A
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Abstract
ELECTRONIC BINGO SYSTEM
Abstract Of The Disclosure An electronic bingo system for generally enhancing the oper-ation and playing value of the gamer by providing such features as flashing the last number called, providing an exciting light display upon designation of a winner, etc. The game is comprised of a ball table including a matrix of numbered switches for closure upon interference by a numbered ball, a plurality of control switches, a general display for individually illuminating one or more numbers corresponding to each numbered switch of the matrix of switches, means at the table for causing a digital display to indicate the number of the numbered switch upon the at least temporary closure of one of the numbered switches, and means for illuminating the corres-ponding number in the general display upon at least temporary closure of a predetermined one of the control switches.
Abstract Of The Disclosure An electronic bingo system for generally enhancing the oper-ation and playing value of the gamer by providing such features as flashing the last number called, providing an exciting light display upon designation of a winner, etc. The game is comprised of a ball table including a matrix of numbered switches for closure upon interference by a numbered ball, a plurality of control switches, a general display for individually illuminating one or more numbers corresponding to each numbered switch of the matrix of switches, means at the table for causing a digital display to indicate the number of the numbered switch upon the at least temporary closure of one of the numbered switches, and means for illuminating the corres-ponding number in the general display upon at least temporary closure of a predetermined one of the control switches.
Description
This invention relates to an electronic circuit for providing and enhancing the operation of apparatus used in a game such as Bingo.
In a game such as Bingo, randcmly selected numbers are called out in sequen oe of their selection by a game operator, and players utilize cards on which are printed numbers correspanding to some of those which are called. Sin oe a smaller nu~ber of numbers than those randomly selected are printed on each of the cards, the players participate in a game of chan oe to establish which will first obtain a series of numbers in a pre-determined pattern, such as in a straight line, two lines forming the letter "T", etc.
Such games have become highly popular, and as such, are often carefull~ controlled under the law. Ihe randomness of selection of numbers, for instance, must be ensured, the possibility of any of the numbers being called must be equal to all others, and it is highly desirable, particularly in games which are open to the general public, to utilize a display which illuminates each number after it is called for the remainder of the game.
In one oommon form of the game, a transparent box or cage is provided within which are disposed a number of light balls such as ping pong balls, each of which carries one of the numbers to be called. A hole with a ball-catching channel forms an exit to the cage, and a oentrally lccated fan at the bottom of the cage blcws and scatters the balls. Since the only exit to the cage is the channel, one or more balls is blown into it, allcwing the operator to select each ball in sequence out of the ball~
catching channel, the numbers thereon therefore being rendered in totally randcm sequence.
The operator nGrmally calls the number via a public address system after selecting the outer ball in the ball-catching charmel, and he deposits the ball into a correspondingly numbered hole in a Bingo table.
The ball is lightly posted into the holel and is caught by a spring which holds it in its depressed position. On oe depressed, the ball operates an actuator pin of a microswitch or leaf switch. Current pass mg through the switch is directed to a lamp immediately behind a translucent pane ~03Z
~hich carries a number painted thereon which corresponds to the nu~ber of the ball which had been called and is held in the correspondingly num~ered hole.
In this manner each of the balls which had been called causes a corresponding number to be illum m ated in the displ~y for the remainder of the game, allowing the players to check all previously called numbers as the game progresses.
Once the game has been completed, the operator normally shifts the table, moving the balls past the microswitch locations, allowing them to fall into a bin or sink which has its exit into the lower box or cage.
The present invention is directed to an electronic circuit which interfa oes the switch positions actuated by each depressed ball, and among other functions, illuminates the proper lamps in the display.
It should ke noted that in the above-described Bingo system each switch corresponding to a ball position in the operator's ball table extends to a corre~ponding lamp via an individual wire; there is also a single grcund return for all lamps. Bingo or similar games normally utilize 75 or 90 numbers and consequently it is clear that the cable from the Bingo table to the display must be extremely thick, heavy and unyielding. Furthermore, because of the large number of wires, it is costly and difficult to extend the display over a large distance as might be required at two ends of a Bingo hall (scmetimes reguiring the length of cable of as much as several hundred feet, for example).
With such a large number of wires, there is also the danger of breakage of one or more of them as the cable is flexed. This decreases the reliability of the cable as the Bingo table is set up or taken down at the end of each day's games, and it also introduces the possibility of short circuiting due to breakage of the wires. Breakage of the wires also introduces a possibility of danger to personnel utilizing the system, since the breakage could occur at a position adjoining a-pparatus ~hich is tcuched by the operator or by the players. Clearly, flexing of the multi-wire cable repeatedly places substantial stress on each of the 3;Z
wires, and can result in reliability problems with the apparatus as well as a danger to the public due to the potential for shock.
Sln oe such systems are wired directly from switch to liaht bulb to pcwer supply, its manner of oFeration is fixed. m e depression of a ball into the appropriate hole in the Bingo table results simply in the illumunation of a corresponding light bulb.
m e present invention, an the other hand, provides a display which is variable at the push of an operator's button. The last number which has been called is shown on the display bcard as an ill~ninated number, but continuously flashes to inEorm the players which number was last called. Gn oe anather number has been called, the flashing stops and the new number is displayed by a flashing l~np.
The operator is also able to signify a "win" by the illumina-tion of various patterns of lights, for instance, all of the liyht bulbs may be caused to flash in sequence so as to portray a "starburst" moving pattern, which has been found to be an exciting display for players.
Further, a local display for the operator begins flashing after a pre-deterrnined (and variable) period to indicate to him when the next number should be called, and thus provides an even pace to the game.
Of further significance in this invention is the reduction of the cable to contain no more than four individual wires. me length of the cable can be extensive, and have been tested as being reliable over as much as 1,000 feet, cle æ ly sufficient for virtually all indoor locations. It should be noted that the aforenated length is not lirniting, but is merely the length to which the early prototype of this inventian was tested.
It is not intended that this invention be limited for use with Bingo. Other displays ~such as advertising or other illuminated indicator boards as are often found in sports arenas or sports fields can use the inventive systern. Ho~ever, the follcwing disclosure will be directed to an explanation of use in a Bingo game for each of description of the preferred, but not the only embodiment.
The advantages of the invention are obtained in a system for electronically randomly sel~cting a number and illuminating selected ones of a plurality of lamps located at a remote location com~rising an electronic random number generator, a control switch, a general display for individually illuminating one or more numbers corresponding to the generated random number, and means for causing illumination of said corresponding number upon generation of said random number and upon at least temporary operation of said control switch. Preferably, the random number generator is comprised of a microcomputer system, including data and program memories connected to a central processing unit, adapted to generate a random number signal and to store and process signals representative of the generated random number signal as well as signals representative of a signal processing sequence, and to derive and store signals representative of one or more of said lamps to be illuminated, as a result of translation of the processing sequence signals, the means for causing illwmination of said corresponding numbers comprised of converter means connected to the storing means for translating the random number slgnal into a serial bit stream signal representative of the address of one or more particular lamps to be illuminated, and a display bus connected to the output of the converter means for carrying the serial bit stream signal, ~or connection to a serlal bit stream signal decoding and lamp illumination circuit.
A better understanding of the invention will be obtained by reference to the description below, and to thP
following drawings, in which:
Figure 1 is a block schematic of the invention;
Figures 2 and 3 form a block schematic of the microcomputer portion of the invention;
Figures 4 and 5 form a schematic diagram of the input and output interface and controlling portion of the invention;
Figures 6 and 7 form a schematic diagram of the decoding and lamp driving portion of the invention, Figure 8 is a schematic diagram of the connections from Figurees 4 and 5 of the local digital display;
Figure 9 is a waveform diagram showing the signals at various locations in the input and output interface, controlling, decoding and -4a-lamp driving portions of the invention;
Figure 10 is a plan of the storage locations for various cross-point switch numbers, to be illuminated when aperated, in the memory of the input-oùtput peripheral;
Figure 11 is a plan of the contents of the microccmputer registers;
Figure 12 is a pLan of the cantents of the buffer store of the input-output peripheral;
Figure 13 is a plan of the lamp positions of the game pattern display board;
Figures 14 and 15 form a flcw chart of the logic behind the formation of the signals stored and operated by the microccmputer in respect of the main program;
Figures 16 and 17 form a flow chart of the logic behind the formation of the signals stored and aperated by the microoomputer in res-pect of the interrupt routine;
Figure 18 forms a flow chart of the logic behind the formation of the signals stored and operated by the microcomputer in respect of the interrupt subroutine;
Figures 19 and 20 form a flow chart of the logic behind the formation of the signals stored and aperated by the microco~puter in respect of the system subroutine;
Figures 21 and 22 form a flow chart of the logic behind the formation o~ the signals stored and operated by th~ microcomputer in respect of the display pattern subroutine, and Figure 23, which is on the same page as Figure 13 is a block schematic of a system for generatiny random num~ers.
Thrning now to Figure 1, a microcomputer system 1 for use in this invention is shown. The system is ccmprised of a central processing unit 2, ~7hich is preferably type 4040 single chip 4-bit P-channel micro-pro oe ssor which is available frcm Intel Corporation, Santa Clara, California.
Cannected to the central processing unit is a clock generator 3, which is preferably type 4210A, also available from Intel Corporation, - iL14~r~3 driven by a 5.185 megaher~z c~ystalO
Also connected to the central processing unit 2 is a P
(programable read only memory) driver and selector 4, preferably type 4289 also available fram Intel Corporation.
One or more PRQMs 5, such as type 4702A, available from Intel Corporation, is connected to the PRQM driver and selector 4. Associated with the PRCMs 5 and driver and selector 4 can be one or more binary decoders (not shown in Figure 1) for aiding in the selection of a particular PRCM at a required time.
Also connected to the central processing unit 2 is a data RAM (random access memory).
m e elements so far disclosed are connected together via address and data buses, as well as sync, clock, and other leads required f or proper operatiQn thereof. It is assumed that a person understanding this invention is able to assemble this microcomputer system, including determining the memory size required, and therefore the system has only been show~ in block diagram. However~ data sheets describing the inter-fa oe , operation, inter-relationship, and progra~m m g of the specific type of elements noted above are available from the aforenoted Intel Corporation. For the em~odiment described below, three 4702A PRCMs are sufficient.
An output b~s 7 of microccmputer system 1 contains four data leads Do~ Dl, D2, D3, a clock lead, a reset lead, a sync lead, and a cle æ memory lead, the latter useful for an ex*ernal memory.
Output bus 7 is connected to an input-outptlt peripheral integrated circuit 8. Preferably this peripheral is type 4269 which is available fr~n the aforenoted Intel Corporation~ This integrated circuit i~ ccmprised of a random ac oe ss m~mory, means for prcviding a scanning autput signal, means for sensing a scanned input signal, a bus interfa oe circuit, instruction decoding, control logic and timing cir-cuitry, and display registers, as well as interconnection circuits. As its m~de of operation is pt~lished, ~hich publication is availahle f~n Intel Corporation, a description of its internal op~ration will not be described.
Its scanning output ternunals, hcwever, are connected via bus 9 to a matrix of crosspomts 10. The output of the matrix of crosspoints 10 is connected to a scanned signal input to the input-output integrated circuit via bus 11, preferably through a crosspoint switch buffer 12.
me output of the internal random acoe ss memory from the display register of peripheral 8 is applied via bus 13 to a parallel-to-serial converter 14 ~hich changes the parallel form of the cutput to serial form on a data lead. m e output of the converter 14 is also applied to a clock lead for carrying clock pulses, to a reset lead for clearing the output display, and to a ccmmon lead.
m e four leads noted above are sufficient to carry all required information to the system display. Due to the small number of wires, the ~hle can be twisted and passed along and through locations with very littie stress in ccmparison to that which would be incurred by a 76 or 91 wire cable.
m e end of the cable 15 is connected to a buffer 16 which reconstitutes the square waveform of the pulses carried by cable 15, and raises their amplitude to a level sufficient to drive the following logic.
m e data, clock and reset leads at ~he output of buffer 16 are applied both to an address and board select decoder 17 and to a serial-to-parallel converter 18. I'he latter converter converts the data back into parallel form and is applied in parallel to a plurality of latches, ~hich in turn are cor~ected to a plurality of light drivers ~both in block 19).
The output of the address and bc~rd select decoder 17 is connected to an indicator latch select circuit 20, the output of which is connected to individual ones of the latches. Acoordingly a data signal is applied from the serial-to-parallel converter 18 to all latches 19 together, and the indicator latch select circuit 20, driven by the address and board select decoders 17 enables the specific latches at specific times to register and hold the data signal which is applied at that particular time fram the ~erial-to-parallel oonverter 18.
Individual lamps 21 connected to the light dri~ers, for instan oe through silicon oontrolled rectifiers or switches, are accordingly lit up at locations determined by the data signal and the address carried by cable 15, thus providing a display for the players of the game.
Preferabl~ the parallel-to-serial converter 14 is integrated circuit type 74151 available fro~ Fairchild Corporation. Serial-to-parallel converter 18 is preferably integrated circuit type 7496, address and board select decoder 17 and latch select 20 are preferably camprised of type 7442 in conjunction w~th type 7493 integrated circuits, and latches and light drivers 19 are preferably comprised of integrated circuit type 7475; all are avaiLable fram the aforenoted Fairchild Corporation.
Also cannected to microcamputer output bus 7 is a decoder and display driver 22, to the output of which is connected a two digit digital display 23 through drivers 24.
In operation, a crosspoint is closed somewhere within the matrix of crosspoints 10, by the operator depressing a numbered ball which has ~een randamly selected against a crosspoint switch which crosspoint is similarly numbered. Each of the raw ccnductors of the matrix of cross- I
points is scanned in sequence fram scanning output bus 9 of input-output integrated circuit 8, under control of the microcamputer system 1. With the closing of a crosspoint, the scanning pulse at the particular row conductor of the crosspoint is transferred to the adjacent column conductor and via switch buffer 12, is applied to one of the leads of input bus 11.
A signal on one of the leads of input bus 11 causes a system interrupt to ke generated, and under control of the microcamputer system, the input-cutput peripheral translates the matrix position to an indicator lamp address and data signal as to which addressed lamps are to be illumunated, shut off, flashed, etc., at particular times.
At the same time~ the translated address appears at the output bus 7 of the microcomputer system 1 due to the microccmputer system having performed the translation and providing the data signal back to integrated -~L~
circuit 8. The same data signal is applied to the decoder and display driver 22, which deocdes the data and causes the two digit digital dis~l~y 23 to provide an indication of the selected crosspoint matrix location, as a numerical output. m is numerical output is the same as will be illuminated by lamp 21, on oe actuated.
Closure of a further matrix crosspoint, one which has been predetermined for control, is then closed. As before, this causes genera-tion of a system interrupt which recognizes the particular crosspoint which has been closed. In this case, the microcGmputer system 1 causes an cutput signal to be generated on bus 13 which designates which lamp 21 is to be illuminated to display the num~er similar to that shown on digi-tal display 23.
Converter 14 changes the data on the parallel bus 13 to serial form, which is applied to cable 15, on the data, clock, and reset leads, with a ccmmon return. .
At the other end of cable 15, adjacent the display, is connected buffer 16 which remKves noise signals which may have been imposed on the signals carried by cable 15, and raises their potential level and shorten their rise ti~e ~o J~k~ reouired by ccnve~ter 18 ar~ ~ecoder 17.~ Ccnver~er 18 is connected to the output of buffer 16 and changes form of the signals to the parallel form requ~red by the latches of block 19. m e required data is applied to all latches in parallel.
m e output of buffer 16 is also connected to the input of address and bcard select decoder 17. miS circuit determunes first that it is the subject display which is to be addressed, and it further decodes the address of the specific lamps which are to be illumunated. m e output signal of deccder 17 is oonnected to the input of indicator latch select circuit 20, the output of which is connected to individual latches of block l9. Accordingly its decoded address enables a specific latch or grcup of latches to operate and store the data signal from oonverter 18 for the illumination or shutting off of a particular lamp 21 at a particular time. The output signal of the latches are applied to light _9_ drivers, which cause cperation of shutdown of l~nps 21.
In brief review, the aforenoted apparatus displays a selected number to the operator on two digit display 23 and at the same time illumin-ates the correct number on the display. If the ball was placed in the wrong hole, a further can oe llation crosspoint is closed, which turns off the latest display number; the operator then pla oe s the ball in the correct hole.
It is preferred that upon depression of each crosspoint indicating selection of a number to be displayed, the data and the address to which the data is applied should cause the light to turn on and off sequentially, i.e. to flash. On oe a following crossp~int has been closed, the data for the preceding lamp is changed causing steady illumination, and the data directed to the address of the lamp corresponding to the newly closed crosspoint causes the associated newly selected lamp to flash.
With the above general system configuration described, and the assumption that a person skilled in the art fabricating this invention understands the operation of the specific integrated circuits noted above, a description will now be given of the specific inventive circuit by which the elements are interconnected, followed b~ a description of the form of signals to be stored in the memories of the microcomputer system and of the input-out peripheral inte~rated circuit 8 to enable them to operate in accor~an oe with this invention. The specific ~orms of the signals which are stored to cause operation of the microccmputer system (referred to below as programs) are alternative depending on the specific approach taken by the program-designer. Accordingly since various forms of programs can be written to fulfill the invention, its basic logic of formation will be described with reference to a flow chart from which the program can easily be written by a person skilled in the art. It is believed that this is a clearer descriptian by which the form of the signals to be stored by the microcc~puter to control its cperation may ~e understood, rather than by providing lists of binary bits and specific storage locations, or by providing lists of mnemonics. However by way of oompleteness an Appendix to this specification provides specific mnemonic lists, forming an operable and useful program for implementing operaticn.
The microccmputer system is shcwn in more detail in Figures
In a game such as Bingo, randcmly selected numbers are called out in sequen oe of their selection by a game operator, and players utilize cards on which are printed numbers correspanding to some of those which are called. Sin oe a smaller nu~ber of numbers than those randomly selected are printed on each of the cards, the players participate in a game of chan oe to establish which will first obtain a series of numbers in a pre-determined pattern, such as in a straight line, two lines forming the letter "T", etc.
Such games have become highly popular, and as such, are often carefull~ controlled under the law. Ihe randomness of selection of numbers, for instance, must be ensured, the possibility of any of the numbers being called must be equal to all others, and it is highly desirable, particularly in games which are open to the general public, to utilize a display which illuminates each number after it is called for the remainder of the game.
In one oommon form of the game, a transparent box or cage is provided within which are disposed a number of light balls such as ping pong balls, each of which carries one of the numbers to be called. A hole with a ball-catching channel forms an exit to the cage, and a oentrally lccated fan at the bottom of the cage blcws and scatters the balls. Since the only exit to the cage is the channel, one or more balls is blown into it, allcwing the operator to select each ball in sequence out of the ball~
catching channel, the numbers thereon therefore being rendered in totally randcm sequence.
The operator nGrmally calls the number via a public address system after selecting the outer ball in the ball-catching charmel, and he deposits the ball into a correspondingly numbered hole in a Bingo table.
The ball is lightly posted into the holel and is caught by a spring which holds it in its depressed position. On oe depressed, the ball operates an actuator pin of a microswitch or leaf switch. Current pass mg through the switch is directed to a lamp immediately behind a translucent pane ~03Z
~hich carries a number painted thereon which corresponds to the nu~ber of the ball which had been called and is held in the correspondingly num~ered hole.
In this manner each of the balls which had been called causes a corresponding number to be illum m ated in the displ~y for the remainder of the game, allowing the players to check all previously called numbers as the game progresses.
Once the game has been completed, the operator normally shifts the table, moving the balls past the microswitch locations, allowing them to fall into a bin or sink which has its exit into the lower box or cage.
The present invention is directed to an electronic circuit which interfa oes the switch positions actuated by each depressed ball, and among other functions, illuminates the proper lamps in the display.
It should ke noted that in the above-described Bingo system each switch corresponding to a ball position in the operator's ball table extends to a corre~ponding lamp via an individual wire; there is also a single grcund return for all lamps. Bingo or similar games normally utilize 75 or 90 numbers and consequently it is clear that the cable from the Bingo table to the display must be extremely thick, heavy and unyielding. Furthermore, because of the large number of wires, it is costly and difficult to extend the display over a large distance as might be required at two ends of a Bingo hall (scmetimes reguiring the length of cable of as much as several hundred feet, for example).
With such a large number of wires, there is also the danger of breakage of one or more of them as the cable is flexed. This decreases the reliability of the cable as the Bingo table is set up or taken down at the end of each day's games, and it also introduces the possibility of short circuiting due to breakage of the wires. Breakage of the wires also introduces a possibility of danger to personnel utilizing the system, since the breakage could occur at a position adjoining a-pparatus ~hich is tcuched by the operator or by the players. Clearly, flexing of the multi-wire cable repeatedly places substantial stress on each of the 3;Z
wires, and can result in reliability problems with the apparatus as well as a danger to the public due to the potential for shock.
Sln oe such systems are wired directly from switch to liaht bulb to pcwer supply, its manner of oFeration is fixed. m e depression of a ball into the appropriate hole in the Bingo table results simply in the illumunation of a corresponding light bulb.
m e present invention, an the other hand, provides a display which is variable at the push of an operator's button. The last number which has been called is shown on the display bcard as an ill~ninated number, but continuously flashes to inEorm the players which number was last called. Gn oe anather number has been called, the flashing stops and the new number is displayed by a flashing l~np.
The operator is also able to signify a "win" by the illumina-tion of various patterns of lights, for instance, all of the liyht bulbs may be caused to flash in sequence so as to portray a "starburst" moving pattern, which has been found to be an exciting display for players.
Further, a local display for the operator begins flashing after a pre-deterrnined (and variable) period to indicate to him when the next number should be called, and thus provides an even pace to the game.
Of further significance in this invention is the reduction of the cable to contain no more than four individual wires. me length of the cable can be extensive, and have been tested as being reliable over as much as 1,000 feet, cle æ ly sufficient for virtually all indoor locations. It should be noted that the aforenated length is not lirniting, but is merely the length to which the early prototype of this inventian was tested.
It is not intended that this invention be limited for use with Bingo. Other displays ~such as advertising or other illuminated indicator boards as are often found in sports arenas or sports fields can use the inventive systern. Ho~ever, the follcwing disclosure will be directed to an explanation of use in a Bingo game for each of description of the preferred, but not the only embodiment.
The advantages of the invention are obtained in a system for electronically randomly sel~cting a number and illuminating selected ones of a plurality of lamps located at a remote location com~rising an electronic random number generator, a control switch, a general display for individually illuminating one or more numbers corresponding to the generated random number, and means for causing illumination of said corresponding number upon generation of said random number and upon at least temporary operation of said control switch. Preferably, the random number generator is comprised of a microcomputer system, including data and program memories connected to a central processing unit, adapted to generate a random number signal and to store and process signals representative of the generated random number signal as well as signals representative of a signal processing sequence, and to derive and store signals representative of one or more of said lamps to be illuminated, as a result of translation of the processing sequence signals, the means for causing illwmination of said corresponding numbers comprised of converter means connected to the storing means for translating the random number slgnal into a serial bit stream signal representative of the address of one or more particular lamps to be illuminated, and a display bus connected to the output of the converter means for carrying the serial bit stream signal, ~or connection to a serlal bit stream signal decoding and lamp illumination circuit.
A better understanding of the invention will be obtained by reference to the description below, and to thP
following drawings, in which:
Figure 1 is a block schematic of the invention;
Figures 2 and 3 form a block schematic of the microcomputer portion of the invention;
Figures 4 and 5 form a schematic diagram of the input and output interface and controlling portion of the invention;
Figures 6 and 7 form a schematic diagram of the decoding and lamp driving portion of the invention, Figure 8 is a schematic diagram of the connections from Figurees 4 and 5 of the local digital display;
Figure 9 is a waveform diagram showing the signals at various locations in the input and output interface, controlling, decoding and -4a-lamp driving portions of the invention;
Figure 10 is a plan of the storage locations for various cross-point switch numbers, to be illuminated when aperated, in the memory of the input-oùtput peripheral;
Figure 11 is a plan of the contents of the microccmputer registers;
Figure 12 is a pLan of the cantents of the buffer store of the input-output peripheral;
Figure 13 is a plan of the lamp positions of the game pattern display board;
Figures 14 and 15 form a flcw chart of the logic behind the formation of the signals stored and operated by the microccmputer in respect of the main program;
Figures 16 and 17 form a flow chart of the logic behind the formation of the signals stored and aperated by the microoomputer in res-pect of the interrupt routine;
Figure 18 forms a flow chart of the logic behind the formation of the signals stored and operated by the microcomputer in respect of the interrupt subroutine;
Figures 19 and 20 form a flow chart of the logic behind the formation of the signals stored and aperated by the microco~puter in respect of the system subroutine;
Figures 21 and 22 form a flow chart of the logic behind the formation o~ the signals stored and operated by th~ microcomputer in respect of the display pattern subroutine, and Figure 23, which is on the same page as Figure 13 is a block schematic of a system for generatiny random num~ers.
Thrning now to Figure 1, a microcomputer system 1 for use in this invention is shown. The system is ccmprised of a central processing unit 2, ~7hich is preferably type 4040 single chip 4-bit P-channel micro-pro oe ssor which is available frcm Intel Corporation, Santa Clara, California.
Cannected to the central processing unit is a clock generator 3, which is preferably type 4210A, also available from Intel Corporation, - iL14~r~3 driven by a 5.185 megaher~z c~ystalO
Also connected to the central processing unit 2 is a P
(programable read only memory) driver and selector 4, preferably type 4289 also available fram Intel Corporation.
One or more PRQMs 5, such as type 4702A, available from Intel Corporation, is connected to the PRQM driver and selector 4. Associated with the PRCMs 5 and driver and selector 4 can be one or more binary decoders (not shown in Figure 1) for aiding in the selection of a particular PRCM at a required time.
Also connected to the central processing unit 2 is a data RAM (random access memory).
m e elements so far disclosed are connected together via address and data buses, as well as sync, clock, and other leads required f or proper operatiQn thereof. It is assumed that a person understanding this invention is able to assemble this microcomputer system, including determining the memory size required, and therefore the system has only been show~ in block diagram. However~ data sheets describing the inter-fa oe , operation, inter-relationship, and progra~m m g of the specific type of elements noted above are available from the aforenoted Intel Corporation. For the em~odiment described below, three 4702A PRCMs are sufficient.
An output b~s 7 of microccmputer system 1 contains four data leads Do~ Dl, D2, D3, a clock lead, a reset lead, a sync lead, and a cle æ memory lead, the latter useful for an ex*ernal memory.
Output bus 7 is connected to an input-outptlt peripheral integrated circuit 8. Preferably this peripheral is type 4269 which is available fr~n the aforenoted Intel Corporation~ This integrated circuit i~ ccmprised of a random ac oe ss m~mory, means for prcviding a scanning autput signal, means for sensing a scanned input signal, a bus interfa oe circuit, instruction decoding, control logic and timing cir-cuitry, and display registers, as well as interconnection circuits. As its m~de of operation is pt~lished, ~hich publication is availahle f~n Intel Corporation, a description of its internal op~ration will not be described.
Its scanning output ternunals, hcwever, are connected via bus 9 to a matrix of crosspomts 10. The output of the matrix of crosspoints 10 is connected to a scanned signal input to the input-output integrated circuit via bus 11, preferably through a crosspoint switch buffer 12.
me output of the internal random acoe ss memory from the display register of peripheral 8 is applied via bus 13 to a parallel-to-serial converter 14 ~hich changes the parallel form of the cutput to serial form on a data lead. m e output of the converter 14 is also applied to a clock lead for carrying clock pulses, to a reset lead for clearing the output display, and to a ccmmon lead.
m e four leads noted above are sufficient to carry all required information to the system display. Due to the small number of wires, the ~hle can be twisted and passed along and through locations with very littie stress in ccmparison to that which would be incurred by a 76 or 91 wire cable.
m e end of the cable 15 is connected to a buffer 16 which reconstitutes the square waveform of the pulses carried by cable 15, and raises their amplitude to a level sufficient to drive the following logic.
m e data, clock and reset leads at ~he output of buffer 16 are applied both to an address and board select decoder 17 and to a serial-to-parallel converter 18. I'he latter converter converts the data back into parallel form and is applied in parallel to a plurality of latches, ~hich in turn are cor~ected to a plurality of light drivers ~both in block 19).
The output of the address and bc~rd select decoder 17 is connected to an indicator latch select circuit 20, the output of which is connected to individual ones of the latches. Acoordingly a data signal is applied from the serial-to-parallel converter 18 to all latches 19 together, and the indicator latch select circuit 20, driven by the address and board select decoders 17 enables the specific latches at specific times to register and hold the data signal which is applied at that particular time fram the ~erial-to-parallel oonverter 18.
Individual lamps 21 connected to the light dri~ers, for instan oe through silicon oontrolled rectifiers or switches, are accordingly lit up at locations determined by the data signal and the address carried by cable 15, thus providing a display for the players of the game.
Preferabl~ the parallel-to-serial converter 14 is integrated circuit type 74151 available fro~ Fairchild Corporation. Serial-to-parallel converter 18 is preferably integrated circuit type 7496, address and board select decoder 17 and latch select 20 are preferably camprised of type 7442 in conjunction w~th type 7493 integrated circuits, and latches and light drivers 19 are preferably comprised of integrated circuit type 7475; all are avaiLable fram the aforenoted Fairchild Corporation.
Also cannected to microcamputer output bus 7 is a decoder and display driver 22, to the output of which is connected a two digit digital display 23 through drivers 24.
In operation, a crosspoint is closed somewhere within the matrix of crosspoints 10, by the operator depressing a numbered ball which has ~een randamly selected against a crosspoint switch which crosspoint is similarly numbered. Each of the raw ccnductors of the matrix of cross- I
points is scanned in sequence fram scanning output bus 9 of input-output integrated circuit 8, under control of the microcamputer system 1. With the closing of a crosspoint, the scanning pulse at the particular row conductor of the crosspoint is transferred to the adjacent column conductor and via switch buffer 12, is applied to one of the leads of input bus 11.
A signal on one of the leads of input bus 11 causes a system interrupt to ke generated, and under control of the microcamputer system, the input-cutput peripheral translates the matrix position to an indicator lamp address and data signal as to which addressed lamps are to be illumunated, shut off, flashed, etc., at particular times.
At the same time~ the translated address appears at the output bus 7 of the microcomputer system 1 due to the microccmputer system having performed the translation and providing the data signal back to integrated -~L~
circuit 8. The same data signal is applied to the decoder and display driver 22, which deocdes the data and causes the two digit digital dis~l~y 23 to provide an indication of the selected crosspoint matrix location, as a numerical output. m is numerical output is the same as will be illuminated by lamp 21, on oe actuated.
Closure of a further matrix crosspoint, one which has been predetermined for control, is then closed. As before, this causes genera-tion of a system interrupt which recognizes the particular crosspoint which has been closed. In this case, the microcGmputer system 1 causes an cutput signal to be generated on bus 13 which designates which lamp 21 is to be illuminated to display the num~er similar to that shown on digi-tal display 23.
Converter 14 changes the data on the parallel bus 13 to serial form, which is applied to cable 15, on the data, clock, and reset leads, with a ccmmon return. .
At the other end of cable 15, adjacent the display, is connected buffer 16 which remKves noise signals which may have been imposed on the signals carried by cable 15, and raises their potential level and shorten their rise ti~e ~o J~k~ reouired by ccnve~ter 18 ar~ ~ecoder 17.~ Ccnver~er 18 is connected to the output of buffer 16 and changes form of the signals to the parallel form requ~red by the latches of block 19. m e required data is applied to all latches in parallel.
m e output of buffer 16 is also connected to the input of address and bcard select decoder 17. miS circuit determunes first that it is the subject display which is to be addressed, and it further decodes the address of the specific lamps which are to be illumunated. m e output signal of deccder 17 is oonnected to the input of indicator latch select circuit 20, the output of which is connected to individual latches of block l9. Accordingly its decoded address enables a specific latch or grcup of latches to operate and store the data signal from oonverter 18 for the illumination or shutting off of a particular lamp 21 at a particular time. The output signal of the latches are applied to light _9_ drivers, which cause cperation of shutdown of l~nps 21.
In brief review, the aforenoted apparatus displays a selected number to the operator on two digit display 23 and at the same time illumin-ates the correct number on the display. If the ball was placed in the wrong hole, a further can oe llation crosspoint is closed, which turns off the latest display number; the operator then pla oe s the ball in the correct hole.
It is preferred that upon depression of each crosspoint indicating selection of a number to be displayed, the data and the address to which the data is applied should cause the light to turn on and off sequentially, i.e. to flash. On oe a following crossp~int has been closed, the data for the preceding lamp is changed causing steady illumination, and the data directed to the address of the lamp corresponding to the newly closed crosspoint causes the associated newly selected lamp to flash.
With the above general system configuration described, and the assumption that a person skilled in the art fabricating this invention understands the operation of the specific integrated circuits noted above, a description will now be given of the specific inventive circuit by which the elements are interconnected, followed b~ a description of the form of signals to be stored in the memories of the microcomputer system and of the input-out peripheral inte~rated circuit 8 to enable them to operate in accor~an oe with this invention. The specific ~orms of the signals which are stored to cause operation of the microccmputer system (referred to below as programs) are alternative depending on the specific approach taken by the program-designer. Accordingly since various forms of programs can be written to fulfill the invention, its basic logic of formation will be described with reference to a flow chart from which the program can easily be written by a person skilled in the art. It is believed that this is a clearer descriptian by which the form of the signals to be stored by the microcc~puter to control its cperation may ~e understood, rather than by providing lists of binary bits and specific storage locations, or by providing lists of mnemonics. However by way of oompleteness an Appendix to this specification provides specific mnemonic lists, forming an operable and useful program for implementing operaticn.
The microccmputer system is shcwn in more detail in Figures
2 and 3, and its str~cture will be briefly descriked. Microprocessor 30 is connected at its data terminals Do~ Dl, D2, and D3 to similarly identified data terminals of memory interface integrated circuit 31. This circuit prGvides the PRQM dri~e and selectian function descriked earlier with refer~nce to Figure 1. Its data output terminals Ao~A7 are connected to the data input terminals of PRQM 32, which has its own output terminals connected to input termlnals GPAo~OPA3 and OPRo-OPR3 of integrated circuit 31.
Memory interfaoe integrated circuit 31 also has address output terminals Co-C3~ which are connected to input term mals Ao~A2 and El of 1 out of 8 binary decoder 33. The address cutput terminals O0-O3 are individually connected to specific P~nMs, in order that a specific PRDM
can be addressed to apply or receive data on the data bus interconnecting the PR~Ms to the memory interface.
Also connected to the mlcroprocessor 30 is a clock generator 34, to which a 5.185 megahertz crystal 35 is oonnected. Clock generator 34 is connected to microprocessor 30 via corresponding reset terminals, and via correspondingly numkered clock frequency terminals 01 and 02~ The aforenoted clock output and reset terminals are also connected to memory interface 31. Sync terminals of the microprocessor and memory interfa oe are also interconnected.
The clock leads 01 and 02' the sync lead, the reset lead and the fcur data leads Do~D3 are also connected to a ~AM 36, preferably being a 320 bit random acoess memory with a 4 bit output port on leads Do~D3. An auxiliary output from the R~l is obtainable at output terminals O0-O3.
The aforenoted leads are accessed as the microcomputer output bus 7 also including rlear memory leads CM RAM 1 and CM R~M o from the microcomputer 30. m e latter lead is connected to RAM 36, and functions to clear stored data signals out of that memory upon control by micro-processor 30.
Other resistors, capacitors and power leads are shcwn for appropriate connection to the aforenoted elements. m e structure and mutual operation of the elements of the microcomputer as well as the nature of the stored program signals are within the skill of a person skilled in the art, and full details of their operation is obtainable from the afore- -noted Intel Corporation.
Turning now to Figures 4 and 5, the input-output control structure is shown. It will be understood that an external switch matrix shculd be used, preferably ccmprised of rows and columns of conductors whi~h can be made to contact at a particular crossp~int. In the Bingo form of the game, crosspoint contact is made by depressing a numker d ball at the intersection of a similarly numbered raw and column conductor.
A suitable crosspoint matrix is described in Canadian patent application serial 290,796, filed November 14, 1977, invented by Graham-A. Jullien.
However, the present invention is not limited thereto; the crosspoint array can be made of microswitches having one terminal of each row of switches connected together, and one terminal of each column of switches oonnected together.
For example, in the 90 number game there might be 8 r~w conductors and 16 column conductors to provide 128 crosspoints, which prcvide sufficient crosspoints both for the numbers and for control functions.
Input-output perip~eral integrated circuit 37, as noted earlier, includes means for scanning an array of terminals 50-S7 by applying a high level signal to each termunal in sequen oe. Each terminal So-S7 is connected to a respective horizontal conductor of the crosspoint matrix. Input-output peripheral 37 also is ccmprised of 8 scanned input terminals Ro-R7. Each of these terminals is connected to each of 8 vertical conductors ir. two groups, of the crosspoint matrix.
Memory interfaoe integrated circuit 31 also has address output terminals Co-C3~ which are connected to input term mals Ao~A2 and El of 1 out of 8 binary decoder 33. The address cutput terminals O0-O3 are individually connected to specific P~nMs, in order that a specific PRDM
can be addressed to apply or receive data on the data bus interconnecting the PR~Ms to the memory interface.
Also connected to the mlcroprocessor 30 is a clock generator 34, to which a 5.185 megahertz crystal 35 is oonnected. Clock generator 34 is connected to microprocessor 30 via corresponding reset terminals, and via correspondingly numkered clock frequency terminals 01 and 02~ The aforenoted clock output and reset terminals are also connected to memory interface 31. Sync terminals of the microprocessor and memory interfa oe are also interconnected.
The clock leads 01 and 02' the sync lead, the reset lead and the fcur data leads Do~D3 are also connected to a ~AM 36, preferably being a 320 bit random acoess memory with a 4 bit output port on leads Do~D3. An auxiliary output from the R~l is obtainable at output terminals O0-O3.
The aforenoted leads are accessed as the microcomputer output bus 7 also including rlear memory leads CM RAM 1 and CM R~M o from the microcomputer 30. m e latter lead is connected to RAM 36, and functions to clear stored data signals out of that memory upon control by micro-processor 30.
Other resistors, capacitors and power leads are shcwn for appropriate connection to the aforenoted elements. m e structure and mutual operation of the elements of the microcomputer as well as the nature of the stored program signals are within the skill of a person skilled in the art, and full details of their operation is obtainable from the afore- -noted Intel Corporation.
Turning now to Figures 4 and 5, the input-output control structure is shown. It will be understood that an external switch matrix shculd be used, preferably ccmprised of rows and columns of conductors whi~h can be made to contact at a particular crossp~int. In the Bingo form of the game, crosspoint contact is made by depressing a numker d ball at the intersection of a similarly numbered raw and column conductor.
A suitable crosspoint matrix is described in Canadian patent application serial 290,796, filed November 14, 1977, invented by Graham-A. Jullien.
However, the present invention is not limited thereto; the crosspoint array can be made of microswitches having one terminal of each row of switches connected together, and one terminal of each column of switches oonnected together.
For example, in the 90 number game there might be 8 r~w conductors and 16 column conductors to provide 128 crosspoints, which prcvide sufficient crosspoints both for the numbers and for control functions.
Input-output perip~eral integrated circuit 37, as noted earlier, includes means for scanning an array of terminals 50-S7 by applying a high level signal to each termunal in sequen oe. Each terminal So-S7 is connected to a respective horizontal conductor of the crosspoint matrix. Input-output peripheral 37 also is ccmprised of 8 scanned input terminals Ro-R7. Each of these terminals is connected to each of 8 vertical conductors ir. two groups, of the crosspoint matrix.
3~ m e structure is also cGmprised of 16 externally enabled electronic switches, preferabl~ CMOS switches 38. Each of the CMQ6 switches contains an input terminal, which terminals are divided into tw~ groups OA-7A and OB-7B. Each of the input terminals is connected to each of the 16 vertical conductors. A resistor 39 connects each of the 16 CMOS switch input leads to a constant voltage plane, -lOV.
me output terminals of the 8 CMOS switches to which input terminals OA-7A are themselves connected to the scanned input terminals Ro~R7 of the input-output peripheral 37. m e output terminals of the CMCS
switches having input terminals OB-7B are individually connected in parallel with the output terminals of the first set of CMOS switches to scanned input terminals Ro~~ of input-output peripheral 37.
It should also be noted that scanning output terminal S7 is connected directly to input terminal 7A of th~ last CM~S switch 38.
m e enable input terminals of the CMOS switches having input terminals OA-7A are connected together to enable lead 40, and the enable input terminals of the CMKS switches having input terminals OB-7B all connected together to enable lead 41.
m e input-output peripheral integrated circuit 37 also has an RS output terminal which is at a high level for the duration of each alternate scan, and is at low level for each alternate scan~ m is output term~nal is connected to the input terminals of a pair of CMOS switches 42 and 43. Ihe output terminals of CMCS switches 42 and 43 are both connected to the input terminals of CMOS switches 44 and 45, one input terminal of which is connected in a circuit path to a -lOV souroe , and the other of which is connected in a circuit path to at 5V source, both through a pair of resistors. With the power supply input of switch 42 connected to -5 volts and the power supply input of switch 43 to -lOV, and both of switches 44 and 45 to ~5V, the resulting operation of the 4 switches when alternately high and low level signal is applied to the input of switches 42 and 43 from the RS terminal is to apply high level signals alternately to enable leads 40 and 41.
Accordingly it will be seen that as a high level signal apFears on lèads So-S7 of the input-output peripheral 37 in sequence, for the entire duration there will be a hi~h level signal appearing on the RS
terminal, which, with the-operation at this time of CMOS switches 43 and 44, eauses a high level signal to appear on enable lead 41. Aecordingly for the present scan period CMOS switches 38 whieh have input terminals OB-7B are enabled.
With no erosspoint being closed, none of the latter CMOS switches will conduct, and there is no scanned input signal applied to terminals Ro-R7 of the input-output peripheral 37. Should one of crosspoints have been closed the high potential level signal appearing on one of the row eonductors of the matrix leads connected to terminals So-S7 at a pæ ticul æ
time during the scanning eyele is transferred to the column eonductor at the erosspoint, and to the input of one of the CMOS switehes having input terminals OB-7B. Sin oe this group of CMOS switches had been enabled via enable lead 41, the high level signal is passed through a corresponding CMCS switeh and is applied to one of the input terminals ~-R7.
During the i~mediately following scanning cyele, the signal level on the RS lead is at low le~el. CMOS switehes 42 and 45 operate to cause the potential on enable lead 40 to rise in level, and the potential on enable lead 41! to drop to 1~7 level. Aeeordingly, the CM06 switehes whieh have input terminals OB-7B are disabled, and CMOS switehes 38 whieh have input terminals OA-7A are now enabled.
Should a erosspoint switeh elosure be deteeted, of eourse it will have no effect during this scanning cyele on the CMCS switches hieh are now disabled. Hcwever, should it eorrespond to a vertical matrix eonduetor which is connected to one of the CMOS switehes which is now enabled, high level signal frcm the appropriate sequentially seanning termunals So-S7 is transferred through the elosed erosspoint to the input of one of the termunals P~0- ~ .
me partieular input output peripheral 37 used in the present embodiment, t~pe 4269, is only capable of storing the switeh elosures of 64 erosspoints, ~i.e., made up by a block matrix of 8 by 8 switches). However the Bingo ga~e utilizes a larger number of erosspoint switches, i.e. 75 or 90 in nl~nber plus control switches. To recognize and sean the remaininq ~7itches, 3~
an additional block of s~"itches comprising a further 8 by 8 matri~ is used.
One switch, of column 8, rcw 8 of the second block is permanently closed.
A system interrupt is generated when this (or any other) switch closure is sensed. With the corresponding switch of column 8, row 8 of the first block of switches, the operation program provides means for detecting when the first or second block of switches has been completely scanned, sin oe the binary bit in the R~M portion of peripheral 37 at the location for column 8, row 8 is caused to change state every time the corresponding switch of the second block of switches is scanned. In this manner the switch closure positions from the two blocks of crosspoint switches are separated. The capabilities of the peripheral 37 is thus extended from 64 crosspoints to 126 (128 less 2). The program for implementation will be described in more detail belcw.
The counting of memory storage locations continues continuously for each successive scanning cycle until the high level input interrupt from the aforeno~ed column 8, rcw 8 crosspoint, or from another crosspoint, is re oe ived. With re oe ption of this interrupt signal, there is a recycling and restarting of the count of me~ory locations from the keginning, which is of ccurse coincident with the keginning of the first of the two scanning cycles. Preferably the interrup-t is set to occur every 5 milliseconds.
The column 8 scanning output terminal S7 is connected through a diode Dl to the input of AND gate 46. The other input of AND gate 46 is connected through a diode Dg to the enable input of CMOS switch 45 which, it will ~e recalled, when activated, causes a high level output signal on enable lead 40. AND gate 46 therefore will be activated at the same time as CMOS switch 38 having input terminal 7A~ that is, when the scanning output termunal S7 is active, as well as enable lead 40 ~hich causes the enabling of the CMOS switches 38 to which input terminals OA-7A are connected. In short, AND gate 46 provides an o~t~ut signal at the same time that terminal ~ on the input-output integrated circuit 37 is operated directly from S7 terminal via its direct connection to termlnal 7A; there is direct coinciden oe with the interrupt signal.
3;Z
~ ne out.~ut ter~nal of ~D gate 46 is connected to the O
terminal of flip flop 47, as well as through an inverter to the P termunal.
The signal at the Q output of flip flop 47, after keing applied to LED
driver 48, is applied to the reset lead of the output cable to display.
As was noted earlier, the input-output peripheral 37 contains a pair of display reglsters which have output terminals Bo~B3 and Ao~A3/
forming an 8 bit parallel bus output. There terminals are connected via the 8 parallel leads of the bus to Do~D7 of a binary to serial multiplexer 49. The output of m~ltiplexer 49 is applied to the input of a line amplifier 48, the output of whi~h is applied to the data lead of the output cable.
m e individual leads of the output bus 7 described earlier ~ -are connected to corresponding terminals of the input-output peripheral 37, a clear mEmory CM RAM O terminal (for the internal RAM of peripheral 37), a sync termunal, data terminals Do-D3, clock inputs 02 and 01~ reset, and common lead INT.
A signal on the CM RAM O lead clears all data signals stored in the memory of the input-output peripheral 37. A signal on the sync lead indicates the beginning of an instruction, i.e., the beginning of a complete - scanning cycle, etc. It is from this lead that a clock signal is develcped for display.
The sync lead is connected through an isolating resistor 50 to the base of transistor 51, to which a base diode 52 is a~nnected to ground.
m e collector output of transistor 51 is connected to the input of a bit binary counter 53, the first count output of which is connected to one input of AND gate 54. Another count output of binary counter 53 is connected to input T of flip flop 55 as well as to inverter 56.
Other count outputs of four bit binary counter 53 are connected to the A and B clock inputs of binary to serial multiplexer 49, and the out-put of inverter 56 is connected to clock input C of multiplexer 46. The particular count output terminals ~hich are connected to the A, B or C
terminals of ~ultiplexer 49 and to flip flop 55 are shcwn for the noted part numbers, and are determlned by the required timung, and should other components than those descri~ed be used, 'heir corlnections are left to the person skilled in the artj It is preferred that the 4 bit binary ccunter be type 7493 available from Fairchild Corporation, and that flip flop 55 should ~e type 7474 available from the same sour oe.
m e Q output of flip flop 55 is connected to the second input of AND gate 54. The output of AND gate 54 is connected to inverter amplifier 57, the output of which is connected to a line amplifier 48, the output of ~hich is applied to the clock lead of cable 15.
m ere should clearly be a large division between the frequency of the sync pulse on the sync lead and the pulses appearing on the clock lead. However, the operation of binary counter 53 pr~ides timing signals to multiplexer 49 to sequen oe the serial format output bits corresponding to the parallel format input bits applied to it, in synchronization with the cloclc pulses derived through AND gate 54.
The binary to serial multiplexer 49 is preferably integrated ~rcuit type 74151 which is available from Fairchild Corporation. Amplifiers 48 are preferably each type 7S49 which are available fram the same sour oe .
The previously listed leads of output bus 7 from mlcrooomputer 1 are also applied to a decoder and display driver 58, which preferably is integrated circuit type 4265, available fram Intel Corporation. The decoder and display driver 58 is adapted to convert data from the data bus leads Do~D3, under control of the clock and synchronization pulses of the 01~ ~2~ and sync leads and to convert the signals into parallel coded signals to ~e applied to the individual segments of a numerical display, such as a light emitting diode (LED) display. The output terminals of the decoder and display driver are shown as Wo-W3~ Xo-X3/ Yo-Y3~ and Z0-Z3.
mese cutput terminals are connected to the input of inverter amplifiers 59 to output leads aM,bM, CM~ dM, aL, bL, CL~ dL, eM~fM~ YM~ / L~ L
gL, and enable. These leads are connected to the individual leads of the correspanding LED seg~ents 60 (forming the most significant digit) and 61 (forming the least significant digit), see Figure 8.
With the ccnnec-tions shown, the signals on the data bus corresponding to the crosspc~nt which had been closed in the eY.ternal switch matrix causes immediate display of the number correspcnding to the crosspoint by the LED display. T~is display is preferably located adjacent the game operator, such as part of the Bingo game table itself.
It should be noted that binary counter 53 and flip flo~ 55 as well as AND gate 54 are connected in a manner such that only 8 clock pulses are generated from the sync lead per output eight digit character.
Each of the scanning output terminals So-S7 of input-output peripheral 37 is connected through a corresponding diode Dl-D8 to a resistor to the base of transistor 61. Accordingly, each scan pulse is passed through transistor 61; its collector output is applied to the reset inputs of counter 53 and flip flop 55. As a result, the scanning pulse train from transistor 61 causes reseting of the counter 53 and flip flop 55, which act as multiplexer address counters, and are accordingly reset. A reset pulse is also generated as described earlier derived from terminal S7 of peripheral 37, through diode Dl, AND gate 46, to the reset lead of the cable 15, which synchronizes the output serial clata to the first character.
m e timing for the reset pulse relative to the signal on the RS output of peripheral 37, the clock pulses and the reset pulses of 'che counter 53 are shown in Figure 9.
As noted earlier, cable 15 leads to the inclicator circuit board, and sin oe it is comprised of only 4 wires, can be both lengt~y and flexed around short radius corners.
Turning now to Figures 6 and 7, the end of cable 15 is sho~
The data,clock, and reset leads are connected individually through small valued resistors 65 to the input of indivldual optical isolators 66. m e return lead of the input of all of the optical isolators are connected together and to the c~n~.on lead of cable 15. At the originating end of cable 15, the c~mon lead is connected to a sour oe of potential,V ~see Figures 4 and 5). Accordingly, as each IED driver amplifier 48 on the Data, Clock and Reset leads is switched on, a circuit is conpleted causing current to pass through the corresponding optical isolator 66. The output transistor within the corresponding isolator is turned on, causing its collector to pull the voltage from a high to a low potential state.
When the amplifier 48 are switched off, open circuiting the aforenoted circuit, the collector voltage goes back to the high state. m e individual output leads of optical isolators 66 are ccnnected to the resistors 166 and to the individual inputs of Schmitt triggers 67.
The function of the optical isolators is to convert the current loop data transfer pulses into voltage pulses, and to provide electrical isolation between the microccmputer system and the light driver electronics.
r~he current loop data transfer preferably uses currents in excess of 20 mA and provides excellent immunity frcm interference and general stray effects. The relatively slow response of the isolator also minimizes cable ringing effects. Electrical isolation is required where the display lights are directly driven from a 115V mains supply. The function of the Schmitt triggers 67 is to reconstruct each pulse into square wave form in order that these pulses reliably operate the following electronic devices.
rrhe output of Schmitt trigger 67 to which the data pulses are applied is connected to a serial-to-parallel decoder 68, which is preferably in the form o~ a 4 bit capacity shift register, such as type 7496 available fro~ Fairchild Corporation.
The output of Schmitt txigger 67 to which the clock pulses are applied is also connected to the clock input of the aforeno-ted shift register 68. Since the shift register has capacity of four bits, every four clock pulses on its output leads 69 contain a four bit binary word.
'rhese ~ords are applied via output leads 69 to the input of latches 70.
Preferably the latches are type 7475, available from Fairchild Corporation.
ach four bit binary word designates one out of four of the latch circuits within ]atches 70 to lock up to an operative level. Each latch circuit is connected through a resistor Rl-R32 to the gate of an individual one of silicon controlled rectifiers Sl-S32. Each siliccn controlled rectifier is connected from a 0 voltage plane through an in-dividual lam~ Ll-L32 (not sha~) to a la~p current supply.
-1~
As each latch requires a 1 out of 4 cperate instruction with each four bit binary w~rd, it i.s necessary to address the particular latch which is to release its information and activate the appropriate silicon controlled rectifier to cause illumination of the appropriate light kulb on the display.
The clock output of Schmitt trigger 67 is applied to the input of counter 71. Gne output of counter 71 is connected to the input of ccunter 72. The outputs of counter 71 and 72 are ccnnected to decoders 73 and 74, both directly and serially through AND gates 75, 76, and 77 as shohn.
me reset signal from the reset lead after passing through its corresponding optical isolator and Schnitt trigger is applied to the reset input of both of counters 71 and 72.
- Decoder 74 decodes the latch addresses for the latches 70;
whereas decoder 73 determunes whether the address is designated for the shown latches.
To provide a full complement of 75 or 90 nu~bers, additional æ
circuits will be connectea to cable 15, ~ic~l circuits are designated ~y a different block designator. me block select jumper connects decoaer 74 to the appropriate output of decoder 73 to ensure that the present display operate circuitry is the one designated for operation. Sin oe the address deccding is established from the clock pulses, the block select jumper merely enables decoder 74 at an appropriate time for each data word received from the cable. It~is preferred that the data signal shculd consist of 128 bits broken into four 32 bit blocks. Block select jumper therefore causes decoder 74 to designate the appropriate address during one block of the four 32 bit blocks in each data w~rd signal.
The outFut leads of decoder 74 are individually connected to one of the inputs of each of respective NOR gates 78-85. The output of each of the NOR gates is individually connected to the enable input of respective corresponding latches 70. It shouLd be noted that there are two ways of addressing latches 70 shcwn. In one case NOR gate 78 addresses its corres-ponding latch, as do the remaining NOR gates address latches 79-85. One input of each of NOR gates 79-85 is individually ccnnected to corresponding individual outputs of deccder 74O m e other inputs of NOR gates 79-85 are connected together and to a sour oe of inhibiting voltage. Each of the latches 78-85 enables its corresponding latch 70 when an appropriate output is obtained from decoder 74.
In the second way of addressing, instead of being connected via the latch select jumFer 86 to a source of inhibiting voltage, the second input of each of the NOR gates 79-85 can be connected to one of a group of 4 leads connected to the output of the Latch to ~hich NOR gate 78 is connected. AccordingLy the data word signal which is decoded by decoder 68 appears at the output of latch 70 to which NOR gate 78 is ccnnected determines the time at which the remaining NOR gates 79-85 are enabled.
Accordingly there is a substantial expansion of the capability of the apparatus to respond to the data signal, which is in effect an increasing of the effective data storage of the input-output peripheral 37.
Wi~h the latch select jumper 86 connected to any of the four 3~
outputs of the latch 70 to which NOR gate 78 is connected, NOR gate 78 is first activated with a particular word signal decoded in decoder 68. Latch 70 performs decoding, causing, for instance, one of its output terminals to be at the proper operate level for one of the input leads of NOR gates 79-85. A second address is thus formed and not only is an address of c~ecoder 74 required to activate one of NOR gates 79-85, but also an address resulting from the four bit binary word decoded via latch 70 which is activated through NOR gate 78. Sucoe ssive four bit binary words can there-fore be used to activate various latches in suc oession as a result of an effective expansion of the addressing.
The lamp driver circuit board which is to respond to the data of the four 32 bit blocks in the 128 bit da~a stream is deter~uned by the block select jumper 87 connected to the appropriate output on decoder 73, as described earlier. Each lamp driver board has its block select jumper connected to a different output terminal of decoder 73.
In a Bingo game which utilizes either 75 or 90 numbers, it should be noted that three of the circuits just described are used, although there is capacity for four. In a three lamp-driver circuit system, there is capability for 3 x 32 96 lamps. In a 90 number system, 90 of the 96 lamps are used to illuminate the nurnbers; the rer~aining six can rernain disccnnected ~distributed as two silicon controlled rectifiers not connected per lamp driver board, preferably), or they can be used to illuminate des_gnator ~rds other than the numbers, such as whether the game is normal, a special etc. In a 75 number system, there can be 30 siliccn controlled rectifier lamp drivers cperated on two lamp driver circuit boards, and 15 on a third.
In operation, data signals are received from the data lead of cable 15 and are translated in the corresponding optical isolator 66. The output is restored to proper pulse fo~m with a short enouoh rise time to reliably operate the following logic, in Schmitt trigger 67. The serial data is converted by decoder 68 to four bit words ~lich appear on output leads 6g. The decoder 68, being a shift register, is operated frcm the clock pulses ~hich are received from the clock lead passed through Schnitt trigger 67 in a similar manner as the data signals. The four bit words whlch are designated for the present lanp driver circuit appear as a sequence of 8 four bit bytes comprising a 32 bit block of data, while binary data designated for other lamp driver boards for illuminating the same display are contained in successive four bit, eight byte data signals which follow in three suc oe ssive blocks.
At the beginning of eachl28 bit block of data, a reset pulse is present on the reset lead. After ~eing translated by the corresponding optical isolator 66 and Schmitt trigger 67, the reset pulse is applied to counters 71 and 72 which drive decoders 73 and 74. As a result an output signal ap~ears on one of the four outputs of decoder 73, which enables decoder 74 as a result of its block select jumper being connected to one of the four decoder 73 output terminals. Since counters 71 and 72 have the clock pulses as inputs, and the outputs thereof are also connected to decoder 74, decoder 74 is enabled at an input terminal A at the clock pulse fr~quency, at an input terminal B by 1/2 the clock frequency, and an input terminal C at V4 the clock frequency. m e block select enables the decoder 74 at 1/2 frequency of the signal at termunal C and the result is an enabling of output terminals O0-O7 sequentially during the block select enabling period. Of course while the enabling period is for one complete period of the signal (both high and low level) of the pulse at the C
terminal of decoder 74, it will not be enabled again until the appropriate block of signal activates the termunal to which the block direct jumper is connected, that is every fourth block o~ 32 bytes.
With the output terminals O0-O7 sequentially activated, each of NOR gates 78-85 is sequentailly activat~d (assuming latch select jumper 86 is connected to an inhibit voltage level). Accordingly each latch 70 is sequentially enabled, and, when enabled, latches up with the parallel four bit signal applied to its respective input at the particular time it is activated from output leads 69 of decoder 68. As a result silic~n controlled rectifiers Sl-S32 axe activated and renL~in on until latch 70 iL~4~
receives a changed input signal, is enabled, and changes its latch statlls.
Lamps oonnected to terminals ~ -L32 f the silicon controlled rectifiers are thereby caused to operate according to the data on cable 16, at the particular appropriate time.
Other lamp driver circuits operate in a similar manner, ex oept that the block select jumper is connected to a different output termunal of decoder 73. Hence it is activated according to its designated data, and the remaining lamps on the 75 or 90 display board are lit.
It shculd ~e noted that sin oe the appropriate address decoding is performed by counters 71 and 72 and decoder 73, these ccmponents and NAND gates 75, 76, and 77 need not be reproduced in successive boards.
The address decoding terminals Ao~A2 and So-S3 can ke connected to other boards, directly to their correspanding decoders 74. In this case the decoder 74 terminal D of the immediately follcwing display circuit has its jumper oonnected to, for instance, lead Sl, rather than as in the present display circuit, to S0.
It was noted earlier that the input-output peripheral 37 contains a R~M. This R~M is, in the preferred type 4269 a circulating buffer having registers for storing 16 bytes by faur bits each, providing a capacity of 64 bits per register, or 128 bits in total. Figure 10 depicts a layout of the preferred form of storage within the registers, designated as A register and B register. The B register addresses of each four bit byte is shcwn as the left hand oolumn, and the addresses for each our bit byte o the A register is shcwn in the right hand column. A bit stored at each of the locations designated by a square within the A or B register designates that a oorresp~ding lamp designated by the num~er of the storage location in Figure 10 is to be lit. For instance, if column 2 of the bit register having row address 54 contains a binary "1", lamp number 33 is to be lit. Acoordingly the program signals stored within the microcomputer cause a binar~ bit to be stored at location 33 when the crosspoint switch number 33 has been closed and this has been sensed by a scanned pulse on ane of lead So-S7, and has keen receivcd on one of leads Ro-R7 by peripheral -2~-33, also under control of the microcomputer. Upcn sensing of the closure of crosspoint switch 33, a bit is deposited at location 33 in the B register of the RAM sh~n in Figure lO.
When the RAM is read, a bit at location 33 is recognized, and the local light emitting diode display immediately displays numeral 33 in the manner described earlier. In addition, the operation signals of the microcomputer cause the input-output peripheral 37 to output nume~al 33 of the RAM B register on the display terminals Bo~B3, Ao~A3. This signal is changed to serial form within binary to serial multiplexer 49, and is outputted as data at the appropriate time designated by the R~ scan time when the memory location is accessed. This, of course, is in synchronisum with the clock pulses which are applied outputted to the clock lead of cable 15. As described earlier, a reset pulse at the beginning of each second scan cycle is also provided on the reset lead.
The numeral 33 in data signal form appearing at the appropriate time in the RAM scan sequence is decoded in the lamF driver circuit and applied to latches 70. m e clock pulses are decoded as described earlier into an address, and the appropriate latch is enable at the proper time for numeral 33, in 4 bit binary form applied to the input of latches, to activate the gate of a single silicon controlled rectifier, causing operation of a single lamp as descriked earlier.
Ihe operation signals of the microcomputer are adapted to cause numeral 33 to flash on and off, by suc oessively adding and removing it at particular times from the data signal train exiting the peripheral 37 via terminals Bo-B3 and Ao A3. A fuLther number crosspoint being closed causes the operation signals to keep numeral 33 illuminated steadily, and the next crosspoint will cause an illumunated numker to flash, after its number is stored in the RAM at the appropriate location as described.
~hile the abcve described the ~unction of the apparatus to display a nuweral, variations of the above result as the program si~lals are varied; yet the illumination sequence is as cutlined. Accordingly the description below is directed to the operation or program signals portion of the invention which are prooe ssed and translated by the apparatus.
Appendix 1 is comprised of a listing of the mnemonics which constitute the substanoe of the preferred program required for the system, assuming that the components described earlier include the Intel type 4040 microprooessor, from which the machine language program can be written.
The mnemonics are assumed to be well kncwn to a person skilled in the art, and 2 listing thereof and their function as well as their machine language equivalent is available fr~n the aforenoted Intel Corporation. However to aid in understanding of the specific portions of the programs, each group of a distinguishable series of mnemonics are headed by a descriptive title which notes the function of the sequence of mnernonics which follows.
As the titles are clear and are intended to be descriptive of the function of the signals stored which correspond to the mnemonic listing, no furthur description thereof is deemed necessary, since simply following the sequen oe titles will prcvide sufficient ~xplanation to a person skilled in the art to program the m~crocomputer sufficiently to carry out the invention.
For instance, turning to page 5 of the Appendix, the heading STAR~ OF M~IN RDUrINE and the setting up of the mcdes, timer periods, etc.
beco~es clear.
However, to orient the reader further to the functions of the signals provided by the mnernonics, a logic flcw chart from which the sequen oe of the mnemonics was derived will be described by reference to the MAIN
RCUTINE flow chart, Figures 14 and 15 which are to be read together, the MAIN INTERRUPT flow chart, Fig~res 16 and 17 which are placed together, the INrE~RUPT ~WT~ES, in Figure 18, the SYSTEM SUBRfUTINES, Figures 19 and 20 which are placed together, and the PATTERN SUB~CUTINE, in Figures 21 and 22 which are plaoed together.
In respect of the functians perfarmed by the system, as was noted earlier selected switches of the external crosspoint switch matrix are operated in sequence upon the randcm selection OL the numbers carried on ping pong balls contained within a conventional Bingo blower. Onoe a Eerticular selection has been made, the most re oently selected number on the display board is flashed repeatedly, on oe per second preferably, while previous selections remain illuminated. The operation of a digital display adja oent or on the housing of the switch matrix can ke used to accurately time the calling of the selected numbers by the caller. After each timed period is over, the local digital display is caused to flash on and off indicating that another selectian is reqwired. The preferred programmed form of the timer can be speeded up or slcwed down in one second increments.
A special feature of the system provides a pattern display ~Figure 13) which operate to indicate a Bingo pattern to be used for a particular game. The pattern can also be rotated by 90 degrees from whatever is displayed by closing a crosspoint control switch. The system also has the capability to test itself.
Turning now to Figures 14 and 15, the main routine begins by programing the input-output peripheral 37 (described ky refQren oe to its component number 4269) to a predetermined operating mode described in the first block, as is the deccde and display driver 58 (referred to as component type 4265). The main routine in mnemonic form starts on page 5 of AppendiY. 1.
The flow chart then describes the function of the signals required to monitor the crosspoint switch closure addresses generated in the interrupt handler routine. The switch closure can be for a number selection, or for a control function. If the switch closure is for a num~er selection, the routine checks to see if this number has already been selected. If it is a new selection the address is passed back to the interrupt handler routine. If the swi-tch closure is a control switch, it is chec~ed for either a C~EL indication or for a STARr indication.
If the oontrol switch is a CANCE~ indicatiGn, the current selecticr, address is made void ~i.e., an address is given ~ich causes 3~
no computer action) and ~he RAM storage in the input-output peripheral 37 is cleared at that address.
It the switch closure is a "start" control indication, the entire RAM storage in the input-output peripheral 37 is cleared and a void current selection address is set.
Turning now to Figures 16, 17 and 18, the interrupt routine and subroutine flow charts are given. m e interrupt handler begins when a system interrupt is generated upon detection of a switch closure by the input-output peripheral 37O The purpose of this r~utine is to scan the tw~ switch matrix blocks to determine which switch closure has generated the interrupt.
If the real time microcomputer time switch from the clock circuit had generated the interrupt, then the interrupt timer is advanced.
~hen the interrupt timer overflows the following events occur:
` (l) the interrupt timer is reloaded;
(2) the on/off toggle flag is reversed (toggled);
(3) the binary bit which had been stored at the current selecticn address in the input-output peripheral R~M
store is set to a l if the toggle switch is on, and is set to a 0 if the toggle switch is off; and - (4) the system timer is decremented until it reaches a value of 0.
If the interrupt was generated by a numker switch, as opposed to a control switch, the routine ignores this and waits to register it when the real time clock interrupt occurs. A switch closure counter is used during the switch s~anning periods to detect whether there was no switch closure, one switch closure or more than one switch closure. If no switch closures were detected, no action is taken. If more than one switch closures were detected, the nibble of information of the switch closure positicn is set to "void" (i.e. all l's). If one switch closure was detected, the switch closure position is pla oed in various registers as noted bela~. See Figure 11 for a designat.ion of the assignments of the ~4~3Z
scratch memory register in the microprocessor. Also see Pi~re 12 for a designaticn of the storage addressed of the crosspoint switch designations in the first in - first out register in the input-output peripheral 37, which, it will be noted, is grouped into Blocks 1 and 2, each of which is grouped into two segments RDl and RD2.
me switch closure position is placed in the following registers of the microprocessor, for example: the least significant bit of the RDl or RD2 segment is placed in register 8; the first in - first out (fifo) address and block numker is plaoed in register A; and a nibble pattern frcm the fifo address is placed in register 9.
The current selection address is stored in registers 2 and 3 of Bank 0 of the memory, and is stored as a direct register control address for the input-output peripheral 37. me nibble to be written to this address is stored in register 4 of Bank 0.
The interrupt routine implements a real time clock by acknowledging only the interrupt caused by the permanent switch closure at the end of block 2 referred to earlier in the description of the hardware. Any other switch closure will generate an interrupt, but the interrupt routine will im~ediately exit on detecting this. When the permanent switch closure is sensed a register is incremented. When this register reaches zero state (at a frequency of about once every 80mSecs) a full 2 block scan is performed in order to detect if any switch closures have been made. Since each 8 bit row in the 4269 RAM is being cverwritten every 300 microsecs and the "housekeeping" requirements at the start of the interrupt routine are longer than this time, this technique is ~he manner used to ensure that the switch closure data is not destrcyed before being read out. m e 2 block scan is implemented ky monitoring a change of the column 8, row 8 R~M bit from a one to a zero. This indicates that block l has been fully read into the RAM. Block one is now scanned; the timing of this part of the routine is such that the first r~ is read out before it is overwritten with block 2 data. At the end of the block 1 scan, the r~ltine waits for the column 8, rcw 8 RAM bit to chanqe frcm a zero to a one.
me output terminals of the 8 CMOS switches to which input terminals OA-7A are themselves connected to the scanned input terminals Ro~R7 of the input-output peripheral 37. m e output terminals of the CMCS
switches having input terminals OB-7B are individually connected in parallel with the output terminals of the first set of CMOS switches to scanned input terminals Ro~~ of input-output peripheral 37.
It should also be noted that scanning output terminal S7 is connected directly to input terminal 7A of th~ last CM~S switch 38.
m e enable input terminals of the CMOS switches having input terminals OA-7A are connected together to enable lead 40, and the enable input terminals of the CMKS switches having input terminals OB-7B all connected together to enable lead 41.
m e input-output peripheral integrated circuit 37 also has an RS output terminal which is at a high level for the duration of each alternate scan, and is at low level for each alternate scan~ m is output term~nal is connected to the input terminals of a pair of CMOS switches 42 and 43. Ihe output terminals of CMCS switches 42 and 43 are both connected to the input terminals of CMOS switches 44 and 45, one input terminal of which is connected in a circuit path to a -lOV souroe , and the other of which is connected in a circuit path to at 5V source, both through a pair of resistors. With the power supply input of switch 42 connected to -5 volts and the power supply input of switch 43 to -lOV, and both of switches 44 and 45 to ~5V, the resulting operation of the 4 switches when alternately high and low level signal is applied to the input of switches 42 and 43 from the RS terminal is to apply high level signals alternately to enable leads 40 and 41.
Accordingly it will be seen that as a high level signal apFears on lèads So-S7 of the input-output peripheral 37 in sequence, for the entire duration there will be a hi~h level signal appearing on the RS
terminal, which, with the-operation at this time of CMOS switches 43 and 44, eauses a high level signal to appear on enable lead 41. Aecordingly for the present scan period CMOS switches 38 whieh have input terminals OB-7B are enabled.
With no erosspoint being closed, none of the latter CMOS switches will conduct, and there is no scanned input signal applied to terminals Ro-R7 of the input-output peripheral 37. Should one of crosspoints have been closed the high potential level signal appearing on one of the row eonductors of the matrix leads connected to terminals So-S7 at a pæ ticul æ
time during the scanning eyele is transferred to the column eonductor at the erosspoint, and to the input of one of the CMOS switehes having input terminals OB-7B. Sin oe this group of CMOS switches had been enabled via enable lead 41, the high level signal is passed through a corresponding CMCS switeh and is applied to one of the input terminals ~-R7.
During the i~mediately following scanning cyele, the signal level on the RS lead is at low le~el. CMOS switehes 42 and 45 operate to cause the potential on enable lead 40 to rise in level, and the potential on enable lead 41! to drop to 1~7 level. Aeeordingly, the CM06 switehes whieh have input terminals OB-7B are disabled, and CMOS switehes 38 whieh have input terminals OA-7A are now enabled.
Should a erosspoint switeh elosure be deteeted, of eourse it will have no effect during this scanning cyele on the CMCS switches hieh are now disabled. Hcwever, should it eorrespond to a vertical matrix eonduetor which is connected to one of the CMOS switehes which is now enabled, high level signal frcm the appropriate sequentially seanning termunals So-S7 is transferred through the elosed erosspoint to the input of one of the termunals P~0- ~ .
me partieular input output peripheral 37 used in the present embodiment, t~pe 4269, is only capable of storing the switeh elosures of 64 erosspoints, ~i.e., made up by a block matrix of 8 by 8 switches). However the Bingo ga~e utilizes a larger number of erosspoint switches, i.e. 75 or 90 in nl~nber plus control switches. To recognize and sean the remaininq ~7itches, 3~
an additional block of s~"itches comprising a further 8 by 8 matri~ is used.
One switch, of column 8, rcw 8 of the second block is permanently closed.
A system interrupt is generated when this (or any other) switch closure is sensed. With the corresponding switch of column 8, row 8 of the first block of switches, the operation program provides means for detecting when the first or second block of switches has been completely scanned, sin oe the binary bit in the R~M portion of peripheral 37 at the location for column 8, row 8 is caused to change state every time the corresponding switch of the second block of switches is scanned. In this manner the switch closure positions from the two blocks of crosspoint switches are separated. The capabilities of the peripheral 37 is thus extended from 64 crosspoints to 126 (128 less 2). The program for implementation will be described in more detail belcw.
The counting of memory storage locations continues continuously for each successive scanning cycle until the high level input interrupt from the aforeno~ed column 8, rcw 8 crosspoint, or from another crosspoint, is re oe ived. With re oe ption of this interrupt signal, there is a recycling and restarting of the count of me~ory locations from the keginning, which is of ccurse coincident with the keginning of the first of the two scanning cycles. Preferably the interrup-t is set to occur every 5 milliseconds.
The column 8 scanning output terminal S7 is connected through a diode Dl to the input of AND gate 46. The other input of AND gate 46 is connected through a diode Dg to the enable input of CMOS switch 45 which, it will ~e recalled, when activated, causes a high level output signal on enable lead 40. AND gate 46 therefore will be activated at the same time as CMOS switch 38 having input terminal 7A~ that is, when the scanning output termunal S7 is active, as well as enable lead 40 ~hich causes the enabling of the CMOS switches 38 to which input terminals OA-7A are connected. In short, AND gate 46 provides an o~t~ut signal at the same time that terminal ~ on the input-output integrated circuit 37 is operated directly from S7 terminal via its direct connection to termlnal 7A; there is direct coinciden oe with the interrupt signal.
3;Z
~ ne out.~ut ter~nal of ~D gate 46 is connected to the O
terminal of flip flop 47, as well as through an inverter to the P termunal.
The signal at the Q output of flip flop 47, after keing applied to LED
driver 48, is applied to the reset lead of the output cable to display.
As was noted earlier, the input-output peripheral 37 contains a pair of display reglsters which have output terminals Bo~B3 and Ao~A3/
forming an 8 bit parallel bus output. There terminals are connected via the 8 parallel leads of the bus to Do~D7 of a binary to serial multiplexer 49. The output of m~ltiplexer 49 is applied to the input of a line amplifier 48, the output of whi~h is applied to the data lead of the output cable.
m e individual leads of the output bus 7 described earlier ~ -are connected to corresponding terminals of the input-output peripheral 37, a clear mEmory CM RAM O terminal (for the internal RAM of peripheral 37), a sync termunal, data terminals Do-D3, clock inputs 02 and 01~ reset, and common lead INT.
A signal on the CM RAM O lead clears all data signals stored in the memory of the input-output peripheral 37. A signal on the sync lead indicates the beginning of an instruction, i.e., the beginning of a complete - scanning cycle, etc. It is from this lead that a clock signal is develcped for display.
The sync lead is connected through an isolating resistor 50 to the base of transistor 51, to which a base diode 52 is a~nnected to ground.
m e collector output of transistor 51 is connected to the input of a bit binary counter 53, the first count output of which is connected to one input of AND gate 54. Another count output of binary counter 53 is connected to input T of flip flop 55 as well as to inverter 56.
Other count outputs of four bit binary counter 53 are connected to the A and B clock inputs of binary to serial multiplexer 49, and the out-put of inverter 56 is connected to clock input C of multiplexer 46. The particular count output terminals ~hich are connected to the A, B or C
terminals of ~ultiplexer 49 and to flip flop 55 are shcwn for the noted part numbers, and are determlned by the required timung, and should other components than those descri~ed be used, 'heir corlnections are left to the person skilled in the artj It is preferred that the 4 bit binary ccunter be type 7493 available from Fairchild Corporation, and that flip flop 55 should ~e type 7474 available from the same sour oe.
m e Q output of flip flop 55 is connected to the second input of AND gate 54. The output of AND gate 54 is connected to inverter amplifier 57, the output of which is connected to a line amplifier 48, the output of ~hich is applied to the clock lead of cable 15.
m ere should clearly be a large division between the frequency of the sync pulse on the sync lead and the pulses appearing on the clock lead. However, the operation of binary counter 53 pr~ides timing signals to multiplexer 49 to sequen oe the serial format output bits corresponding to the parallel format input bits applied to it, in synchronization with the cloclc pulses derived through AND gate 54.
The binary to serial multiplexer 49 is preferably integrated ~rcuit type 74151 which is available from Fairchild Corporation. Amplifiers 48 are preferably each type 7S49 which are available fram the same sour oe .
The previously listed leads of output bus 7 from mlcrooomputer 1 are also applied to a decoder and display driver 58, which preferably is integrated circuit type 4265, available fram Intel Corporation. The decoder and display driver 58 is adapted to convert data from the data bus leads Do~D3, under control of the clock and synchronization pulses of the 01~ ~2~ and sync leads and to convert the signals into parallel coded signals to ~e applied to the individual segments of a numerical display, such as a light emitting diode (LED) display. The output terminals of the decoder and display driver are shown as Wo-W3~ Xo-X3/ Yo-Y3~ and Z0-Z3.
mese cutput terminals are connected to the input of inverter amplifiers 59 to output leads aM,bM, CM~ dM, aL, bL, CL~ dL, eM~fM~ YM~ / L~ L
gL, and enable. These leads are connected to the individual leads of the correspanding LED seg~ents 60 (forming the most significant digit) and 61 (forming the least significant digit), see Figure 8.
With the ccnnec-tions shown, the signals on the data bus corresponding to the crosspc~nt which had been closed in the eY.ternal switch matrix causes immediate display of the number correspcnding to the crosspoint by the LED display. T~is display is preferably located adjacent the game operator, such as part of the Bingo game table itself.
It should be noted that binary counter 53 and flip flo~ 55 as well as AND gate 54 are connected in a manner such that only 8 clock pulses are generated from the sync lead per output eight digit character.
Each of the scanning output terminals So-S7 of input-output peripheral 37 is connected through a corresponding diode Dl-D8 to a resistor to the base of transistor 61. Accordingly, each scan pulse is passed through transistor 61; its collector output is applied to the reset inputs of counter 53 and flip flop 55. As a result, the scanning pulse train from transistor 61 causes reseting of the counter 53 and flip flop 55, which act as multiplexer address counters, and are accordingly reset. A reset pulse is also generated as described earlier derived from terminal S7 of peripheral 37, through diode Dl, AND gate 46, to the reset lead of the cable 15, which synchronizes the output serial clata to the first character.
m e timing for the reset pulse relative to the signal on the RS output of peripheral 37, the clock pulses and the reset pulses of 'che counter 53 are shown in Figure 9.
As noted earlier, cable 15 leads to the inclicator circuit board, and sin oe it is comprised of only 4 wires, can be both lengt~y and flexed around short radius corners.
Turning now to Figures 6 and 7, the end of cable 15 is sho~
The data,clock, and reset leads are connected individually through small valued resistors 65 to the input of indivldual optical isolators 66. m e return lead of the input of all of the optical isolators are connected together and to the c~n~.on lead of cable 15. At the originating end of cable 15, the c~mon lead is connected to a sour oe of potential,V ~see Figures 4 and 5). Accordingly, as each IED driver amplifier 48 on the Data, Clock and Reset leads is switched on, a circuit is conpleted causing current to pass through the corresponding optical isolator 66. The output transistor within the corresponding isolator is turned on, causing its collector to pull the voltage from a high to a low potential state.
When the amplifier 48 are switched off, open circuiting the aforenoted circuit, the collector voltage goes back to the high state. m e individual output leads of optical isolators 66 are ccnnected to the resistors 166 and to the individual inputs of Schmitt triggers 67.
The function of the optical isolators is to convert the current loop data transfer pulses into voltage pulses, and to provide electrical isolation between the microccmputer system and the light driver electronics.
r~he current loop data transfer preferably uses currents in excess of 20 mA and provides excellent immunity frcm interference and general stray effects. The relatively slow response of the isolator also minimizes cable ringing effects. Electrical isolation is required where the display lights are directly driven from a 115V mains supply. The function of the Schmitt triggers 67 is to reconstruct each pulse into square wave form in order that these pulses reliably operate the following electronic devices.
rrhe output of Schmitt trigger 67 to which the data pulses are applied is connected to a serial-to-parallel decoder 68, which is preferably in the form o~ a 4 bit capacity shift register, such as type 7496 available fro~ Fairchild Corporation.
The output of Schmitt txigger 67 to which the clock pulses are applied is also connected to the clock input of the aforeno-ted shift register 68. Since the shift register has capacity of four bits, every four clock pulses on its output leads 69 contain a four bit binary word.
'rhese ~ords are applied via output leads 69 to the input of latches 70.
Preferably the latches are type 7475, available from Fairchild Corporation.
ach four bit binary word designates one out of four of the latch circuits within ]atches 70 to lock up to an operative level. Each latch circuit is connected through a resistor Rl-R32 to the gate of an individual one of silicon controlled rectifiers Sl-S32. Each siliccn controlled rectifier is connected from a 0 voltage plane through an in-dividual lam~ Ll-L32 (not sha~) to a la~p current supply.
-1~
As each latch requires a 1 out of 4 cperate instruction with each four bit binary w~rd, it i.s necessary to address the particular latch which is to release its information and activate the appropriate silicon controlled rectifier to cause illumination of the appropriate light kulb on the display.
The clock output of Schmitt trigger 67 is applied to the input of counter 71. Gne output of counter 71 is connected to the input of ccunter 72. The outputs of counter 71 and 72 are ccnnected to decoders 73 and 74, both directly and serially through AND gates 75, 76, and 77 as shohn.
me reset signal from the reset lead after passing through its corresponding optical isolator and Schnitt trigger is applied to the reset input of both of counters 71 and 72.
- Decoder 74 decodes the latch addresses for the latches 70;
whereas decoder 73 determunes whether the address is designated for the shown latches.
To provide a full complement of 75 or 90 nu~bers, additional æ
circuits will be connectea to cable 15, ~ic~l circuits are designated ~y a different block designator. me block select jumper connects decoaer 74 to the appropriate output of decoder 73 to ensure that the present display operate circuitry is the one designated for operation. Sin oe the address deccding is established from the clock pulses, the block select jumper merely enables decoder 74 at an appropriate time for each data word received from the cable. It~is preferred that the data signal shculd consist of 128 bits broken into four 32 bit blocks. Block select jumper therefore causes decoder 74 to designate the appropriate address during one block of the four 32 bit blocks in each data w~rd signal.
The outFut leads of decoder 74 are individually connected to one of the inputs of each of respective NOR gates 78-85. The output of each of the NOR gates is individually connected to the enable input of respective corresponding latches 70. It shouLd be noted that there are two ways of addressing latches 70 shcwn. In one case NOR gate 78 addresses its corres-ponding latch, as do the remaining NOR gates address latches 79-85. One input of each of NOR gates 79-85 is individually ccnnected to corresponding individual outputs of deccder 74O m e other inputs of NOR gates 79-85 are connected together and to a sour oe of inhibiting voltage. Each of the latches 78-85 enables its corresponding latch 70 when an appropriate output is obtained from decoder 74.
In the second way of addressing, instead of being connected via the latch select jumFer 86 to a source of inhibiting voltage, the second input of each of the NOR gates 79-85 can be connected to one of a group of 4 leads connected to the output of the Latch to ~hich NOR gate 78 is connected. AccordingLy the data word signal which is decoded by decoder 68 appears at the output of latch 70 to which NOR gate 78 is ccnnected determines the time at which the remaining NOR gates 79-85 are enabled.
Accordingly there is a substantial expansion of the capability of the apparatus to respond to the data signal, which is in effect an increasing of the effective data storage of the input-output peripheral 37.
Wi~h the latch select jumper 86 connected to any of the four 3~
outputs of the latch 70 to which NOR gate 78 is connected, NOR gate 78 is first activated with a particular word signal decoded in decoder 68. Latch 70 performs decoding, causing, for instance, one of its output terminals to be at the proper operate level for one of the input leads of NOR gates 79-85. A second address is thus formed and not only is an address of c~ecoder 74 required to activate one of NOR gates 79-85, but also an address resulting from the four bit binary word decoded via latch 70 which is activated through NOR gate 78. Sucoe ssive four bit binary words can there-fore be used to activate various latches in suc oession as a result of an effective expansion of the addressing.
The lamp driver circuit board which is to respond to the data of the four 32 bit blocks in the 128 bit da~a stream is deter~uned by the block select jumper 87 connected to the appropriate output on decoder 73, as described earlier. Each lamp driver board has its block select jumper connected to a different output terminal of decoder 73.
In a Bingo game which utilizes either 75 or 90 numbers, it should be noted that three of the circuits just described are used, although there is capacity for four. In a three lamp-driver circuit system, there is capability for 3 x 32 96 lamps. In a 90 number system, 90 of the 96 lamps are used to illuminate the nurnbers; the rer~aining six can rernain disccnnected ~distributed as two silicon controlled rectifiers not connected per lamp driver board, preferably), or they can be used to illuminate des_gnator ~rds other than the numbers, such as whether the game is normal, a special etc. In a 75 number system, there can be 30 siliccn controlled rectifier lamp drivers cperated on two lamp driver circuit boards, and 15 on a third.
In operation, data signals are received from the data lead of cable 15 and are translated in the corresponding optical isolator 66. The output is restored to proper pulse fo~m with a short enouoh rise time to reliably operate the following logic, in Schmitt trigger 67. The serial data is converted by decoder 68 to four bit words ~lich appear on output leads 6g. The decoder 68, being a shift register, is operated frcm the clock pulses ~hich are received from the clock lead passed through Schnitt trigger 67 in a similar manner as the data signals. The four bit words whlch are designated for the present lanp driver circuit appear as a sequence of 8 four bit bytes comprising a 32 bit block of data, while binary data designated for other lamp driver boards for illuminating the same display are contained in successive four bit, eight byte data signals which follow in three suc oe ssive blocks.
At the beginning of eachl28 bit block of data, a reset pulse is present on the reset lead. After ~eing translated by the corresponding optical isolator 66 and Schmitt trigger 67, the reset pulse is applied to counters 71 and 72 which drive decoders 73 and 74. As a result an output signal ap~ears on one of the four outputs of decoder 73, which enables decoder 74 as a result of its block select jumper being connected to one of the four decoder 73 output terminals. Since counters 71 and 72 have the clock pulses as inputs, and the outputs thereof are also connected to decoder 74, decoder 74 is enabled at an input terminal A at the clock pulse fr~quency, at an input terminal B by 1/2 the clock frequency, and an input terminal C at V4 the clock frequency. m e block select enables the decoder 74 at 1/2 frequency of the signal at termunal C and the result is an enabling of output terminals O0-O7 sequentially during the block select enabling period. Of course while the enabling period is for one complete period of the signal (both high and low level) of the pulse at the C
terminal of decoder 74, it will not be enabled again until the appropriate block of signal activates the termunal to which the block direct jumper is connected, that is every fourth block o~ 32 bytes.
With the output terminals O0-O7 sequentially activated, each of NOR gates 78-85 is sequentailly activat~d (assuming latch select jumper 86 is connected to an inhibit voltage level). Accordingly each latch 70 is sequentially enabled, and, when enabled, latches up with the parallel four bit signal applied to its respective input at the particular time it is activated from output leads 69 of decoder 68. As a result silic~n controlled rectifiers Sl-S32 axe activated and renL~in on until latch 70 iL~4~
receives a changed input signal, is enabled, and changes its latch statlls.
Lamps oonnected to terminals ~ -L32 f the silicon controlled rectifiers are thereby caused to operate according to the data on cable 16, at the particular appropriate time.
Other lamp driver circuits operate in a similar manner, ex oept that the block select jumper is connected to a different output termunal of decoder 73. Hence it is activated according to its designated data, and the remaining lamps on the 75 or 90 display board are lit.
It shculd ~e noted that sin oe the appropriate address decoding is performed by counters 71 and 72 and decoder 73, these ccmponents and NAND gates 75, 76, and 77 need not be reproduced in successive boards.
The address decoding terminals Ao~A2 and So-S3 can ke connected to other boards, directly to their correspanding decoders 74. In this case the decoder 74 terminal D of the immediately follcwing display circuit has its jumper oonnected to, for instance, lead Sl, rather than as in the present display circuit, to S0.
It was noted earlier that the input-output peripheral 37 contains a R~M. This R~M is, in the preferred type 4269 a circulating buffer having registers for storing 16 bytes by faur bits each, providing a capacity of 64 bits per register, or 128 bits in total. Figure 10 depicts a layout of the preferred form of storage within the registers, designated as A register and B register. The B register addresses of each four bit byte is shcwn as the left hand oolumn, and the addresses for each our bit byte o the A register is shcwn in the right hand column. A bit stored at each of the locations designated by a square within the A or B register designates that a oorresp~ding lamp designated by the num~er of the storage location in Figure 10 is to be lit. For instance, if column 2 of the bit register having row address 54 contains a binary "1", lamp number 33 is to be lit. Acoordingly the program signals stored within the microcomputer cause a binar~ bit to be stored at location 33 when the crosspoint switch number 33 has been closed and this has been sensed by a scanned pulse on ane of lead So-S7, and has keen receivcd on one of leads Ro-R7 by peripheral -2~-33, also under control of the microcomputer. Upcn sensing of the closure of crosspoint switch 33, a bit is deposited at location 33 in the B register of the RAM sh~n in Figure lO.
When the RAM is read, a bit at location 33 is recognized, and the local light emitting diode display immediately displays numeral 33 in the manner described earlier. In addition, the operation signals of the microcomputer cause the input-output peripheral 37 to output nume~al 33 of the RAM B register on the display terminals Bo~B3, Ao~A3. This signal is changed to serial form within binary to serial multiplexer 49, and is outputted as data at the appropriate time designated by the R~ scan time when the memory location is accessed. This, of course, is in synchronisum with the clock pulses which are applied outputted to the clock lead of cable 15. As described earlier, a reset pulse at the beginning of each second scan cycle is also provided on the reset lead.
The numeral 33 in data signal form appearing at the appropriate time in the RAM scan sequence is decoded in the lamF driver circuit and applied to latches 70. m e clock pulses are decoded as described earlier into an address, and the appropriate latch is enable at the proper time for numeral 33, in 4 bit binary form applied to the input of latches, to activate the gate of a single silicon controlled rectifier, causing operation of a single lamp as descriked earlier.
Ihe operation signals of the microcomputer are adapted to cause numeral 33 to flash on and off, by suc oessively adding and removing it at particular times from the data signal train exiting the peripheral 37 via terminals Bo-B3 and Ao A3. A fuLther number crosspoint being closed causes the operation signals to keep numeral 33 illuminated steadily, and the next crosspoint will cause an illumunated numker to flash, after its number is stored in the RAM at the appropriate location as described.
~hile the abcve described the ~unction of the apparatus to display a nuweral, variations of the above result as the program si~lals are varied; yet the illumination sequence is as cutlined. Accordingly the description below is directed to the operation or program signals portion of the invention which are prooe ssed and translated by the apparatus.
Appendix 1 is comprised of a listing of the mnemonics which constitute the substanoe of the preferred program required for the system, assuming that the components described earlier include the Intel type 4040 microprooessor, from which the machine language program can be written.
The mnemonics are assumed to be well kncwn to a person skilled in the art, and 2 listing thereof and their function as well as their machine language equivalent is available fr~n the aforenoted Intel Corporation. However to aid in understanding of the specific portions of the programs, each group of a distinguishable series of mnemonics are headed by a descriptive title which notes the function of the sequence of mnernonics which follows.
As the titles are clear and are intended to be descriptive of the function of the signals stored which correspond to the mnemonic listing, no furthur description thereof is deemed necessary, since simply following the sequen oe titles will prcvide sufficient ~xplanation to a person skilled in the art to program the m~crocomputer sufficiently to carry out the invention.
For instance, turning to page 5 of the Appendix, the heading STAR~ OF M~IN RDUrINE and the setting up of the mcdes, timer periods, etc.
beco~es clear.
However, to orient the reader further to the functions of the signals provided by the mnernonics, a logic flcw chart from which the sequen oe of the mnemonics was derived will be described by reference to the MAIN
RCUTINE flow chart, Figures 14 and 15 which are to be read together, the MAIN INTERRUPT flow chart, Fig~res 16 and 17 which are placed together, the INrE~RUPT ~WT~ES, in Figure 18, the SYSTEM SUBRfUTINES, Figures 19 and 20 which are placed together, and the PATTERN SUB~CUTINE, in Figures 21 and 22 which are plaoed together.
In respect of the functians perfarmed by the system, as was noted earlier selected switches of the external crosspoint switch matrix are operated in sequence upon the randcm selection OL the numbers carried on ping pong balls contained within a conventional Bingo blower. Onoe a Eerticular selection has been made, the most re oently selected number on the display board is flashed repeatedly, on oe per second preferably, while previous selections remain illuminated. The operation of a digital display adja oent or on the housing of the switch matrix can ke used to accurately time the calling of the selected numbers by the caller. After each timed period is over, the local digital display is caused to flash on and off indicating that another selectian is reqwired. The preferred programmed form of the timer can be speeded up or slcwed down in one second increments.
A special feature of the system provides a pattern display ~Figure 13) which operate to indicate a Bingo pattern to be used for a particular game. The pattern can also be rotated by 90 degrees from whatever is displayed by closing a crosspoint control switch. The system also has the capability to test itself.
Turning now to Figures 14 and 15, the main routine begins by programing the input-output peripheral 37 (described ky refQren oe to its component number 4269) to a predetermined operating mode described in the first block, as is the deccde and display driver 58 (referred to as component type 4265). The main routine in mnemonic form starts on page 5 of AppendiY. 1.
The flow chart then describes the function of the signals required to monitor the crosspoint switch closure addresses generated in the interrupt handler routine. The switch closure can be for a number selection, or for a control function. If the switch closure is for a num~er selection, the routine checks to see if this number has already been selected. If it is a new selection the address is passed back to the interrupt handler routine. If the swi-tch closure is a control switch, it is chec~ed for either a C~EL indication or for a STARr indication.
If the oontrol switch is a CANCE~ indicatiGn, the current selecticr, address is made void ~i.e., an address is given ~ich causes 3~
no computer action) and ~he RAM storage in the input-output peripheral 37 is cleared at that address.
It the switch closure is a "start" control indication, the entire RAM storage in the input-output peripheral 37 is cleared and a void current selection address is set.
Turning now to Figures 16, 17 and 18, the interrupt routine and subroutine flow charts are given. m e interrupt handler begins when a system interrupt is generated upon detection of a switch closure by the input-output peripheral 37O The purpose of this r~utine is to scan the tw~ switch matrix blocks to determine which switch closure has generated the interrupt.
If the real time microcomputer time switch from the clock circuit had generated the interrupt, then the interrupt timer is advanced.
~hen the interrupt timer overflows the following events occur:
` (l) the interrupt timer is reloaded;
(2) the on/off toggle flag is reversed (toggled);
(3) the binary bit which had been stored at the current selecticn address in the input-output peripheral R~M
store is set to a l if the toggle switch is on, and is set to a 0 if the toggle switch is off; and - (4) the system timer is decremented until it reaches a value of 0.
If the interrupt was generated by a numker switch, as opposed to a control switch, the routine ignores this and waits to register it when the real time clock interrupt occurs. A switch closure counter is used during the switch s~anning periods to detect whether there was no switch closure, one switch closure or more than one switch closure. If no switch closures were detected, no action is taken. If more than one switch closures were detected, the nibble of information of the switch closure positicn is set to "void" (i.e. all l's). If one switch closure was detected, the switch closure position is pla oed in various registers as noted bela~. See Figure 11 for a designat.ion of the assignments of the ~4~3Z
scratch memory register in the microprocessor. Also see Pi~re 12 for a designaticn of the storage addressed of the crosspoint switch designations in the first in - first out register in the input-output peripheral 37, which, it will be noted, is grouped into Blocks 1 and 2, each of which is grouped into two segments RDl and RD2.
me switch closure position is placed in the following registers of the microprocessor, for example: the least significant bit of the RDl or RD2 segment is placed in register 8; the first in - first out (fifo) address and block numker is plaoed in register A; and a nibble pattern frcm the fifo address is placed in register 9.
The current selection address is stored in registers 2 and 3 of Bank 0 of the memory, and is stored as a direct register control address for the input-output peripheral 37. me nibble to be written to this address is stored in register 4 of Bank 0.
The interrupt routine implements a real time clock by acknowledging only the interrupt caused by the permanent switch closure at the end of block 2 referred to earlier in the description of the hardware. Any other switch closure will generate an interrupt, but the interrupt routine will im~ediately exit on detecting this. When the permanent switch closure is sensed a register is incremented. When this register reaches zero state (at a frequency of about once every 80mSecs) a full 2 block scan is performed in order to detect if any switch closures have been made. Since each 8 bit row in the 4269 RAM is being cverwritten every 300 microsecs and the "housekeeping" requirements at the start of the interrupt routine are longer than this time, this technique is ~he manner used to ensure that the switch closure data is not destrcyed before being read out. m e 2 block scan is implemented ky monitoring a change of the column 8, row 8 R~M bit from a one to a zero. This indicates that block l has been fully read into the RAM. Block one is now scanned; the timing of this part of the routine is such that the first r~ is read out before it is overwritten with block 2 data. At the end of the block 1 scan, the r~ltine waits for the column 8, rcw 8 RAM bit to chanqe frcm a zero to a one.
4~3;2 This indicates that bloc}; 2 has been ccmpletely ~.~it~en into the P~, and this is now scanned. A scan counter is used to detect for zero, single or multiple switch closures.
The extension memory part of this inteirupt handler rcutine examunes the system timer, and if the timer is 0, turns the digital display on for a toggle flag "on" indication and turns the digital display off for a toggle flag "off" indication. The system timer is reloaded when a new switch clo Æ e is detected (see Figure 15).
A flow chart describing the system subroutine is found in Figures 19 and 20~ m e purpose of these routines is to extend the cperation of the system to interface the digital display. The functions of the sub-routine are as follows:
(1) to convert the current selection address to a BCD ccde, to add displacements for the skipped positions and generate the appropriate 7 segment code which is written to the decoder and display driver 58, (2) to check for cperation of TEST, SLoW or FST, after closure of an appropriate crossFoint control switch, and to take appropriate action as follcws:
(i) TEST: starting at position 0, sequentially illuminate the display numkers up to the highest number, i.e. 75 or 90.
The local digital display also is caused to follcw the numker sequence. At the end of the sequence, the pro oe ss is repeated after 5 seconds and clearing of the lamps. The START crosspoint switch is continually monitored and upcn closure the test sequence is halted and the start prooedure is follcwed.
(ii) S~CW: Increment the Fermanent system timer to a maximum value of 15 seconds. When the value is loaded into the system timer register, the digital display takes one mor~ seccnd from the time of switch closure to the on/off flashing sequence for each increment.
(iii~ FST: ~ecrement the Fer~nent system timer. miS
speeds up the tImer by one second~ The minimL~ value of ~his timer is one second.
m e pattern subroutine flow chart is shown in Figures 21 and 22.
These routines are only concerned with the display pattern generator, which is shcwn with referen oe to a 75 number system, due to the limitations of the system capacity as described.
m e patterns are stored in an extension memory, and are ac oe ssed as five stored bytes per pattern. m e pattern switch closures are either a requested pattern or one of two pattern control switches: "RDTATE PATTERN"
and "TEST PATTERN".
If a pattern is requested, the starting address of the first byte is calculatea, and the five bytes are transferred frc~ the extension memory to the last 32 byte block of the RAM storage of the input-output peripheral 37.
Should this option be utilized, a separate pattern light display is utilizea, which is separated into quadrants shcwn in Figure 13.
Groups of lamps within each quadrant are illuminated to display a pattern, which will be ~he pattern of the numbers to be p]ayed by the players of the game.
The light connection diagram is given numerically in Figure 13.
Each quadrant of the bcard can be considered to be in contingucus 6 byte segments of the ccnnec~ed 5 byte pattern. If the pattern is rotated six bytes, then this has the effect of rotating the pattern board ~y 90 degrees.
The six byte rotation is performed in the ROTATE pattern routine.
The TEST PATTERN control switch causes three patterns to be applied to the display board in rapid sequen oe. The process is repeated until a STARr switch closure is detected, at which time an interrupt is generated and the systems operate as on the main routine flow chart described earlier.
m e system can be given the capability to s~bstitute a ranclom nun~er instead of requiring manual selection of a number using the previously noted crosspoint matrix. The randcm num~er generator can be -31~
in~l~ner~ted ky the ~icrcY ~put~r on the ~asis of direc~i~ fra~ stor~d control signals comprisi~g a program.
A mcdulo 16 feedback shift register is implemented, as shcwn in Figure 23. Each shift pcsition is numbered or lettered in sequen oe . An additional function is pr~Jided frcm positions 14 and 15 in position 16, (lakelled 216) which has been found to give ex oe llent randomness of the result. A program to obtain the randcm number in ~n Intel Corporation 4004 microccmputer is as follGws.
Mnemonic Function SHF, ~ 6P ~5 / FE~CH 125 TO REGISTER PAIR 6 SRC 6P / SET UP R~M1J REG 3 ~ CHAR D
RDM / GET CHhR D TO ACC.
INC 13 / INCREI~:NT REGISTER 13 SRC 6P . / SET UP CHAR E
.1 , , . _ .
. .
CLC / CI~EAR CARRY
ADM / MODUI,O 16 ADDITION OF CHARACTERS D & E
XCH ~ / EXC~IANGE ACGUMULATOR WITH RE:GISTER 3 FIM 6P 112 J FETCH 112 TO REGISTER PA:I:R 6 SRC 6P / SEND OUT NEXT SHIFT REGISTER AI~DRESS
RDM / GET SH~ REGISTER CHARACTER
XCH j / EXCHANGE ACCUMULATOR WITH REGISTER 3 l~lRM / WRITE IN PREYIOUS DATA
ISZ 13 *-4 / MOVE UP SHIFT REGISTER
XCH 2 / EXCHANGE ACCUMUI~TOR WITH REGISTER 2 BBL O / RETURN FROM SHP~, RESUL~ IN REGISTER PA~
m e subrcutine uses register 3 m data R~M #1 of the 4004 system.
The register has to be initialized with a pattern other than all zeros.
The simplest initialization pattern is to write the character address in as the shift register character itself.
FIM 4P 112 / F~TCH 112 TO RE~ISTER PAIR 4 SRC 4P / SET UP RAIN 1, PIEG 3, CHAR O
~D 9 ~ TRANS~ER REGISTER 9 TO ACCUMU ~ TOR
~RM / WRITE THIS VALUE IN R ~
ISZ 9 *-3 / LOOP AROUND ALL C-~ARACTERS
It is believed clear that the present system introdu oe s substantial flexibility in the structure and operation of a Bingo type game.
Due to the use of a microprocessor, there is substantial flexibility and thereby improved oFeration afforded the yame operator. Prior to ccmmenoement of the game the system can be fully tested at the touch of a buttQn, whereby all lamps are sequentially illuminated. m e pattern of the testing is such as to convey a visually exciting display, thus increasing the enjcyment of the players.
Once a numker has been called it is displayed to the game operator, and also upon his selection is displayed on the large display board. The most re oently selected number flashes, thus providing instant recognizability to players who may not have been devoting their fullest attentian to the last called number, thus removing the requirement for them to check all numbers an the display board to find out which had been called last. This obviously reduces player fatigue.
Internal timing, which is varia~le at the selection of an cperator, provides a flashing mode to his local digital display to indicate when the next number should be called. Sin oe the timer accurately paces the game, player restlessness is decreased. Further, upan the designation of a w~nning game, a "starburst" or other pattern can be displayed ~n the n~mber display, generally enhancing the excitement of the winning call.
Yet, in the case of an erroneous winning call, the previous display c~n be recalled from memory and displayed for the audience whereupon the game can cGntinueS
3;2 In addition,'~a pattern display can be provided to the audienoe to show the required winning numerical pattern required for sFecial or 7'jackpot" games.
In addition to the aforenoted operation advancements, the present invention allows such structural advantages as the use of more than one display board connected in parallel with others and disp~sed at various locations around the game room. m is is particularly an aid in large Bingo halls, particularly in those which are irregularly shaped. Furth2r-more, the display boards can be located at great distan oes from the main operation console with significantly increased reliability due to the xequirement now of only a four wire cable, rather than the 76 or greater wire cable pr2viously required. The substantially narrower cable can therefore be hidden and can follow a more convenient route around the rcon than heretofore.
It ~ay bec3me obvious to a person skilled in the art under-standing this invention that other modifications and embodiments than those described above can be provided. All are oonsidered within the scope and sphere of the invention as defined in the appended claims.
* AUTO MCB 3 PAGE SYSTEM
* START OF PAGE ZERO
= 000 NOP
JUN STR
*
INTERRUPT ROUTINE
*
* FIP~ST SAYE MAIN ROUTINE STATUS
*
INT SBl ~ .
LCR
RAL
*
* NOW iSTAART INTERRUPT ~ANDLER
*
CI~ECK FOR END OF BLOCK 2 ~ .
~qS CAD
RDl RAL
*
* IF BLOCK 2 END, INCREMENT " OUNTER
* AND CHECK FOR SCAN TRIGGER
*
- * Cl~ MENCE: SCAN AFTER WAITING FOR
* END OF BL9CK 1 *
INl RDl RAL
J"N 2 INl *
* CXE:CK FOR TRIGGER BEFORE SCAN
*
*
* SCAN BLOCK 1 *
FIRST CLEAR SWITCH CLOSURE COUNTER
*
,i .
LDM O
* NOW SCAN
JMS BLK
*
* NEXT SCAN Bl.OCK 2 * FIRST WAIT FOR END OF BLOCK 2 JI~IS CAI~
IN3 RDl RAL
* NOW SCAN
JMS BLK
END OF BI,OCK SCANS
*
CHECK SWITCH Cl,OSURES
*
* KBP, JUMP IF NO SWITCH CI,OSURES
*
LDM F
X~H 9 JUN ENl *
JUMP IF SINGLE SWITCH CLOSURE
*
SET NI:BBhE FLAG
RAR
XC~ 9 JUN ENl *
* SET BLOC~ FLAG FOR SINGLE SWITCH CLO~;URE
XC~
XCH A
INCREMi~:M~ INTERRUPT TIMER LOw ORDER NIBBhE
* TO TAKE ACCOUNT OF TIME TO SERVICE INTERRUPT
,. *
3~
E~l IliC 3 * CHECK HIGH ORDER hIBBI~: I
*
*
* R2~0AD INTERRUPT TIMER AND
SERVICE SYSTE~ TIMER
LOD D
LOD C
*
* HAYE TO CHECK FOR ON TOGGT~ - FIRST
S:~39 RAI.
*
DAC
,JUMP TO EXTENSION MEMORY
JMS IEX
* ~LASH CURRENT SELECTION
SRC lP
SBl I,OD 5 CMA
*
I,OD 8 RAL
~N7 IN8 ~hqP
*
TOGGLE ON/OFF FLAGr *
IiY9 XCH 8 RAL
CMC
`~ RAR
XC~
*
J
* ~I~AP UP
f ~
EN2 J~3 CAD
XC~ 6 RAR
DCL
BBS
* SUBROUTINE TO S~T UP CONTROL
SRC OP
BB~ O
* SUBROUTINE TO SCAN A ~LOCK
~ OF 8 X 7 SWITCHES
CI,C
RAL
". BLl SRC QP
SAMPIE LO'~ ORDER NIBBIE
SKIP IF NO CLOSURE
JMS l~qOI`~
* SAMPLE HIGH ORDER NIBBIE
~L2 RDl *
SKIP IF NO CLOSU~E
LDM O
JMS MON
* INCREr~NT RO~ ADDRESS AND
* CHECK FOR COl'~PIETION
*
3a ~ !
~ " ~
~L~ l IiYC 1 IOD~ 1 . i IAC
IAC
JCN C BLl *
BBL O
*
MONITOR ROUTINE FOR SWITCH C~OSURES
*
*
* MASK OUT RDl/RD~ FLAG
*
I.OD 8 RAR
CLC
RAL
* . I
* NOW PUT IN CURRENT STATUS
* . I
0~?5 - . XCH 8 '.
LOI) 1 XCH A
* CHAI`JGE SWITCH CLOSURE COUNTER STATUS
~N2 LOD 9 KBP
RAL
Lt:)D 7 STC
RAI, RAL
XC~ 7 *
BBL O
*
* START OF l~iAIN ROUTINF
*
* FIRST SET UP 42~9 TO ~01I.Ol,~ING STATU~
#
* INDIVIDUAL SCANNED DISPh~Y: 16 DIGITS
* ON A & B RE~ISTERS.
I
~9 SCAI;5i~) S~ CH SE.~SO?~ ri'lr.T.~IX
*
S RC OP
LDM O
tlR O
'~JR 1 * SET U~! 4265 TO OUTPUT MODE
SRC OP
W~P
SET INT~RRUPT TIMER TO 0. 5 SECONDS
SET SYSTEM TI~IER TO 10 SECONDS
*
IDM A
XCH B
*
* SET CUP~RENT SELECTION TO IN~IIBIT
*
FTM lP CO
*
* ENAi3IE INTERRUPTS AND START CHECKING INITIAI.
* VALID ADDRESS
t * FIRST CHECK VALID A~DD~2SS
*
COM DIN
l,OD 9 EIN
IAC
JCN 4 C 01!5 *
TURN OFF INTERRUPTS
*
DIN
JUMP TO EXTENSION MEMORY
*
JMS CSW
~r D
L4~
CilECK YOR Chi`iCLL Ci~ STA.D.T
CM7 LDr,l 3 C~C
ADI~ A
CM9 LOD 8 , I
RAR
LOI) 7 RAL
RAL
*
* RESTART GAI~ CLEAR 4269 *
SRC OP ~-LDM O
WRl FIM lP CO
*
* TURN ON INTERRUPTS AND BACK TO START.
*
EIN
*
- JUN C OM
CHECK CANCEL
C;.16 LOD 7 RAI, CANCEL CURRENT SELECTI ON
* FIRST WAIT FO~ TOGGLE OFF
EIN
R Al, FIM lP CO
*
JUN C OM
* GET C ONTENTS OF ADDRESS
FIRST G T Al:)D.~ESS
C~il4 LOD A
XCH l l I
~1 ,, RAR
I~DI~I 2 RAL I r XCH O
* TURN ON I i`lTERRUPTS
EIN
RAL
JCN A T ON
SRC OP
CHECK I~ ALREADY WRITTEN TO, i JCN 4 C Ohq * ~ ., WRITE NEW SELECTI ON
I,OD O
.
* JUMP TO ~XTE~ISION MEMORY
~lS BIN
* ! - i REWRITE~ SYSTEM TIMER
XCI~ 6 JUI~ ~O~
*
*
.
- ~t 2 4~;3Z
*~li**~*~***~*~****~*~*****~ t PA~ 1 JUIl~;P ADD2~SS
- 10() *.
~ WRITE TO DI~PLAY
* ROUTINE TO GET THE BCD VALUE OF 426 * ADDRESS IN BANK O REGISTER PAIR 7 ~ FIND BINARY NUMBER FROM NIBBIE PATTERN
BIN . LOD 7 KBP !-XCH F
* ADD 4 IF NECESSARY
LOD O
LD~ 4 ADD F
XCX F
*
* ADD 8 IF NECESSARY
CLC
R~ . j XC~ E
C~C I
LDM 8 i-ADD F
- XCH F
* PR~VENT WRITING IF CONTRO~ SWITCH
~BL l * CORRECT FOR DISPLACEI'~ENTS
LOD F
SUB F
XCH F
CMC
LDM O
XC~ ~
SUB E
XC~ ~:
*
* LEAYE ~ 3 ~ ~ ~1Lr~3Z t . ,. - - ~ ,j,, ;
* ROUTIN~ TO CON'JERT 7P ~ AR'l TO ~CD ~D T ~AYE R2SULT IIY 7 BCI:I CLB
XC}~ E
LD~I A
XCH F
* i3CD COUNTER IN REG. ~:, MSD IN REG. 5, A IN REG. F & LSD IN ACCUMULATOR
* NOW SUBTRACT A FROM LSD
BC3 Sl1~ F
* CHECK FOR ~302ROW
DAC
XC}I 5 * LSD IN AGC,, MSD-l IN REG. 5 13Cl JCN A BC2 3UMP IF ANSWER FOUNl:l INC E
CLC
.JUN BC3 * ADD BACK 10, PUT LSD IN REG " F AN~ EXIT
XCH F
* ROUTINE TO WRITE 7 SEGMENT CODE TO
* DISPI,AY, BCD IN 7P
WP~T FIM OP 80 S~C OP
*
* 4265 ADDP~ESSED, NOW GET COI)E TO REG, PAIR O
* FIRST C~ECK FOR I.EADING ZERO
FIM OP O O
LOD E
JCN 4 WTl LDM F
X~X O
CLC
ADD E
XC~ 1 ~4 CG;~., hDD,~s S I;~ OB, NO~ v.,T C03E
FIN OP
* ~JRITE COD~ TO MS~
*
IfT1 LOD 1 WRO
~JR2 * SAI'~E PROCEDURE FOR LSD
WT3 ~DM F
XCH O
CLC
LDM 6 t ADD F
FIN OP
*
I,OD 1 .:
WRl LOD O
~ .
:BBL O
* CHECK FOR GONTROL S~'1ITCH
* (SLOW, FAST OR TEST) *
CS'~ LDM 3 ADD A
JCN 4 CSl *
* JUMP TO EXTENSION MEMORY 2 *
CS2 JUN CSX (for 1 page memory exten~ion CSl LOD 8 this becomes CS2 BBL O
*
RAR
.~ .
RAR
*
I.OD 7 RAL
*
* I~:ST ROUTINE
_~ ~r ~a~L~ I
* PUI' ST~.RTIi~lu NUr~B2R IN s~r Ai~i:l?.ESS
hN~ ~CD C()i~ IN 7P
*
TST FIM lP 50 L[~r.~ 1 FIM 7P ~1 !
SPEED UP TIMER
*
START TEST LOOP
EIN
*
* FIRST STOP SYSTEM TIhiER FLAG
*
TSl LDM E' WRITE OUT TO DISPIAY
JMS WRT
*
* TURN ON DISPLAY
*
LDM F
JMS BSR
*
* WAIT FOR TRANSITION FROM TOGGIE OFF TO
* TOGGLE ON, THIS ESTABLISHES THAT THE
* PREVI OUS DATA WAS WRITTEN
*
RAL
T~;2 LOD 8 RAL
*
* UPDATE BCD DATA
*
CT~3 XCH F .
IAC
DAA
XCH F
ADD E
XCH E
*
* UPOATE NIB:3LE I
~ I
TS7 Cl.C
I~OD 4 RAI.
*
Lr ~; i C.~2CK FOR OVE~.FLO,1 * OVER~LO~ ROUTINE
FIRST ROTATE NIBBIE AGAIN
R~L
*
* NOW CHANGE NIBBLE OF SRC ADDRESS
RAR
CMC
* C~ECK IF NOW 5 IN MS NIB~IE
JC~ A TS5 INCREMENT LS NIBBLE
* PUT BACK REG. 2 * PUT BACK NIB31E
TS~ XCH 4 * CORRECT FOR DISPLACEMENT IF NECESSARY
* CORRECTION NOT REQUIRED IF MS SRC = 5 RAR
* CORRECTION NOT REQUIRED IF SRC OF LS EVEN
RAR
* CORR~.CTION NOT REQUIRED IF NIBBLE PATTERN
* IS NOT IN MOST SIGNIFICANT P~C~-LOD
RA~
* CORRECT FOR DISPLhCEMENT BY GOXNG
* TO NEXT ADD~ESS
~7 , ,, ., ~
JUN TS?
* CHECK IF FINIS~;D (76 IN BCO) (91 for 5C~
number system) * FIRST CHECK FOR START SWITCH
TS6 ~OD 9 IAC
RAL
RAL
TS9 1.13M 9 (J,DM 7 for 90 number system) CLC
ADD E
LDM 9 ( LOD F f or 90 number sy3tem ) ADD F ~DAC " " " "
* SLOW DOWN INTERRUPT TIMER
* SET SYSTEM TIM2R AND WAIT FOR ZERO COUNT
(~ LDM 5 *
RESET AND BACK TO BEGI~YNING
JUN TF~
*
ROUTINE ~0 SP~:ED IJP TIM~:R
*
DAC
XCH B
JUN REL
*
* ROUTINE TO SLO~ DOl,~IN TI~R
*
SLW LOD B
IAC
XCH B
*
~- * ROUTIN:E TO WAIT FOR RELEASE OF
* CURRENT CONTROL S~IITCH
~8 z RE1 DIil I.OD 9 IAC
EIN
JCIY C REL
DIN
JllN C 0 ,~,, .
INTERRUPT EXTENSI ON, CHECK FOR TOGGIE
OFF AND ZERO SYSTEM TI~IER. IF TRUE
* l~{EN CANCEL DISPLAY
~IRST CANCEL DISPLAY IF VOID ADDR~SS
~ .
- RAL
LDM E
JCN C IXl RAII
I~M E
JCN A BSR
IXl LDM F
ROUTINE TO WRITE ACC, TO BIT SET/RESET
SRC OP
S~C
WRM
B~L O
FINISH OFF TEST ROUTINE
TFN SRC OP
LDM O
WP~1 JUN TST
TND ~IM lP CO
* JUST PUT IN YOID ADDRESS~, NCW RESET TIiæR
TN1 :FIM 6P A5 * RESET 4269 AND LEAVE
JIJN RST
~9 ' 7 S~;ii2NT CGDr FOR DISPIRY
= lF6 HE~ 3F
HEX o6 HEX 66 i, *
~*********~****~********~**~*~**~****~**~*~*
': *
*
* CHECK CONTROL S',11ITCHES FOR
* PATTERN GENERATOR
* CHEC~ FOR PATTER~ CONTROL, * JUII~P TO APPROPRIATE CODE IF C02RECT
CHECK. OTHERWISE RETURN TO PAG~ 1 *
CSX LD~I 3 CI~
ADD A
JCN 4 SXl IAC
IAC
IAC
XND BBL O
*
SXl LOD 8 RAR
JCN A XND
RAR
RAR
JCN A XND
* ROUTINE TO DYNAMIChLL~ TEST
* PATTERN BûX
* FIR~T SP~.ED UP TIifir.R
T~ FI~I 6P F5 EIN
JMS TCK
FIM OP AC
Ji~ T~
JMS TC~
JUN TPT
* ROUTINE TO CXE5K FOR NEXT PATTERN
~ TRIGGER AND A~SO FOR CANCEL SWITCH
TCK JMS PLl RAL
J~N 2 TK3 TKl LOD 8 RAL
JCN A TKl *
* CHECK FOR CANCEL SWITCH
IAC
RAL
RA~
* SLOW DO~N TIMER AND RESTART
JUN TNl *
*
* ROUTINE TO ROTATE PATTERN TXROUG~
* ONE QUADRANT CLOCKWISE (SIX IEFT SnIFTS) *
ROT LDM A
X~ 5 *
ROUTINE TO S~I~T PATTE~ DISPLAY
IE~T ONE POSITION
*
SRC OP
R~3 ~AL
*
~ CO~ iPU'r CA.~ f, i;O,l S.. Irr t FIM OP 5C
~ CH~CK FO~ FINIS}~
; SH3 ISZ 1 SHl JUN REL
* ROUTINE TO SHIFT OP ADDRESSED PATTE2N
~ IN 4269 SHl SRC OP
RAL
WMP
I;DM 11, XCH O
SRC OP
RAL
WMP
SET UP FOR NEXT BLOCK SHI~T
L~M 5 XCH O
. ~
GET PATTE~N ADDRESS DATUM FOR
APPROPRIATE CONTROL SI~JITCH BLOCK POSITION
*
JUN DPL
SX~ FIM OP CO
JUN DPL
* ROUTINE TO ADD DISPLACEMENT TO
~ ~ P~TTE~N ADDRESS
*
- KBP
DAC
CI.C
RAL
RAL
RAR
JMS PLl JUN COM
. ~.
3;~ l * i~O,I GET THE FOU~ Ph'rTE:R;; BfTES
PLl Jr,.s GET
LG~3 E
l 7P 4C
JM~ PUT
LOD E
FII;I 7P 4D
JMS PUT
LOD E
Jhl~ PUT
l.OD E
JUN PUT
ROUTINES TO PUT AND GET PATTERN BYTES
- WMP
INC E
WMP
*
LOD F
BBI. O
* CENTRE ONLY BYTE PATTEPcN FOR
PATTEFZN BOX TEST
= 29C
rIEX 7 1 HEX FF
HEX FF
XEX FF
- HEX FF
*
= 2AO
*
*
* FULL COVER
*
HEX OO
HEX OO
HEX OO
s "....
I~`iM..:2. COV2R
H~X 75 HE~ 5D
* OUT~R RING
*
XE~C Fl INNER RING
HEX Fl HE:X 75 - ~ CRS)SS
HEX CF
f * DIAGONAL CROSS
`- HEX 71 HEX ~6D
HEX DB
{)UTER LINE
*
HEX Fl HEX BC
HEX l?A
HEX FF
MIDDLE LINE
HEX Fl HEX FF
* CENTRE LIN2 HEX CF
HEX FF
HEX FC
*
The extension memory part of this inteirupt handler rcutine examunes the system timer, and if the timer is 0, turns the digital display on for a toggle flag "on" indication and turns the digital display off for a toggle flag "off" indication. The system timer is reloaded when a new switch clo Æ e is detected (see Figure 15).
A flow chart describing the system subroutine is found in Figures 19 and 20~ m e purpose of these routines is to extend the cperation of the system to interface the digital display. The functions of the sub-routine are as follows:
(1) to convert the current selection address to a BCD ccde, to add displacements for the skipped positions and generate the appropriate 7 segment code which is written to the decoder and display driver 58, (2) to check for cperation of TEST, SLoW or FST, after closure of an appropriate crossFoint control switch, and to take appropriate action as follcws:
(i) TEST: starting at position 0, sequentially illuminate the display numkers up to the highest number, i.e. 75 or 90.
The local digital display also is caused to follcw the numker sequence. At the end of the sequence, the pro oe ss is repeated after 5 seconds and clearing of the lamps. The START crosspoint switch is continually monitored and upcn closure the test sequence is halted and the start prooedure is follcwed.
(ii) S~CW: Increment the Fermanent system timer to a maximum value of 15 seconds. When the value is loaded into the system timer register, the digital display takes one mor~ seccnd from the time of switch closure to the on/off flashing sequence for each increment.
(iii~ FST: ~ecrement the Fer~nent system timer. miS
speeds up the tImer by one second~ The minimL~ value of ~his timer is one second.
m e pattern subroutine flow chart is shown in Figures 21 and 22.
These routines are only concerned with the display pattern generator, which is shcwn with referen oe to a 75 number system, due to the limitations of the system capacity as described.
m e patterns are stored in an extension memory, and are ac oe ssed as five stored bytes per pattern. m e pattern switch closures are either a requested pattern or one of two pattern control switches: "RDTATE PATTERN"
and "TEST PATTERN".
If a pattern is requested, the starting address of the first byte is calculatea, and the five bytes are transferred frc~ the extension memory to the last 32 byte block of the RAM storage of the input-output peripheral 37.
Should this option be utilized, a separate pattern light display is utilizea, which is separated into quadrants shcwn in Figure 13.
Groups of lamps within each quadrant are illuminated to display a pattern, which will be ~he pattern of the numbers to be p]ayed by the players of the game.
The light connection diagram is given numerically in Figure 13.
Each quadrant of the bcard can be considered to be in contingucus 6 byte segments of the ccnnec~ed 5 byte pattern. If the pattern is rotated six bytes, then this has the effect of rotating the pattern board ~y 90 degrees.
The six byte rotation is performed in the ROTATE pattern routine.
The TEST PATTERN control switch causes three patterns to be applied to the display board in rapid sequen oe. The process is repeated until a STARr switch closure is detected, at which time an interrupt is generated and the systems operate as on the main routine flow chart described earlier.
m e system can be given the capability to s~bstitute a ranclom nun~er instead of requiring manual selection of a number using the previously noted crosspoint matrix. The randcm num~er generator can be -31~
in~l~ner~ted ky the ~icrcY ~put~r on the ~asis of direc~i~ fra~ stor~d control signals comprisi~g a program.
A mcdulo 16 feedback shift register is implemented, as shcwn in Figure 23. Each shift pcsition is numbered or lettered in sequen oe . An additional function is pr~Jided frcm positions 14 and 15 in position 16, (lakelled 216) which has been found to give ex oe llent randomness of the result. A program to obtain the randcm number in ~n Intel Corporation 4004 microccmputer is as follGws.
Mnemonic Function SHF, ~ 6P ~5 / FE~CH 125 TO REGISTER PAIR 6 SRC 6P / SET UP R~M1J REG 3 ~ CHAR D
RDM / GET CHhR D TO ACC.
INC 13 / INCREI~:NT REGISTER 13 SRC 6P . / SET UP CHAR E
.1 , , . _ .
. .
CLC / CI~EAR CARRY
ADM / MODUI,O 16 ADDITION OF CHARACTERS D & E
XCH ~ / EXC~IANGE ACGUMULATOR WITH RE:GISTER 3 FIM 6P 112 J FETCH 112 TO REGISTER PA:I:R 6 SRC 6P / SEND OUT NEXT SHIFT REGISTER AI~DRESS
RDM / GET SH~ REGISTER CHARACTER
XCH j / EXCHANGE ACCUMULATOR WITH REGISTER 3 l~lRM / WRITE IN PREYIOUS DATA
ISZ 13 *-4 / MOVE UP SHIFT REGISTER
XCH 2 / EXCHANGE ACCUMUI~TOR WITH REGISTER 2 BBL O / RETURN FROM SHP~, RESUL~ IN REGISTER PA~
m e subrcutine uses register 3 m data R~M #1 of the 4004 system.
The register has to be initialized with a pattern other than all zeros.
The simplest initialization pattern is to write the character address in as the shift register character itself.
FIM 4P 112 / F~TCH 112 TO RE~ISTER PAIR 4 SRC 4P / SET UP RAIN 1, PIEG 3, CHAR O
~D 9 ~ TRANS~ER REGISTER 9 TO ACCUMU ~ TOR
~RM / WRITE THIS VALUE IN R ~
ISZ 9 *-3 / LOOP AROUND ALL C-~ARACTERS
It is believed clear that the present system introdu oe s substantial flexibility in the structure and operation of a Bingo type game.
Due to the use of a microprocessor, there is substantial flexibility and thereby improved oFeration afforded the yame operator. Prior to ccmmenoement of the game the system can be fully tested at the touch of a buttQn, whereby all lamps are sequentially illuminated. m e pattern of the testing is such as to convey a visually exciting display, thus increasing the enjcyment of the players.
Once a numker has been called it is displayed to the game operator, and also upon his selection is displayed on the large display board. The most re oently selected number flashes, thus providing instant recognizability to players who may not have been devoting their fullest attentian to the last called number, thus removing the requirement for them to check all numbers an the display board to find out which had been called last. This obviously reduces player fatigue.
Internal timing, which is varia~le at the selection of an cperator, provides a flashing mode to his local digital display to indicate when the next number should be called. Sin oe the timer accurately paces the game, player restlessness is decreased. Further, upan the designation of a w~nning game, a "starburst" or other pattern can be displayed ~n the n~mber display, generally enhancing the excitement of the winning call.
Yet, in the case of an erroneous winning call, the previous display c~n be recalled from memory and displayed for the audience whereupon the game can cGntinueS
3;2 In addition,'~a pattern display can be provided to the audienoe to show the required winning numerical pattern required for sFecial or 7'jackpot" games.
In addition to the aforenoted operation advancements, the present invention allows such structural advantages as the use of more than one display board connected in parallel with others and disp~sed at various locations around the game room. m is is particularly an aid in large Bingo halls, particularly in those which are irregularly shaped. Furth2r-more, the display boards can be located at great distan oes from the main operation console with significantly increased reliability due to the xequirement now of only a four wire cable, rather than the 76 or greater wire cable pr2viously required. The substantially narrower cable can therefore be hidden and can follow a more convenient route around the rcon than heretofore.
It ~ay bec3me obvious to a person skilled in the art under-standing this invention that other modifications and embodiments than those described above can be provided. All are oonsidered within the scope and sphere of the invention as defined in the appended claims.
* AUTO MCB 3 PAGE SYSTEM
* START OF PAGE ZERO
= 000 NOP
JUN STR
*
INTERRUPT ROUTINE
*
* FIP~ST SAYE MAIN ROUTINE STATUS
*
INT SBl ~ .
LCR
RAL
*
* NOW iSTAART INTERRUPT ~ANDLER
*
CI~ECK FOR END OF BLOCK 2 ~ .
~qS CAD
RDl RAL
*
* IF BLOCK 2 END, INCREMENT " OUNTER
* AND CHECK FOR SCAN TRIGGER
*
- * Cl~ MENCE: SCAN AFTER WAITING FOR
* END OF BL9CK 1 *
INl RDl RAL
J"N 2 INl *
* CXE:CK FOR TRIGGER BEFORE SCAN
*
*
* SCAN BLOCK 1 *
FIRST CLEAR SWITCH CLOSURE COUNTER
*
,i .
LDM O
* NOW SCAN
JMS BLK
*
* NEXT SCAN Bl.OCK 2 * FIRST WAIT FOR END OF BLOCK 2 JI~IS CAI~
IN3 RDl RAL
* NOW SCAN
JMS BLK
END OF BI,OCK SCANS
*
CHECK SWITCH Cl,OSURES
*
* KBP, JUMP IF NO SWITCH CI,OSURES
*
LDM F
X~H 9 JUN ENl *
JUMP IF SINGLE SWITCH CLOSURE
*
SET NI:BBhE FLAG
RAR
XC~ 9 JUN ENl *
* SET BLOC~ FLAG FOR SINGLE SWITCH CLO~;URE
XC~
XCH A
INCREMi~:M~ INTERRUPT TIMER LOw ORDER NIBBhE
* TO TAKE ACCOUNT OF TIME TO SERVICE INTERRUPT
,. *
3~
E~l IliC 3 * CHECK HIGH ORDER hIBBI~: I
*
*
* R2~0AD INTERRUPT TIMER AND
SERVICE SYSTE~ TIMER
LOD D
LOD C
*
* HAYE TO CHECK FOR ON TOGGT~ - FIRST
S:~39 RAI.
*
DAC
,JUMP TO EXTENSION MEMORY
JMS IEX
* ~LASH CURRENT SELECTION
SRC lP
SBl I,OD 5 CMA
*
I,OD 8 RAL
~N7 IN8 ~hqP
*
TOGGLE ON/OFF FLAGr *
IiY9 XCH 8 RAL
CMC
`~ RAR
XC~
*
J
* ~I~AP UP
f ~
EN2 J~3 CAD
XC~ 6 RAR
DCL
BBS
* SUBROUTINE TO S~T UP CONTROL
SRC OP
BB~ O
* SUBROUTINE TO SCAN A ~LOCK
~ OF 8 X 7 SWITCHES
CI,C
RAL
". BLl SRC QP
SAMPIE LO'~ ORDER NIBBIE
SKIP IF NO CLOSURE
JMS l~qOI`~
* SAMPLE HIGH ORDER NIBBIE
~L2 RDl *
SKIP IF NO CLOSU~E
LDM O
JMS MON
* INCREr~NT RO~ ADDRESS AND
* CHECK FOR COl'~PIETION
*
3a ~ !
~ " ~
~L~ l IiYC 1 IOD~ 1 . i IAC
IAC
JCN C BLl *
BBL O
*
MONITOR ROUTINE FOR SWITCH C~OSURES
*
*
* MASK OUT RDl/RD~ FLAG
*
I.OD 8 RAR
CLC
RAL
* . I
* NOW PUT IN CURRENT STATUS
* . I
0~?5 - . XCH 8 '.
LOI) 1 XCH A
* CHAI`JGE SWITCH CLOSURE COUNTER STATUS
~N2 LOD 9 KBP
RAL
Lt:)D 7 STC
RAI, RAL
XC~ 7 *
BBL O
*
* START OF l~iAIN ROUTINF
*
* FIRST SET UP 42~9 TO ~01I.Ol,~ING STATU~
#
* INDIVIDUAL SCANNED DISPh~Y: 16 DIGITS
* ON A & B RE~ISTERS.
I
~9 SCAI;5i~) S~ CH SE.~SO?~ ri'lr.T.~IX
*
S RC OP
LDM O
tlR O
'~JR 1 * SET U~! 4265 TO OUTPUT MODE
SRC OP
W~P
SET INT~RRUPT TIMER TO 0. 5 SECONDS
SET SYSTEM TI~IER TO 10 SECONDS
*
IDM A
XCH B
*
* SET CUP~RENT SELECTION TO IN~IIBIT
*
FTM lP CO
*
* ENAi3IE INTERRUPTS AND START CHECKING INITIAI.
* VALID ADDRESS
t * FIRST CHECK VALID A~DD~2SS
*
COM DIN
l,OD 9 EIN
IAC
JCN 4 C 01!5 *
TURN OFF INTERRUPTS
*
DIN
JUMP TO EXTENSION MEMORY
*
JMS CSW
~r D
L4~
CilECK YOR Chi`iCLL Ci~ STA.D.T
CM7 LDr,l 3 C~C
ADI~ A
CM9 LOD 8 , I
RAR
LOI) 7 RAL
RAL
*
* RESTART GAI~ CLEAR 4269 *
SRC OP ~-LDM O
WRl FIM lP CO
*
* TURN ON INTERRUPTS AND BACK TO START.
*
EIN
*
- JUN C OM
CHECK CANCEL
C;.16 LOD 7 RAI, CANCEL CURRENT SELECTI ON
* FIRST WAIT FO~ TOGGLE OFF
EIN
R Al, FIM lP CO
*
JUN C OM
* GET C ONTENTS OF ADDRESS
FIRST G T Al:)D.~ESS
C~il4 LOD A
XCH l l I
~1 ,, RAR
I~DI~I 2 RAL I r XCH O
* TURN ON I i`lTERRUPTS
EIN
RAL
JCN A T ON
SRC OP
CHECK I~ ALREADY WRITTEN TO, i JCN 4 C Ohq * ~ ., WRITE NEW SELECTI ON
I,OD O
.
* JUMP TO ~XTE~ISION MEMORY
~lS BIN
* ! - i REWRITE~ SYSTEM TIMER
XCI~ 6 JUI~ ~O~
*
*
.
- ~t 2 4~;3Z
*~li**~*~***~*~****~*~*****~ t PA~ 1 JUIl~;P ADD2~SS
- 10() *.
~ WRITE TO DI~PLAY
* ROUTINE TO GET THE BCD VALUE OF 426 * ADDRESS IN BANK O REGISTER PAIR 7 ~ FIND BINARY NUMBER FROM NIBBIE PATTERN
BIN . LOD 7 KBP !-XCH F
* ADD 4 IF NECESSARY
LOD O
LD~ 4 ADD F
XCX F
*
* ADD 8 IF NECESSARY
CLC
R~ . j XC~ E
C~C I
LDM 8 i-ADD F
- XCH F
* PR~VENT WRITING IF CONTRO~ SWITCH
~BL l * CORRECT FOR DISPLACEI'~ENTS
LOD F
SUB F
XCH F
CMC
LDM O
XC~ ~
SUB E
XC~ ~:
*
* LEAYE ~ 3 ~ ~ ~1Lr~3Z t . ,. - - ~ ,j,, ;
* ROUTIN~ TO CON'JERT 7P ~ AR'l TO ~CD ~D T ~AYE R2SULT IIY 7 BCI:I CLB
XC}~ E
LD~I A
XCH F
* i3CD COUNTER IN REG. ~:, MSD IN REG. 5, A IN REG. F & LSD IN ACCUMULATOR
* NOW SUBTRACT A FROM LSD
BC3 Sl1~ F
* CHECK FOR ~302ROW
DAC
XC}I 5 * LSD IN AGC,, MSD-l IN REG. 5 13Cl JCN A BC2 3UMP IF ANSWER FOUNl:l INC E
CLC
.JUN BC3 * ADD BACK 10, PUT LSD IN REG " F AN~ EXIT
XCH F
* ROUTINE TO WRITE 7 SEGMENT CODE TO
* DISPI,AY, BCD IN 7P
WP~T FIM OP 80 S~C OP
*
* 4265 ADDP~ESSED, NOW GET COI)E TO REG, PAIR O
* FIRST C~ECK FOR I.EADING ZERO
FIM OP O O
LOD E
JCN 4 WTl LDM F
X~X O
CLC
ADD E
XC~ 1 ~4 CG;~., hDD,~s S I;~ OB, NO~ v.,T C03E
FIN OP
* ~JRITE COD~ TO MS~
*
IfT1 LOD 1 WRO
~JR2 * SAI'~E PROCEDURE FOR LSD
WT3 ~DM F
XCH O
CLC
LDM 6 t ADD F
FIN OP
*
I,OD 1 .:
WRl LOD O
~ .
:BBL O
* CHECK FOR GONTROL S~'1ITCH
* (SLOW, FAST OR TEST) *
CS'~ LDM 3 ADD A
JCN 4 CSl *
* JUMP TO EXTENSION MEMORY 2 *
CS2 JUN CSX (for 1 page memory exten~ion CSl LOD 8 this becomes CS2 BBL O
*
RAR
.~ .
RAR
*
I.OD 7 RAL
*
* I~:ST ROUTINE
_~ ~r ~a~L~ I
* PUI' ST~.RTIi~lu NUr~B2R IN s~r Ai~i:l?.ESS
hN~ ~CD C()i~ IN 7P
*
TST FIM lP 50 L[~r.~ 1 FIM 7P ~1 !
SPEED UP TIMER
*
START TEST LOOP
EIN
*
* FIRST STOP SYSTEM TIhiER FLAG
*
TSl LDM E' WRITE OUT TO DISPIAY
JMS WRT
*
* TURN ON DISPLAY
*
LDM F
JMS BSR
*
* WAIT FOR TRANSITION FROM TOGGIE OFF TO
* TOGGLE ON, THIS ESTABLISHES THAT THE
* PREVI OUS DATA WAS WRITTEN
*
RAL
T~;2 LOD 8 RAL
*
* UPDATE BCD DATA
*
CT~3 XCH F .
IAC
DAA
XCH F
ADD E
XCH E
*
* UPOATE NIB:3LE I
~ I
TS7 Cl.C
I~OD 4 RAI.
*
Lr ~; i C.~2CK FOR OVE~.FLO,1 * OVER~LO~ ROUTINE
FIRST ROTATE NIBBIE AGAIN
R~L
*
* NOW CHANGE NIBBLE OF SRC ADDRESS
RAR
CMC
* C~ECK IF NOW 5 IN MS NIB~IE
JC~ A TS5 INCREMENT LS NIBBLE
* PUT BACK REG. 2 * PUT BACK NIB31E
TS~ XCH 4 * CORRECT FOR DISPLACEMENT IF NECESSARY
* CORRECTION NOT REQUIRED IF MS SRC = 5 RAR
* CORRECTION NOT REQUIRED IF SRC OF LS EVEN
RAR
* CORR~.CTION NOT REQUIRED IF NIBBLE PATTERN
* IS NOT IN MOST SIGNIFICANT P~C~-LOD
RA~
* CORRECT FOR DISPLhCEMENT BY GOXNG
* TO NEXT ADD~ESS
~7 , ,, ., ~
JUN TS?
* CHECK IF FINIS~;D (76 IN BCO) (91 for 5C~
number system) * FIRST CHECK FOR START SWITCH
TS6 ~OD 9 IAC
RAL
RAL
TS9 1.13M 9 (J,DM 7 for 90 number system) CLC
ADD E
LDM 9 ( LOD F f or 90 number sy3tem ) ADD F ~DAC " " " "
* SLOW DOWN INTERRUPT TIMER
* SET SYSTEM TIM2R AND WAIT FOR ZERO COUNT
(~ LDM 5 *
RESET AND BACK TO BEGI~YNING
JUN TF~
*
ROUTINE ~0 SP~:ED IJP TIM~:R
*
DAC
XCH B
JUN REL
*
* ROUTINE TO SLO~ DOl,~IN TI~R
*
SLW LOD B
IAC
XCH B
*
~- * ROUTIN:E TO WAIT FOR RELEASE OF
* CURRENT CONTROL S~IITCH
~8 z RE1 DIil I.OD 9 IAC
EIN
JCIY C REL
DIN
JllN C 0 ,~,, .
INTERRUPT EXTENSI ON, CHECK FOR TOGGIE
OFF AND ZERO SYSTEM TI~IER. IF TRUE
* l~{EN CANCEL DISPLAY
~IRST CANCEL DISPLAY IF VOID ADDR~SS
~ .
- RAL
LDM E
JCN C IXl RAII
I~M E
JCN A BSR
IXl LDM F
ROUTINE TO WRITE ACC, TO BIT SET/RESET
SRC OP
S~C
WRM
B~L O
FINISH OFF TEST ROUTINE
TFN SRC OP
LDM O
WP~1 JUN TST
TND ~IM lP CO
* JUST PUT IN YOID ADDRESS~, NCW RESET TIiæR
TN1 :FIM 6P A5 * RESET 4269 AND LEAVE
JIJN RST
~9 ' 7 S~;ii2NT CGDr FOR DISPIRY
= lF6 HE~ 3F
HEX o6 HEX 66 i, *
~*********~****~********~**~*~**~****~**~*~*
': *
*
* CHECK CONTROL S',11ITCHES FOR
* PATTERN GENERATOR
* CHEC~ FOR PATTER~ CONTROL, * JUII~P TO APPROPRIATE CODE IF C02RECT
CHECK. OTHERWISE RETURN TO PAG~ 1 *
CSX LD~I 3 CI~
ADD A
JCN 4 SXl IAC
IAC
IAC
XND BBL O
*
SXl LOD 8 RAR
JCN A XND
RAR
RAR
JCN A XND
* ROUTINE TO DYNAMIChLL~ TEST
* PATTERN BûX
* FIR~T SP~.ED UP TIifir.R
T~ FI~I 6P F5 EIN
JMS TCK
FIM OP AC
Ji~ T~
JMS TC~
JUN TPT
* ROUTINE TO CXE5K FOR NEXT PATTERN
~ TRIGGER AND A~SO FOR CANCEL SWITCH
TCK JMS PLl RAL
J~N 2 TK3 TKl LOD 8 RAL
JCN A TKl *
* CHECK FOR CANCEL SWITCH
IAC
RAL
RA~
* SLOW DO~N TIMER AND RESTART
JUN TNl *
*
* ROUTINE TO ROTATE PATTERN TXROUG~
* ONE QUADRANT CLOCKWISE (SIX IEFT SnIFTS) *
ROT LDM A
X~ 5 *
ROUTINE TO S~I~T PATTE~ DISPLAY
IE~T ONE POSITION
*
SRC OP
R~3 ~AL
*
~ CO~ iPU'r CA.~ f, i;O,l S.. Irr t FIM OP 5C
~ CH~CK FO~ FINIS}~
; SH3 ISZ 1 SHl JUN REL
* ROUTINE TO SHIFT OP ADDRESSED PATTE2N
~ IN 4269 SHl SRC OP
RAL
WMP
I;DM 11, XCH O
SRC OP
RAL
WMP
SET UP FOR NEXT BLOCK SHI~T
L~M 5 XCH O
. ~
GET PATTE~N ADDRESS DATUM FOR
APPROPRIATE CONTROL SI~JITCH BLOCK POSITION
*
JUN DPL
SX~ FIM OP CO
JUN DPL
* ROUTINE TO ADD DISPLACEMENT TO
~ ~ P~TTE~N ADDRESS
*
- KBP
DAC
CI.C
RAL
RAL
RAR
JMS PLl JUN COM
. ~.
3;~ l * i~O,I GET THE FOU~ Ph'rTE:R;; BfTES
PLl Jr,.s GET
LG~3 E
l 7P 4C
JM~ PUT
LOD E
FII;I 7P 4D
JMS PUT
LOD E
Jhl~ PUT
l.OD E
JUN PUT
ROUTINES TO PUT AND GET PATTERN BYTES
- WMP
INC E
WMP
*
LOD F
BBI. O
* CENTRE ONLY BYTE PATTEPcN FOR
PATTEFZN BOX TEST
= 29C
rIEX 7 1 HEX FF
HEX FF
XEX FF
- HEX FF
*
= 2AO
*
*
* FULL COVER
*
HEX OO
HEX OO
HEX OO
s "....
I~`iM..:2. COV2R
H~X 75 HE~ 5D
* OUT~R RING
*
XE~C Fl INNER RING
HEX Fl HE:X 75 - ~ CRS)SS
HEX CF
f * DIAGONAL CROSS
`- HEX 71 HEX ~6D
HEX DB
{)UTER LINE
*
HEX Fl HEX BC
HEX l?A
HEX FF
MIDDLE LINE
HEX Fl HEX FF
* CENTRE LIN2 HEX CF
HEX FF
HEX FC
*
5 1, * DIh~s Or`iAL
HEX 6F' HEX FF
K
*
HEX BF
HEX ~F
*
L
*
XEX Fl HEX EA
HEX CF
* p *
HEX BF
U
*
HEX Fl *
* V
*
HEX FD
- H X FF
*
*
$
HEX 6F' HEX FF
K
*
HEX BF
HEX ~F
*
L
*
XEX Fl HEX EA
HEX CF
* p *
HEX BF
U
*
HEX Fl *
* V
*
HEX FD
- H X FF
*
*
$
Claims (7)
1. In an electronic Bingo game, the combination comprising an electronic random number generator, a control switch, a general display for individually illuminating one or more numbers corresponding to the generated random number, means for causing illumination of said corresponding number upon generation of said random number and upon at least temporary operation of said control switch, the random number generator being comprised of a microcomputer system including data and program memories connected to a central processing unit, adapted to generate a random number signal and to store and process signals representative of the generated random number signal as well as signals representative of a signal processing sequence, and to derive and store signals representative of one or more of said lamps to be illuminated as a result of translation of the processing sequence signals, said means for causing illumination of said corresponding number being comprised of converter means connected to the microcomputer system for translating the random number signal into a serial bit stream signal representative of the address of one or more particular lamps to be illuminated, and a display bus connected to the output of the converter means for carrying the serial bit stream signal, for connection to a serial bit stream signal decoding and lamp illuminating circuit.
2. The combination as defined in claim 1, the random number generator including a module 16 counter, in which the digit in the 14th and 15th positions are added into the 16th position as the counter shifts data sequentially therethrough.
3. In an electronic Bingo game, the combination as defined in claim 1 further comprising a ball table including a matrix of numbered switches for closure upon interference by a numbered ball, a plurality of control switches, a general display for individually illuminating one or more numbers corresponding to each numbered switch of the matrix of switches, means at the table for causing a digital display to indicate the number of the numbered switch upon at least temporary closure of one of said numbered switches, and means for illuminating the corresponding number in the general display upon at least temporary closure of a predetermined one of the control systems.
4. In an electronic Bingo game, the combination as defined in claim 3 further comprising means for causing flashing of the latest illuminated number of the general display while rendering the remaining previously flashing numbers continuously illuminated.
5. In an electronic Bingo game, the combination as defined in claim 3 or 4, further comprising means for causing flashing of the digital display a predetermined period after its initial display, and cessation of flashing once a new number has been indicated.
6. In an electronic Bingo game, the combination as defined in claim 3 including means, upon at least temporary closing of a predetermined control switch, for causing illumination of all numbers in sequence.
7. In an electronic Bingo game, the combination as defined in claim 6, in which said sequence follows a predetermined pattern, and further including means for extinguishing said pattern and re-establishing the display upon at least temporary closure of a further predetermined control switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000387780A CA1141032A (en) | 1978-04-07 | 1981-10-13 | Electronic bingo system |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA300,670A CA1115417A (en) | 1978-04-07 | 1978-04-07 | Electronic bingo system |
| CA000387780A CA1141032A (en) | 1978-04-07 | 1981-10-13 | Electronic bingo system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1141032A true CA1141032A (en) | 1983-02-08 |
Family
ID=25668678
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000387780A Expired CA1141032A (en) | 1978-04-07 | 1981-10-13 | Electronic bingo system |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1141032A (en) |
-
1981
- 1981-10-13 CA CA000387780A patent/CA1141032A/en not_active Expired
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |