GB1571291A

GB1571291A - Tv game apparatus

Info

Publication number: GB1571291A
Application number: GB49139/76A
Authority: GB
Original assignee: NUTTING ASS
Current assignee: NUTTING ASS
Priority date: 1975-11-26
Filing date: 1976-11-25
Publication date: 1980-07-09
Also published as: DE2653859A1; FR2336737B1; IT1074986B; DE2653859C2; JPS5275112A; CA1114054A; JPS5625156B2; FR2336737A1

Description

(54) TV GAME APPARATUS (71) We, DAVE NUTTING ASSOCIATES, INC., a Corporation organised and existing under the laws of the State of Illinois, United States of America, of 511 West Golf Road, Arlington Heights, Illinois 60005, U.S.A., do hereby dedare the invention for which we pray that a Patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- Background of the Invention This invention relates to a player operated visual game apparatus in which moving symtolls appear on the screen and move in accordance with player operated input means.

In the field of game apparatus and the like, recent developments have employed To type devices with moving symbols for simulating playing of various competitive games. For example a widely available ping pong TV game apparatus has been developed wherein a ping pong symbol moves across a TV-type screen.

The players actuate a lever control to move a smail strip, to simulate a paddle, verticals along the opposite edges and if intercept is made, the ball is returned to the opposite side for similar control by the opposite player. Of course, if intercept is not made, the ball moves off the screen and a point is given to the opposite player. Other somewhat more sophis located games have also been suggested. For example, a baseball game may he played wherein a ball is automatically thrown to a batter under proper control by the player operator.The other player operates his control to effectively bat the ball which then moves throughout the field and among a number of players. General!ly, control means reposition the players, particularly around the bases in accordance with the predetermined movement of the simulated ball.Generally, the TV games are developed employing a raster type TV to minimize the cost and with a black and white presentations in which various shades of gray may be produced by binary coding of the intensity drive. Simple movement is normally controlled by horizontal and vertical counters in combination with a hard wired game logic feeding into a suitable coincidence gate, the outpu-t of which controls the video signal of the display.The display unit in turn includes a conventional vertical and horizontal positioning control which, in combination with video coincidence gates, provides for the desired illumination and effective apparent movement d the symbols. Although such devices are employed, they are relatively expensive and are custom designed to each particular game.

Sternatively, the particular game may be stored in a particular read-only memory system for generating of the particular symbols, with the movement and the position thereof controlled by the hardwired game logic. The TV display is then actuated from a controller game logic signal to the coincidence gate. Such systems are acceptable where a relatively few symbolls are employed and only limited capability and control is desired. In multiple synibol-type games and where each is to move over some or alb of the display field, the prior art synthol movement tends to be jerky and unrealistic.Further, the implementation od the system presents certain difficulties from a practical implementation.

In accordance with one aspect of the invention there is provided a player~operated game apparatus for use with a display means having an intensity control means for varying the intensities of picture elements for the presentation of movable symbols on a screen, said apparatus having player-operated means in eluding input elements adapted to be operated by a player and signal means aotuable by said input elements, for enabling interaction of the player with the symbols on the screen, digital display memory means for storing in a digital form a set of digital bits representing the intensities necessary for generating a display on salid screen and locating the symbols within the display, display controller means for addressing said display memory means and reading bits in the display memory means in time-spaced read periods separated by reading idle periods, said display controller means being adapted for connection to said intensity control means of the display means to transmit the bits read to said intensity control means to present the desired display stored in said display memory means, a processor, program means, communicating port means for connecting the signal means of the playeroperated means to the processor, said processor having means for accessing said program means and said display memory means to represent symbols in response to said signal means and said program means wherein the processor modifies digital bits of the symbols in the display memory means to revise the symbols within the display, and control means operatively connected to the display controller means, for operatively coupling the display memory means to the processor during said reading idle periods to change said display memory means between said read periods.

The invention also provides a game apparatus for presentation of game symbols comprising: a raster scan television screen unit having an intensity control means for controlling the intensity of a beam and generating display frames each of which includes a plurality of spaced scan lines of a plurality of display points, a clock means driving a sync and blank means for blanking the beam during horizontal and vertical retrace periods; a processor having a program means which has an instruction bus, said processor having an address bus connected to said program means;; a random access memory having a memory address bus and having a first plurality of memory locations for storing in digital form a set of digital bits representing the intensities necessary for generating a display on said screen and locating the symbols within said display and having a second plurality of memory locations defining a scratch pad for said processor and having a data output bus and a data input bus; a display controller means, having an address bus, for addressing said random access memory and reading the set of bits in said random access memory;; an address multiplexer having a display con troller address input connected to the address bus of the display controller means and a processor address input connected to the address bus of the processor and an address bus output connected to said random access memory address bus and said address multiplexer being connected to said display controller means for coupling the display controller address input to the address bus output during each address by the display controller means of the random access memory, and the processor address bus input therebetween, said display controller means, having a serializing means connected to said data output bus of the random access memory, said display controller means having means for addressing said random access memory and reading a byte set of bits in the random access memory associated with a symbol in time-spaced read periods separated by reading idle periods and storing the byte in the serializing means, said display controller means being adapted for connection to said intensity control means of the raster scan display means to transmit the bits from said serializing means to said intensity control means and present the desired display stored in said display memory means;; a plurality of sets of player-operated means, each set of player-operated means including input elements adapted to be operated by a player and digital encoding means for encoding movement of the input elements, an interrupt logic means connected to said display controller means for generating memory update signals, a data decoder having a first input connected to the instruction bus, a second input connected to the memory data output bus, a third input connected to the player-operated means, a fourth input connected to the interrupt means, and an output, and said data decoder being operatively connected to the processor for connecting an input to the output as determined by the processor, a processor multiplexer having an input bus connected to the output of the decoder and having a data output bus connected to said memory data input bus and having a readwrite bus connected to said processor, and operatively connected to the processor for connecting the read-write bus to the input and output bus as determined by the processor, and said processor having means in response to said memory update signals for addressing said program means and said random access memory to represent the symbols in response to said digital encoding means and said program means whereby the processor modifies the location of the digital bits of the symbols in the random access memory thereby relocating the symbols within the display.

In accordance with a further aspect of the invention there is provided a player-operated game apparatus for use with a raster scan TV display means for presenting movable symbols in a plurality of serial frames on a TV screen, said apparatus having player-operated means for enabling interaction of the players with the symbols presented, an inter-facing means for providing a memory of representations of the symbols and locations of the symbols in the frames, a display controller means for reading the memory of the interfacing means and transferring the representation of the symbols to the raster scan TV display means for presentation on the TV screen, and a programmed processor for updating the memory of representations of the symbols of the interface means in response to the player-operated means, and said interfacing means further providing an interface between the display controller means and the programmed processor so that said display controller means and said programmed processor can operate independently of each other.

The drawings furnished herewith illustrate a preferred construction of the present invention in which the above advantages and features are clearly disclosed as well as others which will be readily understood from the following description.

In the drawings: Fig. 1 is an illustration of a TV game apparatus with character presentation in accordance with programmed processor control for describing an embodiment of the invention; Fig. 2 is a block diagram illustrating the display and display generating components of a preferred embodiment of the present invention; Fig. 3 is a diagrammatic view of first player operated control means for controlling the movement of the symbols on the screen of the TV game apparatus; Fig. 4 is a view similar to Fig. 3 illustrating a second control means for the first player and providing for additional control of the movement of the symbols; Fig. 4a is a view of one of the symbols shown in Fig. 1, with various alternate programmed poses of the symbols shown in phantom;; Figs. 5 and 5a are a schematic circuit illustrating a basic programmed processor board for developing of the game mode of play; and Fig. 6 is a schematic circuit illustrating a particular game logic board for coupling of the game information to processor board circuit for completing of the circuit for a particular game shown in Figs. 1--4.

Referring to the drawings and particularly to Fig. 1 game apparatus is illustrated includ- ing an outer housing 1 with a visual display screen 2 for the presentation of the play of a gunfighter game by a pair of players, represented by first gunfighter 3 and a second gunfighter 4 located to the right and left sides of the screen. The viewing screen 2 includes a suitable background field which is shown for purposes of showing one possibility as a simplified western landscape. The gunfighter 3 includes a gun 5 for shooting of bullet 6 across the screen. The gunfighter 4 similarly includes a gun 7 for shooting a bullet 8 toward the opposite shooter.Obstacles are positioned between the gunfighters 3 and 4, and are shown including a plurality of cactus and trees 9,and 10 adjacent each of the gunfighters 3 and 4 and a centrally located wagon 11 which can move vertically across screen 2, as more fully developed hereinafter. The gunfighter 3 and 4 may be identified by a suitable legend, not shown, and hits identified as at 12 at the top of the screen 2. The available bullets may also be identified by bullet illustration 13 on the bottom of rhe screen. The apparatus may, in accordance with known game devices, have a coin control means with a coin slot input 14 to initially activate the game. First and second sets of manual controls 15 and 16 are provided to the exterior of the housing 1 immediately below the display screen for each of the players.

For the gunfighter game, the control 15 for gunfighter 3 includes a trigger handle 17 including a trigger 18 which is operative to acrivate the viewing screen 2 to shoot a bullet 6 from gun 5. Handle 17 is also pivotally mounted for moving of the shooting arm 19 of the gunfighter 3 for corresponding positioning of rhe gun. The player may thereby direct the bullet angularly upwardly or downwardly.

Control 15 further includes a joy stick lever 20 which is mounted for universal horizontal pivoting to move the gunfighter vertically and horizontally on screen 2.

The controls 16 for the second player are similarly constructed and identified by corresponding primed numbers. Thus, controls 16 include the gun handle 17' with trigger 18' and a joy stick lever 20' for corresponding actuation and positioning of the second gunfighter 4.

The several controls 15 and 16 include encoding means for generating signals to a programmed processor game circuitry, as more fully described hereinafter.

In the play of the game, each player is allotted the same number of bullets 6 and 8 with a set game time in which to shoot the opposite gunfighter. Each player actuates his lever 20-20' to move his gunfighter 3-4 to avoid being hit and to position himself to shoot the opposite gunfighter. The handle 17-17' and trigger 18-18' are actuated to position rhe gunfighter's arms 19-19' and to move a bullet 1818' across the screen 2 for hitting of the opposite gunfighter.

The present invention is particularly directed to the method of implementing the presentation on the screen 2 and the response to the available player controls 15 and 16 to accurately visually display the game and in particular to create movement of the players in an interesting and generally realistic manner such as to simulate running movements and the like. Further, as presently described, the invention is particularly addressed to the development of a single programmed system which can be rapidly, conveniently and inexpensively constructed to any other game.

For example, the programmed processor game circuitry, as presently described for the gunfighter game may be readily adapted and converted to present a baseball or football game by modifying of the viewing screen to present an appropriate playing field with the appropriate players positioned thereon for controlled movement and adapting the encoding means to directly control movement or to create machine assisted and determined movements with the same or other manual controls.

More particularly and referring to Fig. 2, a block diagram illustrating a preferred and novel construction of the present invention for general universal application to different games is illustrated wherein the screen 2 forms a part of any conventional raster scan television unit 21 having a video and sync input 22 for receiving of the appropriate syne signals and beam illumination signals for generating of the appropriate display such as that shown in Fig. 1 on the screen. Generally, a raster TV unit 21 includes a scanning beam 22a which is eontinuously moved across the screen 2 in a plurality of horizontal scanning lines 23, each of which consists of a plurality of points 24 for illumination to generate the symbols or patterns 3, 4 and the like.During the retrace of the scanning beam 22 from the end of one line 23 to the next, the beam 22 is blanked, as shown by the retrace line 25. At the end of the bottom scan line 23, rhe beam 22 is again blanked for the vertical retrace, shown by the vertical retrace line 26. In a conventional TV unit, successive frames of scan lines for each picture have the scan lines 23 interleaved to.

increase the resolution of the display. Thus, the TV unit 21 may be any conventional raster scan type unit. As more fully developed hereinafter, in the illustrated TV game apparatus of this embodiment, the scan frames are not interleaved to display the symbols, which therefore are drawn with a plurality of spaced brightened portions of the scanning lines 23.

Consequently, no further description of the TV unit 21 which may he any well-known or desired construction and may be readily found in the prior at is given other than as necessary to clearly explain the present invention.

The prior at may be referred to by the ordinary worker for reference purposes and details of construction of a TV unfit Generally, in accordance with the present invention, the video signal applied to the input 22 is derived from a random access screen memory unit 28 employed as the interfacing between the screen display means and the game display control means which otherwise funcrion as separate and distinct functional devices. A sync generating and display control unit 29 reads the memory unit 28 and combines the stored data with a TV sync signal for display of the stored material as a static presentation of the view stored in memory.The view in memory unit 28 is written by an integrated program processor 30 during periods when the memory unit 28 is not required by the display cycle, which periods are generally defined as idle time or periods in this description. In particular, the random access screen memory unit 28 is suitably connected for joint but separate or individual communication with the display control unit 29 and processor 30. In the iilustrated embodiment an appropriate multiplexer unit 31 is employed.

The random access memory unit 28 is selected of such a size to correspond to and com pletely store the information necessary for presentation d a complete display and illum ination of the TV screen 2. For example, the TV unit may be arranged with a dot pattern of 2516 by 224 and requires a memory unit 28 on the order of 57,344 bits. Such a random access memory 28 is of course readily available and will completely store the information necessary for 'illumination dot in a conventional raster type TV unit 21.

A TV control clock unit 32 drives a hori zontal line counter 33 and a vertical position counter 34 which define the position of the 'scanning beam 22a on the screen 2. The horizontal and vertical counters 33 and 34 define a first address means connected by the multiplexer 31 to address the memory unit 28 for sequential reading of the memory locations or points. The memory unit 28 reads in suitable multiple 'bit bytes, each of which thus defines the state of a series of points in a scan line 23, and are connected by a parallel to serial latch unit 35 to the common input 22 of the TV unit 21.A sync and blank unit 36 is also driven from the TV counters and combined with the video signal as at 37 for connection to the common input and thereby establishes synchronism between the readout of the locations of memory unit 28 in accordance with the position of the beam 22a on screen 2.

The TV dock or source 32 is also connected to the select input 38 of the multiplexer 31 to establish priority coupling of the memory unit 28 to the TV unit 21, and to selectively acti 7fate the multiplexer 31 to connect a processor bus 39 to rhe memory unit 28.

The sync and blank unit 36 and the select input 38 to the multiplexer are re synchronized to allow the processor 30 to communicate with the memory unit 28 for calculation and updating of the screen display during display reading idle periods when the TV display system is not addressing and reading the memory unit 28. A logic circuit 40 is also coupled to the sync and blank unit 36 to further generate interrupt signals during such idle periods and set appropriate fags or the like, not shown, in the processor 30 to communicate with the memory unit 28 for rewriting of the symbols or patterns.

Generally, the processor 30 includes a central processing unit (CPU) 41 which functions in a programmed sequence under the control d a prograruned memory 42, which tis illustrated as a read-only memory. An inputoutput buffer interface device 43 includes an input bus 44 for coupling to the player operated control elements or controls 15 and 16 and an output bus 45 for energizing of suitable auxiliary visual and sound devices 45a associa- ted with the game apparatus 1. The central processing unit 41 d the processor is also connected by a display update bus 46 to the RAM 28 and to the input-output interface device 43.An address bus 47 is connected to the address multiplexer 31 to selectively establish and control communication with RAM unit 28. The central processing unit 41 cycles through its program under the control of the read only memory 42 to continuously monitor and poll the condition of the control elements 15-16 which includes suitable condition encoding means. The program memory 42 further includes the necessary programs to vary the display or the point illumination data stored in the RAM 28 in accordance with the encoding means as set by activation of the controls 15-16.

The processing unit 41 further requires a scratch pad memory to complete the data reduction. In the illustrated embodiment of the invention, a portion 48 of memory unit 28 is employed for such memory. Thus, the memory map for the processor includes the RAM program memory which may consist of 8000 addresses each of which includes an eight bit byte. The scratch pad may include the next 1000 addresses and the screen or RAM the next 7000 addresses. The processing unit 41 starts at the initial address and then proceeds to process the various game I/O means to control the play and response of the game to rhe input controls.

Referring to Fig. 3, the trigger handle 17 encoding means includes a switch 49 coupled to the trigger 18. The switch 49 completes a circuit from a logic power supply 49a to rhe I/O unit and when read by the CPU 41 causes shooting of one bullet 6 across the screen 2.

The direction is encoded by a three bit logic code generated by pivoting of rhe trigger handle 17, as follows. More particularly, a coding disc 50 is coaxially mounted adjacent the handle support pivot 5.1 and includes three radially spaced concentric contact segments 52, 53 and 54. Fixed contacts 55 are secured to the handle 17 and slidably engage the contact segments 52, 53 and 54 in response to rotation of the handle 17. The fixed controls 55 and aligned contact segments are separately connected to the signal voltage supply 49a and by leads 55a the I/O unit to correspondingly open and close the circuit for reading by the CPU 41.The pivoting of the handle 17, generates seven three bit code combinations, defined by combinations of the open and closed circuits each of which corresponds to a particular position of the shooter arms 19, including a horizontal position 56 and two raised and two lowered positions 57 and 58, as shown in Fig. 4a.

Similarly, the gunfighter 3 movement is encoded by the "joy" stick control 20. Referring to Fig. 4, in the illustrated embodiment a control disc 59 is secured to the pivot shaft 60 of the control. The lever 20 projects through the disc 59 and pivoting of the shaft 60 moves the disc 59 to selectively close four equicircumferentially distributed switches 60, 61, 62 and 63. The latter switches are related to cause the associated gunfighter 3 to move in the corresponding direction. Thus, each switch 60-63 is connected between the control voltage supply 49 and the I/O unit to provide corresponding individual control signals.The CPU 41 again reads each switch line and correspondingly calculates the repositioning of the gunfighter symbol 3 from the present posi tion. Thus, if the right hand switch 60 in Fig. 4 is closed, the gunfighter 3 is to move to the right. The CPU 41 correspondingly erases the symbol 3 and rewrites the symbol in the appropriate shifted memory block of memory unit 28. If both the upper and right switches 60 and 61 are closed, the gunfighter 3 should move upwardly at an angle to the right The CPU 41 calculates the appropriate location of the memory bank to directly generate the angularly oriented movement from the existing position, and in particular selects the gun fighter data to be placed in a corresponding block ob the RAM unit 28.

Referring particularly to Fig. 2, the player operated control means 15 and 16 establish binary logic signals which are read by the CPU 41 and symbols 3 correspondingly rewritten in memory unit 28. The patterns or symbols are programmed in the CPU program memory with suitable vector means 64 for presenting of the movable patterns in various positions or poses. For example, the gunfighter 3 and 4 may move vertically, horizontally and angularly. The speed of movement may be incorporated in the program to provide a single waLking or running movement which may also change during the play of the game, if desired.

The gunfighter writing program includes a plurality of different programs in which the gunfighter 3 is written in different poses such that by sequential invoking of the available programs causes the gunfighter to appear to realistically walk or run from one position to another. Thus, the vectoring means for each appropriate symbol includes means to store the last program written into the random access memory unit 28 and the location of the memory block by storing of the coordinates identifying the location of the symbol reference dot.

At the next calculation and updating, the symbol is completely erased from the memory unit 28, and rewritten with the appropriate program and relocated in the appropriate memory block corresponding to the block of TV dots to be illuminated by the scanning ;beam. The vector means 64 for the symbol stores the new location and last program written to remember rhe pose. The TV control unit 21 subsequently reads out such memory locations to correspondingly and properly energize the beam 22 within the screen block.

Thus, in a practical sequence, the CPU program 42 includes the sequentence d monitoring the player operator controls 15 and 16 for the symbols and then sequentially updating each symbol 3 and 4 in response to generation of an update interrupt signal.

The symbols in the illustrated embodiment of the invention include the gunfighters 3 and 4 which are programmed for three poses including a fixed standing position and second and third positions with the legs positioned forwardly and rearwardly to move realistically across the screen. The movement of the gunfighters 3 and 4 are determined by the player operated controls. In addition, the symbols may be machine changed in response to selected game occurrences such as shooting of an opponent gunfighter. For example, the gunfighter 3 may be caused to lay down in a horizontal position if shot by the opposing shooter 4. In addition, the wagon 11 is caused to move vertically across the screen by successive writing in appropriately shifted memory blocks in accordance with an internal program. Thus, the wagon 11 is rewritten during each complete cycle updating.Further, a bullet 6 shot through an obstacle such as the cactus 9 or 10 may cause the upper portion to be removed from the screen 2. In the latter case, the beam 22 may be directly blanked for erasing of the upper portion. If the wagon 11 is struck, the upper portion is removed directly, and then, because the wagon 11 is rewritten each update cycle, is replaced. Thus, the wagon 11 blinks off and on when hit. The central processing unit 41 in particular reads the encoding means and executes the appropriate software program, addressing via the bus 47 the appropriate random access memory 28 for transfer of data over data input bus 46 to the memory unit 28.

The screen display is rewritten periodically to simulate the presentation of actual movement on the fighting field in a realistic and interacting manner. In order to accomplish this result, the characters are, as just described, not only moved throughout the field but are activated to simulate the movements associated therewith; for example, during running motion the legs are moved and for directing of the bullet the arms move to reposition the gun. In accordance with the present invention, the previous position and arrangement of a symbol is stored temporarily in a temporary storage means prior to rewriting of new symbol and activation of the TV display accordingly. In the present embodiment the processor stores the necessary reference data in its scratch pad memory.

In particular, in Figure 2, a data latch 65 is connected to the parallel memory data output bus to receive data bit information corresponding to the data in random access memory 28 for the addressed location. The tri-state data latch unit is coupled via a connecting bus 66 to the central processing unit bus 41 for communication therewith which interprets the information for proper storage and rewriting of the symbol.

The selection of reading of the data in memory unit 28 or writing of data into memory is controlled by the central processing unit 41 through a read data select line 67 which is connected to the memory unit 28.

Each symbol employed is a fixed size and thus defined within a block of memory unit 28. The processor program memory includes a software program which completely rewrites the symbol within the assigned block size. In updating of a symbol, the processor erases the block of memory and completely rewrites the symbol in a new similar block to correspondingly move the symbol and simultaneously reposition the symbol in whole or in part in accordance with the programs in the program memory unit 28. As more fully developed hereinafter, the present invention preferably employs relatively low speed processor 30 for purposes of economy. The readout of a memory byte to the TV unit from the parallel to serial latch 35 develops an idle period while the bits are serially transmitted to the TV unit 21.The processor time for completing all the tasks necessary to properly interpret the input controls 15 and 16, the present symbol positions and the new positions as well as the game conditions, is created by providing a fifty percent duty cycle in which the TV display means and the processor alternate in accessing of the random access memory 28 both during the scan lines and during the horizontal and vertical retrace periods of the scanning beam which are of course idle periods during which the CPU 41 may use memory unit 28. The duty cycle is maintained during such periods to maintain a simple and inexpensive system.

Further, by accepting the horizontal line illustration of the symbols 3, 4, 9, 10 and 11, the circuitry and particularly the inter-related simplified controls are maintained. The addresses of the screen memory unit 28 which would be associated with scan lines is not employed to store display data but rather is employed as a scratch pad memory for the processor 41.

Thus, the random access memory unit 28 provides the dual functioning of storing a complete screen display over the operative portion, with the portion 48 employed in order to properly manipulate and calculate the necessary data for updating of memory unit in accordance with operation of the player operated controls and corresponding changing of the view on screen 2.

Generally in accordance with the present invention, the display control unit 29 initiates generation of a display frame and completes display of the information in memory unit 28 to establish one complete static visual presentation or picture. In the illustrated system, during one display generating frame, the processor 41 monitors the status of the input-output controls 15 and 16 and during the idle periods accomplishes the various data reduction and calculation tasks in the RAM necessary to reflect the action occurring. During a subsequent frame, the processor 41 updates the symbol by erasing and rewriting of the symbols. In practice, where a few large symbols are used, a single symbol is updated during an update frame period.This is particularly satisfactory where the various symbols may not require simultaneous movement of all or a significant member thereof and thus a series of frames may be generated before updating of the several symbols.

In summary, the TV unit 21 is driven to display the static image of the memory unit 28, with the rapid frame presentation, creating a typical live presentation of the stored image.

The TV control unit continuously and cyclic ally generates the frames essentially as a sepa rate and distinct enrity to produce the presenta tion and during the selected idle periods when the memory unit 28 is not needed releases the memory unit 28 to the processor. During such periods, the memory unit 28 and particularly the scratch pad memory may be addressed by the CPU 41. The display memory section or portion of the memory unit 28 is updated periodically in response to interrupt signals generated by the TV control unit during the period of the alternate update frame. The present invention may of course employ a suit able TV control means and processor which are adapted to communicate with the random access memory unit 28.

Although various systems may be employed to implement the present invention, a par ticularly unique and practical system is shown in Figs. 5-6.

Figs. 5, 5a and 6 illustrate schematic circuits of the elements shown in Fig. 2 particularly adapted for the gunfighter game. Generally, in Figs. 5--5a a processor system is shown which may be constructed as a universal basic circuit which is essentially adapted to be programmed for each game, with only the program memory of the processor changed to each particular game. Such program memory may of course employ commercially available program chips of the plug-in variety. An interfacing circuit, which is constructed for each particular game, is shown in Fig. 6.

In a practical implementation of the present invention the two basic circuits are therefore constructed on individual circuit boards, with the processor board forming a generalized board construction, and with the game logic board being uniquely and separately construc ted for each game.

In the illustrated embodiment of Fig. 5 the processor 30 includes the central processing unit (CPU) 41 having an address bus 47 con nected to the program memory unit 42 and having a read-write data bus 68 connected to a CPU multiplexer 69 for receiving and trans mitting of binary data words. The CPU 41 may be an Intel 8080 with the appropriate control input terminals including a ready 70, an interrupt 71, a hold 72, a reset 73 and a request 73a. The 8080 processor particularly employs 8 bit data words or bytes in communicaring with the associated control and memory devices and a 16 bit address word or byte.

The associated buses are correspondingly data and address bus lines. The CPU 41 is driven from a suitable clock unit 74, (Fig. 5). The operating sequence of the central processing unit is controlled by the program memory unit 42 which is preferably a suitable program unable read-only memory system such as that sold by the Intel Company and may include a plurality of memory chips 76, such as Intel 3604--6. The memory chips are suitably configured and interconnected to define the necessary software program control and further include suitable routing for writing of the several symbols as well as reading of the player control means and other control means and executing of appropriate programs.Each of the chips 76 is connected by address bus 47 to a decoder unit 77 for selecting one of the memory units 76 for readout. The decoder 77 is connected to the bus 47 with individual output lines to the several chips 76. The program memory chips 76 each has eight lines 78 coupled to a common instruction bus 79 and the appropriate eight bit instruction word is transmitted in accordance with the address word applied from the CPU 41 to the decoder 77 and the chips 76. The instruction bus 79 is hardwired to one of four inputs of a four to one multiplexer or decoder 80, shown consisting of four 74LS153 chips.The output of the decoder 80 is connected to one input & of the CPU input-output multiplexer unit 69 shown consisting of a pair of Intel 8216 chips 81 a. The multiplexer unit 69 has an output bus 82 connected to memory bus 46 and to I/O circuit shown in Fig. 6. The multiplexer unit 69 includes input-output lines 68 connected to CPU data ports and provides for transfer of data to and from the CPU 41.

The decoder 80 in addition to the instruction input 83 includes a RAM input 84 connected to the output of the RAM memory unit 28.

The second input to the decoder 80 provides for transfer of one byte from the RAM memory 28.

A third input 85 to the decoder 80 is connected to the game logic lines bus 86 from a game data multiplexer 87, shown in Fig. 6, for inputting of the encoded signals from the I/O unit 43.

The fourth input 88 to the decoder 80 is connected to a pair of interrupt signal lines 89 from the TV clock control assembly 32-34.

The interrupt signals are generated to instruct the CPU 41 to update one of the symbols, as more fully described hereinafter.

The decoder 80 includes a pair of binary selection lines 90 connected by a logic circuit 91 to the output of a status register 92 which continuously is in a state corresponding to the state of the CPU 41. The status register is connected to the data bus 82 and thus is set by the CPU 41 to create the necessary output control state.

The memory unit 28 (as shown in Fig. 5) is a random access memory and for purposes of economy and practical implementation of the present invention are preferably constructed as dynamic memory units such as those manu fractured and sold by Intel Corporation with the identifying number Intel 2107B. The memory cells are generally capacitor cell units which must be periodically refreshed in order to maintain the memory data. The memory unit as illustrated includes 16 memory chips 93 which are divided into eight bit first bank 94 of 8 chips establishing an eight bit output and a second bank 95 of 8 chips establishing an eight bit output connected to bus 96. Each chip is similarly constructed with a 12 bit address input connected to an address bus 97 as illustrated, with the connection to one element shown in detail.The address bus 97 also includes the write-read input 98 for correspondingly enabling of the cells.

The memory unit 28 and particularly the memory chips banks 94 and 95 are alternateçly enabled and driven from a separate TV dock unit 32. The output of the clock unit 32 is thus connected to a clock driver 98 the output of which is connected to simultaneously enable all of the eight RAM chips in either bank 94 or 95. The clock driver 98 thus has a pair of clock outputs 99 and 100 one of which is connected to drive the first bank 94 and the second of which is directed to drive the second bank 95. The clock driver 98 thus toggles between the two banks such that a first word or byte is taken from the first bank, the second byte from the second bank, the third byte from rhe first bank and so on.A single bank of RAM chips 93 is activated or turned on at any given time. This minimizes the power dissipation in the dynamic RAM construction and permits the memory cells to run at a minimum temperature. The toggle rate is such that each memory bank 94 and 95 is refreshed within the storage period. Similarly the dock driver 98, which requires substantial driving power, is selectively turned off to minimize the energy dissipation during the period or time that neither the CPU 41 or the TV control unit 29 is communicating with the memory unit 28, as subsequently described in connection with the addressing of the memory.

As previously described, the raster TV apparatus consists of a 256 by 224 matnix of display points requiring 7000 words and the scratch pad includes an additional 1000 words.

The memory chips 93 thus include a corresponding matrix of memory cells or approximately 64,000 bits. Each chip thus indudes approximately 4000 bits. The memory unit 28 is read out in eight bit bytes or words and thus defines eight adjacent points 24 in a scan line 23 on the screen 2. Further, 32 bytes are re quire to completely define each scan line 23 which as noted is 256 points long, and the memory includes approximately 8000 bytes which are alternately read out, one at a time, from the banks 94 and 95.

In addition to the address bus 97 and data output bus 96, a data input bus 1011 is provided forming an extension of the CPU data bus 46 from the CPU multiplexer 69. The bus 101 thus includes write data bit input lines 102 which are connected one each to the input data ports of the corresponding memory chips 93 in the memory banks 94 and 95. The particular cells into which the data is placed is defined by the CPU addressing of the memory unit 28 via the CPU address bus 47.

The RAM 28 as previously noted is selectlively addressed from either the TV control unit 29 or alternately from the CPU via the address bus 47. The TV control unit 29 in dudes a memory address generating means including a horizontal counter 33 and a vertical counter 34 which conjointly define each of the coordinates of the memory cells and related display points 24. The counters 33-34 are shown similarly formed by a pair of clock driven logic chips 104 and 105 such as sold by Intel with identifying number 74161 or 74LSlGl. The four counter chips are driven from the clock 32 which is connected to a common pulse source with dock 74 and provides sequential addressing of the RAM memories for readout d the cells and display thereof on the screen 2.The output of the counters 33-34 are connected as a set of address lines 100 to one input of the RAM address multiplexer 31, the second input of which is connected to the CPU address bus 47.

The multiplexer 31 is shown as a two to one logic circuit consisting of four 74157 or 74LS147 circuit chips 105, connected to the several elements d horizontal and vertical counters 33 and 34, and to the CPU address bus 47. The output d the multiplexer 31 is an address word 13 bits wide and is connected to the RAM address bus 101. The output thus includes the 12 bits to address the several bit chips in the two banks 94 and 95 and a writeread bit to port 98 to correspondingly enable the member unit 28.

As disclosed herein, the multiplexer in the various connections provides a convenient and practical means of coupling the various input and outputs to a single port. Other means such as latches can, of course, be employed. Further, where the CPU for example, has sufficient ports the several devices can, of course, be directly coupled without the use of such interfacing devices, with the processor, of course, appropriately programmed to read the ports.

These, and other similar concepts, can, of course, be employed within the basic concept herein of using the random access memory unit as the interface between the TV game display unit and the game input controls.

The horizontal clock counter includes a first bit line 106 connected to the parallel to serial data latch 35 via a logic circuit 106a.

As noted previously the clock driver 98 is only driven when the RAM unit 28 is being addressed. The address input words to the memory unit 28 include initial bit lines 107 which are coupled with a driver line 108 from the TV clock unit 29 in a logic circuit 109 to the RAM clock driver 98.

The multiplexer 31 further includes a select input 110 for each unit driven from a select line 111 from rhe TV clock unit and particularly horizontal dock counter 33. The TV clock unit therefore controls the state of the multiplexer 31 and establishes the priority in which the TV display reading has the highest priority. The CPU 41 therefore waits for the TV unit to release the memory unit 28 for communication with the CPU 41. The TV clock unit 29 is also connected to a horizontal blank unit 112 to generate the horizontal blank signal for blanking of the beam 22 during the horizontal resweep time period. A similar vertical blank unit 113 is connected to the clock unit to provide a corresponding vertical blank signal to blank the beam 24 during the retrace time 26.The several sync and blank signals are combined in a logic gate unit 114 haing a sync and blank signal summated with the data output on output line 115 in Fig. 5a to develop a combined video and sync control signal connected to the TV screen driver input 22. The line 115 is also connected to the output of the RAM unit 28 through the parallel-to-serial latch unit having its input connected to the RAM data output bus 96.

In the present invention the random access memory 28 and the CPU 41 are driven from the separate clocks 32 and 74 to permit operation d the two units at their maximum speed. The two devices which are prefereably selected based on practical consideration such as cost, reliability and the like, do not operate at the same speed in the illustrated embodiment and being totally asynchronous, cannot be conveniently driven from a common clock.

For example, in the preferred embodiment, the random access memory unit 28 selected operated at a speed of 800 nanoseconds while the CPU 41 operated at 500 nanoseconds. It is desirable to maintain the operation at its maximum speed to provide maximum available time to unit 41 in view of the significant numher of tasks assigned and which are completed in order to create optimum presentation.

The output of the RAM unit 28 appears on the data output bus 96 by encoding of the write-read line 98 to read. The data output bus 96 connects to a CPU latch 117 of the display latch means 65 in Fig. 2. The data latch 1X17 includes a parallel to parallel latch unit shown consisting of a pair of LS174 register latches. The display latch means 35 is a parallel to serial number 166 latch unit The serial to parallel latch 35 has its select line 11l8 connected by a logic circuit 119 to the horizontal and vertical counters 104 and 105 and its clock port and line 120 connected via logic unit 106a to the counter line 106 of the TV display dock system.The TV clock system thus enables the latch 35 to store the eight display bits and to serially tranunit the bits from the serial output port and line which is connected to the TV input signal line 115 and thus to port 22. The TV clock counters out puts are connected to the sync and blank logic circuit having the sync and blank output line which is ruminated with the data line at line 1115 to form the common input to the TV input port of Fig. 2.

In Fig. 5, a horizontal blank flip-flop logic gate 112 and a vertical blank flip < flop logic gate 113 are set by the counters. The outputs are combined in the logic circuit 114 to establish the appropriate blanking signals.

Under normal sequencing operations, the TV dock system drives the addressing counters 33 and 34 to sequentially address the memory locations, docks the memories to transfer the data into the parallel to serial latch 35. When the 8 bits of information are transferred into the latch the memory unit 28 is released for use by the CPU.

During this period, the parallel to serial latch 35 is outputted in synchronism with the TV sync and blank signal from logic unit 114 to the television set 21 for correspondingly energizing ob the scanning beam 22 in accordance with the information stored in memory.

The parallel to serial latch 35 is clocked in synchronism to maintain proper synchronism between the transmittal of information and the positioning of the scanning beam 22. At the end of transmission of the eight data bits, the TV clock and addressing system automatically accesses the RAM unit 28 to read the next display data byte and transfer it to the parallel to serial latch for another display of such successive byte.

In the illustrated embodiment of the inven tion with eight bit wide bytes, 32 bytes are read for each horizontal scan line. At the end of rhe line, the horizontal iblanking signal is set by dip-flop register 1152 and the beam is blanked during the horizontal retrace time. A new scan line cycle is again initiated with the horizontal counter and the vertical counter appropriately adjusted for generating the addresses for the new line.

As previously noted, the TV control has a priority in the hierarchies of the operating sys tem. When the CPU 41 requests access to the RAM memory, the CPU 41 must wait until the TV control unit releases the memory unit 28. The CPU 41 operates at a slower speed and after access to memory unit 28 is captured does not actually execute the step until the RAM introduces a signal indicating the synchronous state of the units and particularly that the data is on the input of the decoder. The CPU 41 may address the memory unit 28 while the TV display control is also addressing the memory unit 28. When the TV display control releases the memory unit 28, the multiplexer 31 connects the CPU address bus 47 to the RAM address bus 97 and the appropriate eight bits of memory data appear on the data bus 96.The data is placed on the inputs to the CPU parallel to parallel latches 117 and are latched by a synchronizing logic circuit 121.

The synchronizing logic circuit 121 is enabled by the CPU 41 request for data from memory and when the data information is latched, the logic circuit 121 transmits a ready signal to the ready port 70 of the CPU unit 41 via a line 122. The CPU 41 then terminates the "wait" state and proceeds to execute the program for which the data was requested.

The memory unit 28 is directly released to the CPU 41 between each of the display data bytes as well as during each of the horizontal and vertical beam retrace periods. Thus, during these periods the CPU 41 may address the scratch pad portion of the memory units 28.

The pair of Us174 latch registers 117 provides additional input-output logic and lines in addition to the eight data lines. The available portion of the latch which signals the synchronizer, indicates the condition of the latches and particularly the readiness to transmit data to the CPU 41. When the CPU 41 has requested communication with the memory unit 28 and receives the ready signal, the appropriate instruction is forwarded to the decoder 80 to transfer the data through the multiplexer 69 to the data inputs of the CPU 41.

In addition, the CPU 41 interrupt 71 is set periodically to initiate updating of the symbols.

In the illustrated embodiment of the present -invention, the TV display control unit 29 and parricularly the clock system is connected to an interrupt logic circuit 123 to generate a pair of update interrupts. The one interrupt occurs at the middle of a display frame and the second interrupt occurs at the end of the display frame. The first interrupt provides for updating symbols in the upper half of the screen 2 and the second interrupt for updating symbols in the lower haff of the screen 2. The interrupt is binary encoded on a pair of inter rupt encoded lines 124 and 125 from the interrupt logic circuit 123. The encoded lines are connected to fourrh input 88 of decoder 80.

A line 127 is connected to an interrupt latch 126, shown as a LS174 flip-flop, the second of which is connected to the interrupt part of the CPU 41.

The CPU 41 reads the interrupt input of the decoder 80 to determine which interrupt is being processed for appropriately updating of the symbols of the gunfighter 3 and 4.

By initiating the interrupt singal for the upper portion of the screen after writing of such portion, the CPU 41 has the period during the writing of the lower portion of the screen to execute the various tasks for writing of the new symbols. Thus, the CPU 41 may communicate with memory units during the TV idle time. Further, as noted previously, the duty cycle of the next scan frame is employed as the time available to complete the updating of the one symbol. If the upper screen does not contain a symbol requiring updating, the 'CPU 41 acknowledges the interrupt and proceeds to other tasks. Upon generation of the second interrupt, the CPU 41 initiates the update program for the lower portion of the screen 2. Thus, by employing the dual inter rapt the total available update cycle time is increased.

The required updating is determined by the operation of the control means 15 and 16 by the players, as well as other special interrelated controls as shown in the game logic board of Fig. 6.

Referring particularly to 'Fig. 6, the game logic board generally includes multiplexer 87 for transmitting of the setting of control means 15 and 16 and other game inputs to the CPU 41 and for driving of the reinforcing visual and sound devices 45a. Additionally, a special data bit shifter 128 is provided for selectively shift.

ing of the bits in a symbol byte to properly define a syntboi, as hereinafter developed. More particularly, the various control switches 48 50--54 and 60-63, as shown in Figs. 3 and 4, for the gunfighter 3 and 4 are coupled as first and second sets of inputs 129 and 130 o the four to one multiplex 87 which has its out.

put lines 131 connected to bus 86 to the CP decoder 80 of Fig. 5. The third input 132 oi the multiplexer 87 receives game condition control data from a bank of manually set switches 133. Finally, the pattern or symbol byte shifter circuit or unit 128 is connected to the fourth input 134 of the multiplexer 87.

The CPU data bus is connected to the shifted 128 and to an output signal latch 135.

In the illustrated embodiment, the multi.

plexer 87 and the shifter 128 and an output reinforcing latch register unit 135 are coupled to the CPU 41 through three bit address line.

136 driven from the CPU 41. The three input bit lines 136 have two inputs to the mulriplexer 87 for selecting one of the four inputs to be transmitted over the right bit output lines 131.

The two address lines 136 connected to select inputs of the decoders provide binary encoding of the multiplex unit 87 for selective coupling of the output lines 131 to any one of the eight lines of the four inputs 129-134 and thereby permit the sequential transfer of data and information to and from the central processor unit 41 for the lines 136 are also con nected to the shifter 128 and to the latch 135 through logic gates 137 as clock lines for appropriate transfer of data to and from the CPU 41. The data decoder or multiplexer 87 is shown formed from four LS153 register units 139 each of which includes a pair of four input decoding units and thus provides a total of eight input signal bits for each of the four data multiplexed inputs and a corresponding eight output signal bits connected to lines 13.

The user operated control means 15 and 16 each provide eight input signals, in the form d open or closed switches, defining the complete demanded change of a player. The several inuut signals are shown connected to the several inputs via suitable pulse shaping circuits 140, such as suitable opto-isolators. The switches of controls 15 and 16 are similarly connected to the first and second bank of inputs 129 and 130. The connections for control 15 are described for purposes of description.

More particularly, the raise switch 61 for gunfighter 3 is connected to the corresponding first input. The closing of the switch 61 generates a suitable logic pulse as an output binary logic signal which is read by the processor upon encoding of the multiplexer to output the data for gunfighter 3.

The downward movement switch 63 for the gunfighter 3 is connected to the second line of the first decoder input and the right and left movement switches 60 and 62 are connected to the third and fourth lines of such first input 129. The three coding switches 52, 53 and 54 for the position of the gunfighters arm 19 are similarly connected to the multiplexing fifth, sixth and seventh lines of input 129. The eighth line of the first input 129 is connected to the trigger switch 48 for firing of bullet 6 by gunfighter 3. When the CPU 41 program steps to read the controls, the address lines 136 encode rhe multiplexer to output the signals on the first input which are thus transmitted via lines 131 and the bus 86 to the corresponding input 85 of the CPU encoder 80.The CPU 41 reads the data via the multiplexer 69 and the data read/write data lines 68 for appropriate processing and updating of the memory unit 28.

The second input 130 similarly provides for reading of the actuation of the control means 16 for gunfighter 4.

The eight lines of the third input 132 of the multiplexer 87 are coupled to coin and game time control switches, as presently described, and set the conditions for initiating and continuing of play. A pair of coin switches 141 and 142 permit encoding of the game to require insertion of anywhere from one to four coins in the coin receiver 14 to condition the game for operation. Thus, the pair of switches may provide a series of binary codes requiring one, two or three coins to condition the game for play. The switches 141 and 142 are connected to the first and second lines of input 132 and to a logic supply circuit 143.

Credit for proper coinade input as set by switches 141 and 142, is determined by a pair of switches 144 and 145 connected to the third and fourth lines of the third input 132.

The switches 144 and 145 similarly provide encoding of game credits for any given number of coins. CPU 41 maintains a continuous record of the number of coins introduced and the number of games remaining to be played before all of the inserted coinage have been used up.

A further pair of switches 146 and 147 permits encoding of rhe game into different playing times. The switches are shown connected to the fifth and sixth lines of the third input 132. A nominal minimum game period might exist for 60 seconds but it might well be desired to extend the games to 90 or 120 seconds.

The seventh and eighth lines of the third input 132 are connected to signal logic inputs 148-149 related to receipt of a proper coin and the initializing of rhe processor system for initiating the game time. The coin input switch signal is derived from the coin input unit 14 to ensure starting from an initial position.

Thus, each inserted coin is recorded in a suitable register, not shown, and the game apparatus enabled in accordance with the coin setting and credits condition prescribed by the switches 144-147.

Finally, the eight lines of the fourth input 134 of multiplexer 87 is connected to the ight output bit lines 150 of the data shifter unit 128.

The shifter 128 is a variable bit shifting means for rapid shifting of the bits in a data word or byte by a program control amount.

The shifter 128 is employed to shrift the symbol word bits where the positioning of the symbols is offset from actual byte distribution across the screen. Thus, each symbol is encompassed within a block of scan points. Thus, relatively large symbols such as the gunfighter and wagon may be three bytes wide. The screen 2 and memory unit 28 are similarly 32 bytes wide. If the symbol side limits co 3nude with the limits of any three bytes, the symbol could be directly placed and removed from memory. Such may infrequently occur.

Generally, however, the symbol will be shifted by anywhere from one to seven bits and the three symbol defining bytes are spread over four adjacent memory and screen bytes. The symbol bits must then be shifted to properly locate the symbol bits in memory unit 28.

Although the CPU 41 can include the appropriate software program to provide the necessary shift, such an approach would unduly burden the CPU and in particular absorb an unacceptable amount of processor time for the commercially practical apparatus such as shown for the preferred embodiment.

The illustrated shifter 128 includes a pair of cascaded latch stages 151 and 152 in which first and second sequential bytes of data are sequentially placed. The outputs appearing at lines 150 are derived from the 16 output bits of such two bytes to provide a byte with the bits shifted. The amount of shift, up to seven bits, is set by a latch unit 153 which is pro grammed by the CPU 41 in accordance with the desired location of the symbol on the screen 2. More particularly, the first shifter stage 151 includes four separate LS175 latches 154, each having up to six inputs, two of which are derived from the CPU data bus 68.

The output lines 155 of the first stage are connected as inputs to the second stage 152 and also back to other inputs of the first stage as at 156 to develop additional inputs to the second stage 152. The two outputs of the first stage 151 are thus paralleled and the output of the second-stage 152 define the complete 16 bits of adjacent display bytes. The second stage 152 is shown including four similar decoders 157 identified by the number AMD 25S10 having eight input bits and four output bits.

The decoders 157 have three bit selection code lines 158 connected to the CPU pro grammed shift latch 153.

The CPU 41 thus calculates the amount of shift required and correspondingly sets the latch register 153. The data bits for each byte are then directly shifted accordingly as a result of the hardwired instruction that the signal bits appearing at the particular input ports are taken out at a different and properly shifted output port. The eight bit shifted byte is transmitted to the CPU 41 via the data multiplexer 87 and the output lines to the CPU bus 86. This is an extremely practical consideration where large amounts of shift will be required such as where a large number of symbols are used or where each symbol is large such that reasonably large shift values may be required. Thus, a symbol may require up to 100 data bytes, each of which is to be shifted.In the illustrated embodiment, when updating the memory, the latch 153 is set once and the symbol bytes are each directly properly shifted. If a software program were employed, the processor time would be so extreme as to prevent a desirable display, and particularly where larger values of shift were required.

The shifter 128 therefore particularly adapts the system to the use of a relatively slow and therefore commercially practical processor 30.

The visual and audible outputs are transmitted to the output latches 135 from the CPU data bus 68 and the connected game logic board lines 151.

The output of the one latch 135 is connected to a decoder 159 having six individual drivers to a sound generator 160 for driving a pair of speakers 161 and 162. Thus, each firing of a bullet may generate a programmed sound. The second latch 135 Provides for driving of mis ceilaneous recorders and indlcators in accord ance with the game program. The second latch 135 is shown for example developing outputs for driving of a coin counter 163, a credit counter 164 and a game over lamp 165.

The circuits shown in Figs. 5 and 6 thus provide a preferred embodiment for the gun fighter game. The circuits can, of course, be readily adapted to any other game by merely providing an appropriate programming of the CPU program memory unit 42 and providing of the necessary modification to the game logic circuits for the input and output signals re quire for such game.

The preferred embodiment includes various unique features which are significant in the construction of a basic system for many differ ent games. Various modifications of this pre ferred embodiment may of course be in - corporated. For example, if the tasks required of the processor are not as great as in the illustrated game, or a higher speed processor is used, each of the scan frames may be used for display to develop a grearer resolution in the symbols. Similarly, the shifter is most im portent where large symbols are used requiring large amounts of shifting. Consequently, such detail may be eliminated and a software pro gram shift employed if desired. If the pro cessor and RAM memory unit operate at the same or some even multiple of time, a single clock may be employed. These and similar other important features may or may not be employed biased on the particular game and time parameters. In summary, in the imple menting of the invention, various processor and display control of any desired design may be employed which are adapted to essentially independent operation with a random access memory and where the random access memory functions as the interfacing means for provid ing interdependent functional relationships in the playing of the game apparatus.

In the 'illustrated embodiment of the inven tion various multiplexing units are employed for establishing multiple inputs and outputs to the processor and to the memory. Although multiplexers employ a very convenient struc ture where the associated devices have limited input and output ports, the present invention can be employed with direct port connections where available. Thus, a processor might be employed with individual ports connected directly to the data and address channels with the appropriate internal latches and selection.

In rhe illustrated embodiment of the inven tion, a single memory is provided to provide the game presentation in black and white. The game apparatus can be directly modified for colored presentation. In this aspect of the invention, three memory planes would be em ployed, one for each of the basic colors with a master controller to provide the necessary and desired interrelationship of the reading of the various planes. Further, if desired, the color could be basically shades of gray with each dot provided with more than one identifying bit of intersity memory. If such concept were employed to the color schematically there would be three memory planes for each color.

Further, within the broad concept various processors could be employed for the various functions with the intelligence requirements distributed in a logical manner and under the control of a master controller or processor. In multiple systems, for example, a microprocessor might be employed to control the bit shift depending upon the relative time and costs requirements.

The illustrated embodiment of the invention as well as the suggested modifications and the like are all directed to practical implementa tion of the very basic concept d employing the duly addressed memory means which functions as a direct and unique interfacing between the player operated game controllers and the like to and with the completely separately operated display means. As previously noted, this separation d the game into two distinct separate components operating as separate entities and with the memory as the only com mon interfacing not only permits a relatively law cost, versatile game apparatus but uniquely adapts such TV game apparatus to a simple, inexpensive and readily implemented conver sion of a basic structure to various games.

The illustrated embodiment provides a highly significant improvement in the practical implementation with present day technology but the various steps and functions may, of course, employ any other suitable apparatus which can provide the desired functioning.

The present invention thus provides a reli able and relatively inexpensive TV game apparatus particularly adapted to commercial production.

WHAT WE CLAIM IS: 1. A player-operated game apparatus for use with a display means having an intensity con trol means for varying the intensities of picture elements for the presentation of movable sym bols on a screen, said apparatus having player operated means including input elements adap ted to be operated by a player and signal means actuable by said input elements, for enabling interaction of the player with the symbols on the screen, digital display memory means for storing in a digital form a set of digital bits representing the intensities necess ary for generating a display on said screen and locating the symbols within the display, display controller means for addressing said display memory means and reading bits in the display memory means in time-spaced read periods separated by reading idle periods, said display controller means being adapted for connection ro said intensity control means of the display means to transmit the bits read to said intensity control means to present the desired display stored in said display memory means, a processor, program means, communicating port means for connecting the signal means of the player-operated means to the processor, said processor having means for accessing said program means and said display memory means to represent symbols in response to said signal means and said program means wherein the processor modifies digital bits ad the symbols to the display memory means to revise the symbols within the display, and control means operatively connected to the display controller means, for operatively coupling the display memory means to the processor during said reading idle periods to change said display memory means between said read periods.

2. The apparatus of claim 1 wherein said display controller means further includes a memory address generating means and a control signal means for signaling the initiation of a read period, said processor includes a memory address bus, and said control means comprises an address multiplexer operatively coupled to the display memory means and also operatively coupled to the memory address generating means ob the display controller means and to the memory address bus of the processor and operatively coupled to rhe control signal means of the display controller means to control the coupling ob the display memory means to the display controller means and to the processor so that said display controller means can address said display memory means during said read periods and said processor is operatively coupled to said display memory means only during said reading idle periods.

3. The apparatus of claim 2 wherein each groups ob bits in the display memory means has an address and the memory address generating means comprises a plurality of counters for generating sequential memory addresses whereby each group od bits may be addressed and read in sequential fashion.

4. The apparatus of claim 3 wherein bits in the display memory means are arranged in matrix form so that each group of bits has a horizontal and a vertical address and the plurality ob counters includes a horizontal counter for generating the horizontal address and a vertical counter for generating the vertical address of each group of bits.

5. The apparatus ob claim 1 wherein said program means includes symbol memory means having a set ob bits representing the intensities necessary for generating for each symbol a display of said symbol on said screen.

6. The apparatus of claim 5 wherein the processor has means for modifying the location of the bits of the symbols by erasing the bits located in the display memory means associated with a symbol and transferring the bits associated with said symbol from the symbol memory means to a second location within the display memory means in response to said signal means and said program means.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. color could be basically shades of gray with each dot provided with more than one identifying bit of intersity memory. If such concept were employed to the color schematically there would be three memory planes for each color. Further, within the broad concept various processors could be employed for the various functions with the intelligence requirements distributed in a logical manner and under the control of a master controller or processor. In multiple systems, for example, a microprocessor might be employed to control the bit shift depending upon the relative time and costs requirements. The illustrated embodiment of the invention as well as the suggested modifications and the like are all directed to practical implementa tion of the very basic concept d employing the duly addressed memory means which functions as a direct and unique interfacing between the player operated game controllers and the like to and with the completely separately operated display means. As previously noted, this separation d the game into two distinct separate components operating as separate entities and with the memory as the only com mon interfacing not only permits a relatively law cost, versatile game apparatus but uniquely adapts such TV game apparatus to a simple, inexpensive and readily implemented conver sion of a basic structure to various games. The illustrated embodiment provides a highly significant improvement in the practical implementation with present day technology but the various steps and functions may, of course, employ any other suitable apparatus which can provide the desired functioning. The present invention thus provides a reli able and relatively inexpensive TV game apparatus particularly adapted to commercial production. WHAT WE CLAIM IS:

1. A player-operated game apparatus for use with a display means having an intensity con trol means for varying the intensities of picture elements for the presentation of movable sym bols on a screen, said apparatus having player operated means including input elements adap ted to be operated by a player and signal means actuable by said input elements, for enabling interaction of the player with the symbols on the screen, digital display memory means for storing in a digital form a set of digital bits representing the intensities necess ary for generating a display on said screen and locating the symbols within the display, display controller means for addressing said display memory means and reading bits in the display memory means in time-spaced read periods separated by reading idle periods, said display controller means being adapted for connection ro said intensity control means of the display means to transmit the bits read to said intensity control means to present the desired display stored in said display memory means, a processor, program means, communicating port means for connecting the signal means of the player-operated means to the processor, said processor having means for accessing said program means and said display memory means to represent symbols in response to said signal means and said program means wherein the processor modifies digital bits ad the symbols to the display memory means to revise the symbols within the display, and control means operatively connected to the display controller means, for operatively coupling the display memory means to the processor during said reading idle periods to change said display memory means between said read periods.

7. The apparatus of claim 6 wherein the

means for accessing said program means and said display memory means includes means for reading the bits from the symbol memory means in parallel groups defined by a predetermined number of bits, said apparatus further comprising shifting means operatively coupled to the processor for shifting the bits of the groups read from the symbol memory means a number of bit positions within the groups as determined by the processor and means for transferring the bits in groups from the shifting means to the display memory means.

8. In the apparatus of claim 7 wherein a group of bits comprises a byte and two success ive bytes are read from the symbol memory means to the shifting means, said shifting means comprising means for shifting the two bytes and for selecting appropriate bits from the two bytes to form an appropriate byte to store in the display memory means.

9. The apparatus of claim 5 wherein a symbol has a plurality of different poses, said symbol memory means having a set ob digital bits representing the intensities necessary for generating a display of the plurality of poses on said screen for said symbols having a plurality of poses.

10. The apparatus of claim 1 wherein said display controller means includes an interrupt signal means; said processor including interrupt port means connected to the interrupt signal means; and said processor being responsive to said interrupt signal means for writing of bits associated with a symbol in the display memory means.

11. The apparatus of claim 10 wherein the display means generates time-spaced display frames, and the processor erases the bits associated with a symbol and writes in the display memory means bits associated with a symbol during periods of alternate frames.

12. The apparatus of claim 8 wherein said symbols are defined by a selected block within the symbol memory means, at least one of said symbols and blocks being a plurality of bytes wide, said display memory means also having blocks therewithin, said shifting means comprising a hardwired bit shifter for shifting the bits in a symbol byte for transfer to a block within said display memory means and having shift level means for setting the number of bit shifts for each byte, said processor being connected to the shift level means and setting said shift level means for the number of bit shifts to locate the symbol bits in the proper display memory means blocks.

13. The apparatus of claim 1 comprising means for operating said display controller means at a first rate and means for operating said processor at a second rate whereby said processor can operate at a relatively slow rate while maintaining a relatively complete and accurate presentation of a symbol moving with- in the display on a relatively high speed raster scan screen.

14. The apparatus of claim 1 further including a data latch means for latching a plurality of bits from the display memory means to the processor, and a synchronizing means controlled by the display controller means for setting of said latch means, said processor having a wait state established in response to a request for the display memory means and having a ready port connected to said synchronizing means, and said synchronizing means having means connected to the ready port of the processor for producing a ready signal upon the completion of setting of the latch means.

15. The apparatus of claim 1 wherein said display memory means includes a plurality of additional locations defining a scratch pad memory means.

16. The apparatus of claim 10 wherein said display controller means includes a sync and blank signal means for blanking the scanning beam during horizontal and vertical retrace said reading idle period occurring during said horizontal and vertical retrace and a clock means connected to actuate the sync and blank signal means and the interrupt signal means.

17. The apparatus of claim 15 wherein a symbol may have a plurality of different poses, each of which is stored as bits in the program means, and said processor includes means for storing a representation of the last written symbol pose in the scratch pad memory means, for calculating a new symbol pose, and for storing bits representing the new symbol pose in said display memory means, whereby the symbol in the display is repositioned and redrawn to simulate realistic symbol movement.

18. The apparatus of claim 17 wherein said processor in representing a new presentation of a symbol in the display memory means has means for completely erasing the bits of the previous symbol and for storing the bits of the new presentation of the symbol.

19. The apparatus of claim 4 wherein said display means includes a screen having a matrix pattern difined by pluralities of dots, said plurality of dots each having horizontal and vertical co-ordinates on the screen corresponding to the horizontal and vertical addresses of a plurality of bits in the display memory means.

20. The apparatus of claim 4 wherein said control signal means comprises said horizontal counter, and said display controller means further comprises a clock means for providing clock pulses to said address generating means and to said display memory means.

21. The apparatus of claim 11 wherein said processor includes vectoring means for storing reference data for selected symbols in a previous display frame, and said processor having means for storing bits representing a new symbol in said display memory means in accordance with the actuation of said signal means of the player-operated control means to move said symbols within the display in accordance with the movement of the player-operated means and the presentation in the previous display frame.

22. The apparatus of claim 1 including sets of player-operated means for each player, and having a game logic multiplexer having a plurality of multiple bit input means and a multiple bit output, each of said input means being connected to sample one set of said player-operated means in response to the processor.

23. The apparatus of claim 1 wherein the bits are read a group of bits at a time, said apparatus further comprising serializing means for serializing the groups of bits so that a bit at a time is transmitted to the intensity control means.

24. The apparatus of claim 7 wherein the shifting means includes two cascaded latch stages.

25. The apparatus of claim 1 wherein the display memory means includes dynamic memory means for each location within said display memory means, said dynamic memory means being separated into a plurality of groups each of which groups produces a group of bits, and a clock driver for sequentially and cyclically enabling said plurality of groups.

26. The apparatus of claim 1 wherein said display memory means includes a plurality ob memory chips arranged in columns, each cul- umn including a chip for each bit, said memory chips being dynamic memory chips, a driver being connected to the chips in each column for alternatively refreshing and enabling the columns of memory chips, and a logic means connecting said driver to said addressing means for refreshing and enabling of said columns of memory chips during the read periods so that group of bits may be read from a column of memory chips during a read period.

27. The apparatus of claim 1 wherein the means for accessing said program means and said display memory means accesses bits in groups defined by a predetermined number of bits, said apparatus further comprising shifting means operatively coupled to the processor for shifting the bits of the groups a number of bit positions within the groups as determined by the processor.

28. A game apparatus for presentation of game symbols comprising: a raster scan television screen unit having an intensity control means for controlling the intensity of a beam, and generating display frames each of which includes a plurality of spaced scan lines of a plurality of display points; a clock means driving a sync and blank means for blanking the beam during horizontal and vertical retrace periods; a processor having a program means which has an instruction bus, said processor having an address bus connected to said program means;; a random access memory having a memory address bus and having a first plurality of memory locations for storing in digital form a set of digital bits representing the intensities necessary for generating a display on said screen and locating the symbols within said display and having a second plurality of memory locations defining a scratch pad for said processor and having a data output bus and a data input bus; a display controller means, having an address bus, for addressing said random access memory and reading the set of bits in said random access memory;; an address multiplexer having a display controller address input connected to the address bus of the display controller means and a processor address input connected to the address bus of the processor and an address bus output connected to said random access memory address bus and said address multiplexer being connected to said display controller means for coupling the display controller address input to the address bus output during each address by the display controller means Of the random access memory, and the processor address bus input therebetween, said display controller means, having a serializing means connected to said data output bus of the random access memory, said display controller means having means for addressing said random access memory and reading a byte set Of bits in the random access memory associated with a symbol in time-spaced read periods separated by reading idle periods and storing the byte in the serializing means, said display controller means being adapted for connection to said intensity control means of the raster scan display means to transmit the bits from said serializing means to said intensity control means and present the 'desired display stored in said display memory means; a plurality of sets of player-operated means, each set of player-operated means including input elements adapted to be operated by a player and digital encoding means for encoding movement of the input elements;; an interrupt logic means connected to said display controller means for generating memory update signals, a data decoder having a first input connected to the instruction bus, a second input connected to the memory data output bus, a third input connected to the player-operated means a fourth input connected to the interrupt means, and an output, and said data decoder being operatively connected to the processor for connecting an input to the output as determined by the processor; a processor multiplexer having an input bus connected to the output ob the decoder and having a data output bus connected to said memory data input bus and having a read write bus connected to said processor, and operatively connected to the processor for connecting the read-write bus to the input and output bus as determined by the processor; and said processor having means in response to said memory update signals for addressing said program means and said random access memory to represent the symbols in response to sad digital encoding means and said program means whereby the processor modifies the location of the digital bits of the symbols in the random access memory thereby relocating the symbols within the display.

29. The apparatus of claim 28 having a game logic multiplexer having a plurality of multiple bit inputs and a multiple bit output, each of said inputs being adapted to read one set of said control means.

30. A player-operated game apparatus for use with a raster scan TV display means for presenting movable symbols in a plurality of serial frames on a TV screen, said apparatus having a player-operated means for enabling interaction of the players with the symbols presented, an interfacing means for providing a memory of representations of rhe symbols and locations of the symbols in the frames, a display controller means for reading the memory of the interfacing means and transferring the representation of the symbols to the raster scan TV display means for presentation on the TV screen, and a programmed processor for updating the memory of representations of the symbols od the interface means in response to the player-operated means, and said interfacing means further providing an interface between the display controller means and the pro granunmed processor so that said display controller means and said programmed processor can operate independently of each other.

31. The apparatus of claim 30 wherein said memory of said interfacing means comprises three memory planes, each memory plane comprising means for storing the representation ol the symbols and locations of the symbols in one of the three basic colors for presentation of the symbols on the color TV display means.

32. A player-operated TV game apparatus comprising the combination of parts arranged and adapted to operate substantially as hereinbefore described with reference to the accompanying drawings.