CA1141029A - Nonvolatile static random access memory devices - Google Patents

Abstract

NONVOLATILE STATIC RANDOM ACCESS MEMORY DEVICES

ABSTRACT
Nonvolatile, semiconductor random access memory cells comprising a static, RAM cell and a nonvolatile memory element which may be interconnected with the static random-access memory cell by capacitative coupling, such that the RAM cell contents may be directly copied to the nonvolatile element, and such that the nonvolatile memory cell contents will be copied to the RAM cell upon applying power to the RAM cell. The nonvolatile memory element may be a substrate-coupled floating gate cell incorporating self-regulated and asperity enhanced tunnel currents.

Description

NONVOLATILE STATIC RANDOM ACCESS METHOD AND MEMORY DEVICE
; ' ' ' The invention relates generally to the field of metal-oxide semiconductor random access memory systems (MOS RAMs~, and more particularly to nonvolatile static S RAM systems incorporating an integrated floating gate circui~ element.
Many static RAMs employ bistable semiconductor - circuits such as flip-flop circuits as memory cells for storing binary data tones and zeros). For such static memory cells to store information, electrical current from an electrical power source must continually flow in one of the two cross-coupled circuit branches, and be relatively absent from the other branch. Two (binary) distinguishabl2 mémory states for information storage lS are thereby provided, depending upon which branch is conductive, and which branch is correspondingly -nonconductive. Accordingly, such semiconductor memory cells are considered to be "volatile" because if electrical power is removed, the memory state distinguishing current will cease to flow in the current carrying branch, and the information in the cell is accordingly lost. Such volatility is a substan~ial disa~vantage of conventional semiconductor memory systems, and substantial effort in the art has been made to develop circuit elements and structures for providing nonvolatility to semiconductor circuits wheh power is removed [E. Harari, et al., "A 256-Bit Nonvolatile~ _ ll~lOZ~

Static RAM", 1978 IEEE International Solid State Circuits Conference Digest, pp. 108-109; F. Berenga, et al. "E -P~OM TV Synthesizer", 1978 IEEE Internationa~
Solid States Circuit Conference Digest, pp.l96-197; M.
Horne, et al., "A Military Grade 1024-bit Nonvolatile Semiconductor RAM", IEEE Trans. Electron Devices, Vol.
ED-25, No. 8, (1978), pp. 1061-1065; Y. Uchida, et al., "lK Nonvolatile Semiconductor Read/Write RAM", I~EE
Trans. Electron Devices, Vol. ED-25, No. 8 (1978~, pp.
1065-1070; D. Frohmann, A Fully-Decoded 2048-Bit Electrically Programmable MOS-ROM", 1971 IEEE-International Solid State Circuits Conference Digest, - pp. 80-81; U.S. Patent No. 3,660,819; U.S. Patent No.
4,099,196; U.S. Patent No. 3,500,142; Dimaria, et al., "Interface Effects and High Conductivity in Oxides Grown from Polycrystalline Silicon", Applied Phys. letters (1975), pp. 505-507; R.M. Anderson, et al., "Evldence for Surface Asperity Mechanism of Conductivity in Oxide Grown on Polycrystalline Silicon", J. of Appl. Phys., Vol. 48, No. 11 (1977), pp. 4834-4836].
Devices based on the MOS floating gate structure are conventionally used for systems having prolonged data retention. A floating gate is an island of conducting material, electrically insulated from the substrate but capacitively coupled to the substra~e, forming the gate of a MOS transistor. Depending on the presence or absence of charge on this floating gate, the MOS transistor will be rendered conductive ("on") or non-conductive ("off"), thus forming the basis for memory device storage of binary "1" or "0" data corresponding to the presence or absence of floating gate charge. Various means of introducing and removing the signal charge from the floating gate are known.
Once the charge is on the gate, it remains permanently trapped, because the floating gate is completely _3_ - surrounded by an insulating material which acts as a barrier to the discharging of the floating gate.- Charge can be introduced onto the floating gate using hot electron injection and/or ~unneling mechanisms. Charge can be removed from the floating gate by exposure to radiation (uv light, x-rays), avalanche injection, or by so-called tunneling effects. The term tunneling is used herein in a ~road sense to include the emission of an electron from the surface of a conductor into an adjacent insulator through the energy barrierO
Nonvolatile static RAM memories are known which incorporate a floa~ing gate nonvolatile element utilizing very thin gate oxide, but such devices have a number of disadvantages. Charge is tunneled to and from a floating gate element bidirectionally through a relatively thin (50 Angstroms - 200 Angstroms) oxide which may be difficult to reliably`manufacture with ~ ade~uate integrity. Because of the bidirectional - character of the very thin tunnel oxide, the nonvolatile RAM cell may be subject to possible disturb problems - which cause the memory to lose its contents. In particular, such problems may involve limitations in the number of read cycles, and disturbances in the memory - contents of a cell being caused by adjacent cell operations. Other nonvolatile ~AM devices do not use ~loating gates but rather a metal nitride-oxide semiconductor structure in which charge is retained at a silicon nitride, silicon dioxide interface. However, ~ such MNOS devices also have disturb problems which limit ; 30 not only write cycles hut also read cycles, causing limitations on the wide-spread use of MNOS devicesO
It is desirable to interface a nonvolatile element to a RAM circuit to provide nonvolatility in a semiconductor memory array. However, known interfaced devices have various substantial disadvantages. For example, such interfacing may be carried out by introducing a conductance imbalance caused by the nonvolatile elemen~ directly between the two branches of a cross-coupled static RAM cell. However, such conductance imbalance causes the cross-coupled static - RAM cell to carry a DC offset current which must be overcome when the cell is in normal RA~ mode operation, and such imbalances can lead ~o read and write disturb marginalities for the overall memory circuit. Further, such marginalities present manufacturing yield limitations and testing problems.
Another important factor in respect of interfacing the nonvolatile elements to static RAM cells is providing compactness and simplicity to device design, as these factors affect circuit size and cost.
Kno~m interface systems unfortunately tend to require a complex interface in terms of control signals and extra transistors, which has resulted in large nonvolatile static RAM circuit size and correspondingly high cost.
Various known nonvolatile static RAM devices also tend to have the disadvantage of requiring high current demands and high voltages for opération. These requirements place practical limits on device power and speed, and complicate circuit design. Various known nonvolatile static RAM devices also tend to utilize the semiconductor substrate as the principal element in programming the nonvolatile memory components, which may involve application of high voltages to the RAM power line to effect nonvolatile element storage, so that it is difficult to independently optimize and separate the RAM cell design and fabrication process from the nonvolatile element design and fabrication process.
Further, when data placed in the nonvolatile storage element is recalled to the RAM cell, the data may be applied to the RAM cell in a complement~ or opposite state from that in which it was originally written into the nonvolatile element. Thus, if a binary "0" represented b~
a conductive first branch and nonconductive second branch of such a conventional flip-flop RAM cell is written to the non-volatile element, and subsequently is written back to the RAM
cell, the first branch of the RAM cell will be nonconductive and the second branch conductive, thereby representing a binary "1". Such complement state recall, rather than direct, true state recall, is a substantial inconvenience which must be handled by extra circuitry or otherwise accounted for by the user of the memory system.
Broadly speaking, therefore, the present invention provides a method for nonvolatile storage of binary information in a semiconductor integrated circuit, comprising the steps of capacitively sensing the one of two.binary memory states of a volatile semiconductor memory cell having binary information stored therein, causing a predetermined one of two electric charge levels to be created on a dielectrically isolated floating gate conductor corresponding to the one capacitively sensed memory state of the volatile memory cell without altering the memory state of the volatile memory cell, and causing the volatile memory cel] to capacitively sense the current charge level of the floating gate when power is first coupled to the volatile memory cell, such that the memory state of the volatile memory cell correspond~ to the charge level of the floating gate.
The above method may be efected by way of a nonvolatile memory device comprising a volatile semiconduc-tor memory cell for storing binary data, means for reading from and writing to the volatile memory cell, a nonvolatile memory means, comprising .~LJ
sd~ -5-an electrically insulated floating gate conductor, for storing binary data as one of two different electric charge levels on the floating gate conductor, means for capacitively coupling the volatile memory cell to the nonvolatile memory means and for copying the memory state of the bistable memory cell to the floating gate conductor at a predetermined one of the electric charge levels, and means for capacitively coupling the floating gate conductor of the nonvolatile memory means to the volatile memory cell for copying the memory state of the floating gate to the volatile memory cell upon application of electrical power to the volatile memory cell.
These and other features of the invention will become apparent from the following detailed description ,~

sd ~C -5A-1 ~

and the accompanying drawings of which:
FIGURE 1 is a top view of an embodiment of a nonvolatile static random access memory cell in accordance with the present invention as it appears prior to deposition of metal contacts and interconnections, FIG~RE 2 is a semi-schematic top view of the - .nonvolatile cell element of the memory cell o~ FIGURE 1, FIGURE 3 is a cross-sectional view of the 1~ nonvolatile cell element of FIGURE 2 taken through line 3-3 at an intermediate fabrication step;
FIGURE 4 is a cross-sectional view of the nonvolatile cell element of FIGURE 2 taken through line 4-4 at an intermediate fabrication step, and lS FIGURE 5 is a schematic circuit diagram of the nonvolatile static random access memory cell of FIGURE 1.
FIGURE 6 is a top view of a nonvolatile elec-..
- trically pxogrammable semlconductor floating gate memory cell embodiment of the present invention;
FIGURE 7 is a cross-sectional gide view of the embodiment o FIGURE 6, taken through line 2-2, ' FIGURE 8 is a schematic cross-sectional cir-cuit diagram representing the self-regulating circuit area of the embodLment of FIGURE 6 including the bias electrode, floating gate, and erase/store electrode gate Icircuit elements of the embodiment of FIGURE-6;
i FIGURE 5 is a graphic representation of device regulating capacitance as a function of the difference in potential between the bias electrode and the floating -gate for several doping levels;
FIGURE lOis a top view of another embodiment ~of a nonvolatile electrically programmable floating gate memory cell having a lateral tunneling electrode struc-ture, and FIGURE 11 is a cross-sectional side view of the embodiment of FIGURE 10.

-6a-Generally, the present invention is directed to nonvolatile semiconductor memory devices comprising a volatile semiconductor bistable memory'cell for storing binary data as one of two circuit memory states, addressing means for reading binary data from and writing binary data to the bistable volatile semiconductor~memory cell, and a nonvolatile memory element for storing binary data as one of two electric charge levels of a floating gate independently of the memory state of the volatile memory cell. The devices further comprise,means for capacitatively coupling-the volatile memory cell to the floating gate memory element and for copyin~ the memory state of the bistable memory cell to the floating gate element as a predetermined floatiny gate memory state together with means for ,, capacitatively coupling the floating gate element to the volatile semiconductor memory cell for copying the memory state of the floating gate of the nonvolatile element to the volatile cell upon application of .. . , Z~3 electrical power to the volatile memory cell. The means for copying the memory state of the bistable memory cell to the floating gate element and the means for copying the memory state of the floating gate element to the S bistable memory cell are operable such that upon copying an original circuit memory state of the bistable cell into the floating gate element, and subsequently copying the memory st~te of the floating ~ate element to the volatile cell, the bistable cell will be returned to its original memory state. The bistable volatile memory cells may desirably be static MOS four or six-transistor, cross coupled flip-flop circuit elements, and the devices in accordance with the invention will desirably be organized in a memory array such as a random access memory array in accordance with conventional practices.
Having generally described the invention, it will now be more particularly described with respect to the speciîic embodiment illustrated in FIGURES 1-5 of the drawings. Illustrated in FIGURES 1-5 is an embodiment 10 of a nonvolatile, static, ~random-access memory cell in accordance with the present inventionO
The illustrated cell 10 comprises a volatile static, - bistable flip-~lop memory cell 12 and a nonvolatile 25 electrically-alterable floating gate element 14. The illustrated cell 10 forms a part of an x-y addressable random access memory, and accordingly, the volatile memory cell 12 may hereinafter be referred to as a static R~M cell although such cells may also be used in other memory organi~ation designs~
FIGURE 1 is a substantially proportionally, accurate top view of the chip circuit design of the de~ice 1~) which iilustrates- the psivs~licon electrode structure o~ the device cell~ The circuit , .

schematic for the device 10 is shown in FIGURE 5 and, for purposes of clarity of description of the invention, the circuit elements of the device 10 of FIGURE 1 are shown in somewhat more simplified form in FIGURES 2-4.
S As shown in FIGURE 1, the layout design for the cell 10 is relatively compact, and is adapted ~o be a unit of a random access array of contiguous like cells, having relative cell dimensions generally as shown, using five micron (metric) design rules, with unit cell dimensions of about 82.$ microns by 79 microns.
In FIGURE 2, areas of n-implantation of the silicon substrate 11 are defined by solid line and cross-hatched. Further, in order to ilIustrate the various polysilicon layers of the overlapping structure of the device 10, the subsequently deposited polysilicon ~- layers are shown by different line designations. In this regardJ the first polysilicon layer 50 pattern is shown by solid line marked with additional dots, the second polysilicon layer 52 is shown by solid line with additional "x" markings, and the third polysilicon layer - 54 is shown by dashed line. "Buried contact" regions 61, 62 of connection of the polysilicon layer 54 to the n-channel zone are shown by cIosely dashed lines. In both FIGURE~ 1 and 2, regions for connection with metallization are shown by crossed squares.
Turning to schematic ~IGURE 5, the illustrated static RAM cell 12 and the random access array in which it is organized may be of generally conventional design. The RAM cell 12 may be read from and written to by appropriately addressing the cell for sensing or altering its current state in accordance with conventional practice and hy means of suitable R~ array connections and chip interfaces, such as store line 100, Vss potential line 102, Vcc potential line 104, Y data line 106~ and complement Y data line 108, which are .
~3 .

141~ 9 metal lines for carrying po~er and signals across the array (FIGURE 2) which make connection to the individual cells as shown by respective "X" designations in the path of the lines. The Vss potential may be about 0 volts, the Vcc potential may be about 5 volts, and the substrate potential Vbb may be about -3 volts in the illustrated embodiment 10.
The static RAM cell component 12 is coupled to the nonvolatile floating gate element 14 by means of a 10 dynamic, or capacitive imbalance, which coupling provides for storing the current memory content of the volatile static RAM cell 12 in the nonvolatile element 14 upon operator command. Capacitive coupling means is also provided for reading the contents of the nonvolatile floating gate element 14 into the volatile static RAM cell element 12 as desired upon operation of the appropriate circuit elements. The memory content of the static RAM cell 12 and nonvolatile element 14 may normally be independent of each other except on specific copying command. In particular, the current memory content of the RAM cell 10 is not stored into the nonvolatile memory element 14 whenever the RAM cell 12 is written to by the cell addressing and writing means, but rather, the memory content of the static RAM cell is only stored into the nonvolatile element 14 by operation of the capacitive copying circuitry upon specific "store" command, as will be more fuily described. In effect ~he nonvolatile memory element 14 thus appears to the system 10 as a programmable "shadow ROM".
As shown in FIGURE 5, the device 10 may comprise a six-transistor static RAM cell 12 of conventional design, and a nonvolatile electrically-alterable floating gate memory element 14.
The floating gate memory element 14 is of the type described in our contemporaneously filed application `
Serial No. 344,354, entitled "Substrate Coupled Floating Gate Memory CeIl" which for the sake of completeness will also be described herein with particular reference to Flgures 6 through 11 .
Generally, this aspect of the invention is directed to nonvolatile, electrically-alterable semiconductor memory elements of the floating gate type having an automatic self-regulating structure which is adapted to limit the programming currents applied to the floating gate and to enhance the number of useful memory cycles. In this connection, devices in ac-cordance with S~No 344,354 comprise a substantially monocrystal-line semiconductor substrate of one conductivity type, and an-electrically isolated floating gate conductor overlying the substrate. The devices further comprise an electron injection means for injecting electrons onto the floating gate to provide said floating gate with a negative potential, electron removal~
means for removing electrons from the floating gate to provide said floating gate with a potential more positive than said negative potential, an electrically isolatable bias electrode in said substrate of conductivity type opposite that of said sub-strate which is capacitively coupled to the floating gate, and means for detecting the potential state of the floating gate.
These elements may be combined to provide an automatically self-regulating circui-t system which tends to enhance the number of useful device cycles, as will be more fully described hereinafter.
As indicated, the devices comprise a substantially monocrystalline semiconductor substrate of one conductivity type, and in this connection p-type monocrystalline silicon wafers are the preferred substrate, although n-type silicon substrate wafers, ~ jrf~

epitaxial monocrystalline n- or p--type silicon layers on a monocrystalline dieIectric substrate such as sapphire, and other semiconductive materials are contemplated for different embodiments of the invention.
As also indicated, the present devices comprise at least one floating gate, electrically isolated conductor over-lying the substrate. The floating gate conductor may be a conducting polysilicon gate surrounded completely by an insu-lating material, such as thermally grown s-ilicon dioxide. The floating gate may be separated from the substrate by con-ventionally grown silicon dioxide dielectric layers of readily manufacturable ~ ` ~

thicXrless, such as in the range of from about 500 to about 15000 ~n~stroms thick. The upper surface of the floating gate disposed away from the semiconductor sub-strate may be fabricated in such a manner to contain a large population of asperities, which are minute areas o polysilicon with many sharp needle-like protrusions.
Electron emission can occur from such points to an over-lying erase electrode (which may also be fabricated of polycrystalline silicon~ at relatively low ap~lied volt-ages of less than about 30 volts due to enhanced Fowler-Nordheim tunnel emission and other mechanisms. The means o injecting charge onto the floating gate may comprise a program control electrode similarly fabricated - from polysilicon and underlying a portion of the floating gate. The upper surface of the program control electrode may similarly be provided with an upper surface having a population of asperities such that electron emission from the program control electrode to the floating gate may be similarly carried out at relatively low applied voltages of less than about 30 volts potential difference between the progxam control electrode and the floating gate.
As also indicated, means for sensing the stored charge on the floating gate is provided, and in this connection a portion of the floating gate may form the gate o the sense transistor positionea in said sub-strate. If electrons are present on the floating gate, - the (e.g., n-channel) transistor may be turned off. If electrons have been removed from the floating gate, its - 30 potential is positive and the (n-channel) sense transis-tor is turned on. The on or off condition of the float-ing ga~e sense transistor forms the means for detecting the presence or absence of charge on the floating gate and thus provides the basis for memory operation.
An important element of the present de~ices is - an electrically isolatable bias electrode ~ocated within the S~lbstrate at the substrate surface adjacent the floating ~ate, and o opposite conductivity type rela-tive to the substrate. The bias electrode may be locat-ed in the area partially beneath the erase/store elec-trode separated from éach by an oxide, such that it underlies both the floating gate and the erase/store electrode. Because the bias electrode is of opposite conductivity type to that of the substrate, it may be separated from the substxate electrically by pn junction action under the influence of a reverse bias potential, and means for so isolating the bias electrode should be provided in the devices. A primary function of the bias electrode is to properly bias by capacitive action the floating gate during electron injection to (i.e., during a write cycle) and electron emission from (i.e., during an erase cycle) the floating gate. There are several modes of controlling the bias gate potential. The bias electrode potential may be controlled by a switching cir-cuit element or device, such as a transistor in the de-vice substrate which connects the bias electrode to apredetermined reference voltage source when the transis-tor is turned on. When the switching element ~SUC}I as the switching transistor~ is off the bias electrode is brought sufficiently positive with respect to the pro-gram~ing electrode underlyin~ the floating gate, elec-trons will tunnel from the programming electrode to the floating gate, which in turn alters the floating gate potential by making it relatively more negative. This negative alteration of the floating gate potential by application of electrons can be sensed by a suitable sensing means such as a MOS transistor. Similarly, the erase/store electrode, which at least partially overlaps the floating gate and is insulated from the floating gate may be brought to a predetermined positi~e potential so that electrons will tunnel from the 10ating gate to the erase/stoxe electrode. In this manner, the floating gate ~ . ~

may ~e pxovided with a relati~ely more positive voltage whicl-l can be sensed by a suitable means such as the sensing transistor.
The automatic self-regulating compensation cir-cuit feature of the memory devices may be formed physi-cally in the region below the coincident floating gate and bias electrode and substrate in order to shape the current pulse into the floating gate during a write operation when electrons are flowing to the floating gate from the program gate. Such a circuit feature tends to minimi2e the stress across the tunnel oxide bet~een the progran~ing gate asperities and the floating gate. How-ever, after a large number of cycles of operation, - higher stresses are required to write to the floating gate due to trapped charges in the oxide. This circuit adjusts for this condition automatically by providing additional stress when required. It is the combination of provi~ing minimum stress to the floating gate, current pulse shaping, and providing extra stress to compensate for trapped charges which is a principal element in pro-longing the number of useful cycles in devices in accor-dance with the present invention. Further, these fea-tures ~ave been implemented in a very compact manner utilizing the semiconductor electrical nature of the bias electrode and its placement into the surface of the substrate semiconductor. In this regard, when in an electrically isolated condition, the bias electrode functions as a variable capacitive coupling means for capacitively coupling a major proportion of the potential of the erase/store electrode to the floating gate as a function of the floa~ing gate potential. In this con-nection, the capacitive coupling of the erasefstore electrode potential to the floating gate is utilized to develop a potential between the floating gate and the programming electrode suficient to transfer electrons from the programming electrode to the flo~ting gate.

.~

However, the capacitance of the capacitive coupling means is variable such that the portion of the erase/
store electrode potential which is coupled to the float-ing gate decreases with decreasing potential of the floating gate, and more specifically decreases with in-creasing difference between the potential of the bias electrode and the floating gate. Accordingly, the transfer of charge to the floating gate from the pro-. gramming electrode operates to decrease the capacitive coupling and conse~uently the transfer of charge to thefloating gate.
Turning now to the drawings, the present in-vention will now be more particularly described with respect to the specific embodiment of a nonvolatile electrically-alterable semiconductor device 110illus-trated in ~IGURES 6 and 7. Although the devicell0 is an n-channel MOS device, it will be appreciated that other device technologies such as p-channel configurations may also be utilized and are contemplated herein.
As shown in FIGURES 6 and 7 , the cell struc-ture of the device 110 is fabricated on a monocrystalline . . p-type silicon wafer substrate 111 which in the illustra-tive embodiment llomay have an acceptor doping level in the range of from about lx1014 to about 1x1016 atoms per cubic centimeter~ An electrically isolated, polysilicon floating gate 112 is provided adjacent the substrate, which is capacitively coupled ~o a bias electrode113 in the substrate 111. The bias electrode 113 is formed in the substrate lll of opposite conductivity -ty~e from the substratelll, and in the embodimentll0 may have a donor impurity level of in the range of about lx1017 atoms/cm3.
The bias electrode 113 may be formed in accordance with conventional fabrication techniques such as diffusion or ion implantation, and in the illustrated embodiments may be formed to a thickness of about 1 micron by ion implan-tatisn of a donor impuri~y at an implantation density of ~ .
., 3~

lx1012 ~o 1x1015 atoms per cm~.
~ lectrode potential switching means 114 is pro-vided in the device structure for supplying a predeter-mined potential to the bias electrode 113, and for elec-trically isolating the bias electrode. Means 115 issimilarly provided for injecting electrons to the float-ing gate 112,and means 116 for removing electrons from the floating ~ate 112 are also provided, together with . means 117 for sensing the charge state of the floating ~0 gate 112.
The substrate 111 and the bias electrode 113 are separated from the floating gate and other polycrystal-line electrodes forming the means114 for biasing and isolating the electrode 113, the electron injecting means 115 and the floating gate electron emission inducing means 116, by a thexmal oxide dielectric118 which in the illustrated embodiment is grown by conventional thermal oxidation techniques to an inter-element thickness of about 1000 Angstroms.
In this connection, the means114 for biasing and electrically isolating the bias electrode 113 in the monocrystalline substrate 111 comprises a select switch MOS transistor element124 formed between the bias elec-trode113, an interm~diate zone 127 of he substrate 111, 25 and a bias potential supply zone 126 of the same conduc-tivity type as the bias electrode 113, with a polycry-stalline silicon MOS select gate electrode 128 adapted to control the conductivity of the p-type substrate zone 127 between the bias electrode 113 and the bias potential sup-30 ply zone 126. The bias potential supply zone may be diffused or implanted into the substrate by conventional manufacturing techniques, and should best have a rela-tively high doping level to provide high conductivity.
The values of substrate doping and oxide thickness be-tween the select gate of bias electrode switching tran-sistor 124 and the substrate zone 127 are chosen to give a desired threshold voltage in accordance with conven-tional desi~n practice.
. Similarly, the floating gate 112, the electron injecting means115, and the electron removing meansll6 are formed of polysilicon layers suitably sequentially deposited, and etched and oxidized to form the desired structure as indicated in FIGURES 6 and 7. In the illus-trated embodiment, three sequentially deposited layers 150, 152, 154Of polysilicon are used. The bias electrode select gate electrode 128 may be formed from any of the three polysilicon layers but in the illustrated embodi-ment is formed from the irst layer 150. The means115 for injecting electrons in the form of a program gate electrode 130 is similarly fabricated from the first poly- -silic~n layer 150, which is deposited on the silicon oxide dielectric layer formed by oxidation of the substratelll.
The first polysilicon layer 150 is treated to produce sur~
face asperities134 by oxidation at approximately 1000C.
A similar procedure is performed on the second layer 152 of polysilicon used to form the floating gate 112. The purpose of this procedure is to introduce asperities134 on the upper surfaces 136, 140Of the pro~ramming gate electrode and the floating gate as indicated by the ser-rations in FIGURE 7. The asperities are small projec-tions at the surface which are present in numerous quan-tity (e.g., there may be an areal density of 5 x 109 asperities per cm ). A large portion of the asperities may have an average height greater than their base width (e.g., a base width of abou~ 450 Angstroms and a height of about 750 Angstroms). The tips of the asperi-ties are believed to have a very small radius of curva-tuxe which is capable of producing high local fields at relatively low average field strength, thus xeducing the Pield strength necessary for tunneling. These high local fields are sufficient to inject electrons into relatively thic~ oxides (or tunneling purposes, using the term "tunneling" in a broad sense) while applying on the average a relatively low ~oltage difference across the oxide. In a smooth surface lacking such asperities, electrons are not injected into the thick oxide at the low voltages. Suitable asperities 134 can be generated over a range of collditions and a range of sizes, and are not limited to the particular example stated above.
A third polysilicon layer 154 is deposited (after oxida-tion of the second floating gate layer 152) over the floating gate 112 and processed to form an erase~store electrode 132, which in conjunction with the asperities on the top surface of the floating gate 112 forms the means 116 for removing electrons from the floating gate.
The oxides118, 120, 121, 122, 123 separating and insulating the various polysilicon layers150, 152, 154 may be fabricated by well known techniques such as thermal oxidation. Similarly,,the patterned polysilicon layers 150, 152, 154may be patterned and fabricated by well kno~n semiconductor phot,olithographic techniques.
The overlapping regionl44 between the floating gatell2 and the programrning electrode is the area in which electrons tunnel through the separating oxide 122 from the programming gate to the floating gate. By appropriately biasing the floating gate 112 with positive polarity in respect to the programming electrode 130, electrons will tunnel from the programming electrode 130 to the floating gate 112. The electron charge is injected from the asperities134 at the surface of the program control electrode by enhanced tunneling into the sepa-rating oxide 122and travels to and is collected by thefloating gate 112 under the influence of the positive bias. After the biasing voltage is removed from the floating gate 112, the tunneled electrons are confined on the floating gate as they do not have the energy to sur-mount the isolating oxide energy barrier. The electronsmay be retained substantially indefinitely,on the l~ Z~

19- - .

floating ~ate unless removed.
Electrons may be removed from the floating gate by means of an erase/store electrode fabricated in polysilicon having a smooth lower surface separated by a suitable dielectric such as silicon oxide disposed adjacent a portion of the surface of the floating gate which does possess a high density of asperities. By appropriately biasing the erase/store gate at a suffi-ciently high positive potential with respect to the floating gate, electrons may be caused to tunnel fxom the asperities on the upper surface of the floating gate to the exase/store gate. In this manner, the floating gate may be provided with a relatively positi~e charge, i.e., turned on for an n-channel device. The overlap-ping region 145 between the erase/write electrode 32 and the floating gate 112is the area in which electrons tun-nel through the separating oxide 123 from the floating gate to the erase/write electrode. In the illustrated embodiment, these oxides 122, ~23 are approximately 1000 Angstroms thick and are thus easily manufacturable in a reliable and reproducible manner. In this connection, while a ~000 Angstrom silicon oxide dielectric thickness is used in the illustrated embodiment as an optimum thickness, the optimum thickness may change as manufac-turing techniques are improved.
As indicated, means 117 is provided for sensingthe potential of the floating gate112, and in this con-nection, as shown in FIGURE 6, a portionll9 of the float-ing gatell2 extends beyond the bias electrode113 to form the gate electxode of a MO5 sense transistor 156 compris-ing n-type source and drain regions 158, 160 separated by -an intermediate portion of the p-type sub~trate, the conductivity of which is governed by the charge on the floating gate.
In operation of the de~ice 110, the floating gate 112is either charged with an excess number o~

.

r~,s .

- zo -electrons, which causes its voltage to be low (negative~
and thereby functions to turn off the remotely located sense transistor 156, or the floating gate is charged relatively positive by a removal of electrons which S causes its voltage to be high, thereby turning on the remotely located transistor 156. The exact configuration and location of the remote sense transistor, the gate of which is formed by a portion of the floating gate 112,is not essential and many variations may be provided. The 10 . on or off nature of the remotely located sense transis-tor 56 forms the basis for detecting the memory state of the floating gate 112 of the device 110. This memory state of the floating gate 112 may be altered by writing (or "programming") electrons to the gate, and by removing ~or "erasing"l electrons from the gate.
In operat.ion, the erase/store electrode 132 and the floating gate 112have substantial capacitative . interaction with the bias electrode 113 in the substrate . 111. In this regard, it should be noted that the erase/
store electrode 132 overlaps a portion of the bias elec-trode 113 forming a coupling capacitor CC3 of capacitance determined by factors including the overlap area and thickness of oxide dielectric 120. Similarly, the float-ing gate 112overlaps a portion of the bias electrode forming a coupling capacitor CC2 of capacitance deter-mined by the overlap area and the thickness of insula-tion 121, the voltage difference of the floating gate 112 relative to the bias electrode 113 and the doping density N of the bias electrode. These circuit elements are shown semi-schematically in FIGURE 8. In the region of capacitative overlap between the floating gate 112 an~
the bias electrode 113, a self-regulating compensation circuit element is providea due to the nature of the . voltage variable capacitor CC2 as will be more fully described.
In writing, or programming, of the device 11.0, .

, excess electrons are introduced onto the floating gate 11~ from the programming electrode 130. In order to carry ou~ a writing cycle of steps to introduce excess electrons onto floating gate112, a tunnel current pulse of electrons is directed onto the 10ating gate 112 from the programming electrode 130. This tunneling occurs in the overlap region 44 by raising the Eloating gate 112 to a sufficiently positive ~roltage with respect to the programming electrode 13~. -In order to raise the relative potential of the 10ating gate 112, the capacitance coupling of the erase/
store electrode 132 and the floating gate 112 to th~ bias ~ electrode 113 is utilized~ To carry out a write cycle, the gate transistor 124 ma~ be rendered conductive to a refere~ce voltage source more positive than the substrate ~lvoltage by an appro~riate potential Von applied to select gate electrode 128, so that the bias electrode 113 is substantially equilibrated to the potential of the voltage source 126 and is electrically isolated from the substrate by the reverse biased p-n junction action. ~he programming electrode 130 may concommitantly be held at a predetermined reference voltage. The select gate transis-tor 124may then be rendered nonconductive by application of a suitable potential VofE to se~lect gate electrode 128 to leave the bias electrode floating. The erase/store electrode 132 may then be activated by application of a positive voltage VD. Because the erase/store electrode is capacitively coupled to the bias electrode ~by capaci- -tance CC3), the bias electrode 113 will ~end to follow the erase/s~ore electrodel32up in v~ltage for suitable choice of ratios -- of capacitance of CC2 to the capacitance CC3. As mentioned above~
capacitor CC2 i5 the ooupling capacitance be ~ en the floating gate 112and the bias elecbx~e 113.1~en the bias elec~x~ell3reaches a sufficiently high voltage with respect to the pnus~mr~ng electrode 35 130, electrons will tunnel from the programming electrode to the 10ating gate l12. In the pre-

2~

ferred mode of operation, the programming electrode 130 and the voltage source 126 are held at some DC voltage, Vs~, which is typically ground potential (zero volts).
The substrate voltage VBB, is held at a DC voltage more negative than Vss, with:VBB being typically in the range of from about -2 to about -5 volts.
~ re specifically, a write cycle begins by Eulsing sel~ct gate electx~e128from the "off" position ttypically zero volts) to the "on" position (typically fr~m about 2 to about 5 vvlts) for a period of time sufficie~t to substantially ~librate the bias electrode 113 to the potential Vss of the voltage source 126, which in the illustrated embodimentllO may be about 10 nanoseconds. Then the select gate electrode128 is turned off, leaving the bias electrode 113 floating, or isolated by p-n junction action, at potential Vss.
The erase/store electrode132 is maintained at potential Vss during the equilibration of the bias elec-trode113. Subsequently, the erase/store electrode 132 is raised to a write potential VD of approximately 25 volts, which potential is coupled via capacitor CC3 to the ~loating bias electrode 113, and then coupled to the floating gate112 via capacitor CC2. The various operat-ing, control and sensing potentials may be applied by suitable contacts from an external or on-chip power sup-ply, o~, at least in part, may be generated on-chip.
The illustrated device llOmay be part of an array of d~vices ~such that the various potential connections are shown semi-schematically~ which may include suitable means for addressing the individual cells, as well as fox providing and switching the various voltage poten-tials and pulses~ The capacitive coupling of the erase/
store electrode 132 and the floating gate 112 to the bias electrode 113is an important fea~ure in the operation of the device 110. In this connection, the ratio of CC2 to CC3 should desirably be in the range of from about 1:2 to about 2:1, and more preferably in the range of about .

1:1. In the illustrated embodiment, CC2 is substan tially equal to CC3 wi~h this ratio of CC2 and CC3 (and other capacitative effects) of the illustrated embodi-mentllO being chosen in such a ~ay.
The illustrated devicellO provides self-regulating stress compensation during the writing of electrons to the floating gate 112 from the programming electrode 130. If the doping concentration of the bias electrode region is very high (e.g., above about 10l8 lO . atoms per cm ), capacitance CC2 may be considered to be a substantially "metal like" potential invariant capaci-tative plate in respect of transferring potential applied to the erase/store electrode 132, to the program-ming electrode 130j via the bias electrode113 and the l~ floating gate 112. However, by appropriate control of doping density of the bias.electrode 113, the capacita-tive potential interconnective effect may be made variant in a predetermined manner to aid in prolonging . device lifetime. . - . 20. -- Because the capacitance CC2 provided between the bias electrode ll3 and the floating gatell2 may be rendered voltage dependent, and because-tunneled charges from the programming electrode130 affect the potential on the floating gate 112, this variable capacitance can be exploited to shape and limit the tunnel current in a self-regulating.and compensating manner. Such pulse shapiny of the floating gate tunnel current may be utilized to enhance the number of useful cycles in the deviceO In a similar manner, compensation may be pro-3U vided which effectively adds more electric field stressacross the tunnel electrodes as the device begins to degrade through use.
This self-compensating feature utilizes parti-cular physical properties of the electrically isolated "floating" bias electrode113 which is formed of a region of opposite conductivity from the substratelll. The g bias electrodell3 when left floating by disconnection from voltage source Vss accordingly forms a junction isolated region in the substrate which is electrically isolated from the substrate, the floating gate and other electrodes. The capacitance CC2 between the floating gate and the bias electrode is principally determined b~
factors includin~ the voltage difference between these device elements, the thickness and dielectric constant of the intervening insulating layer, and the doping in-tensity of the bias electrode region. When the floatinggate112 has a positive potential with respect to the bias electrode 113, the capacitance CC2 between them is fixed at a maximum, principally determined by the area of overlap and the thickness and dielectric constant o the insulating silicon dioxide layer 121. Accordingly, pulse shaping of the tunnel current to the floating gate from the programming electrode 130 arises from the variable nature of this capacitance. Specifically with respect to electron injection, or "writing", so long as no tunneling from the programming electrodel30 in the floating gatell2 occurs, the potential difference bet~een the bias elec-trode and floating gate may remain small through suitable choice of capacitances CC2 and CC3. However, once tun-neling commences from the programming electrode ~0 to the floating gate 112, the floating gate potential becomes increasingly negative relative to the bias gate electrode 113. This causes a drop in the total drive voltage across the tunneling electrode because the effective coupling capacitance between the floating gate and the bias elec-trode is reduced. The effect of this is ~o shape, con-trol, and limit the maximum peak currents allowed to flow from the programming electrode to the floating gate.
It is well known that the control of the tunnel current through oxides can enhance the total number of cycles available and therefore provide improved performance.
As indicated, once tunneling to the floating

3~

gate has occurred, the potential on the floating gate 112 becomes negative with respect to the floating bias elec-trode 113 and this tends to decrease the capacitance CC2.
Reerring to FIGURE 8, when the potential on the floating gate112 is less than potential at a zonell2B internally of the surface of the bias electrode, a depletion region 112A forms which causes CC2, the coupling capacitor be-tween the floating gate and the bias electrode, to de-crease. The regionll2B can be considered as a "wire-like"
connection, or the common connection, between capacitance element CC2 and capacitance element CC3. Similarly, regions112C.and112D are formed in the substrate which are depletion regions which form the reverse bias junc-~ion isolation of region113 from the substrate lll.
These depletion effects which occur when the potential of the floating gate112 is less than the potential of the bias electrode 113 decrease the capasitance CC2 bekween the floating gate and the bias electrode. The variable capacitance of an electrode in respect of a depletion region may be represented as a function of the potential between the electrode and the substrate ~oyle & Smith (1970), "Charge Coupled Semiconductor Devices", Bell Systems Technical Journal, 49, pp. 587-593~ and in the illustrated embodiment, the variable capacitance CC2 o~ the floating gate 112 with respect to the bias elec-trodell3 may be substantially represented as:
CC2 =. CO
~1+ o (I~V-VFB) where CO is maximum capacitance value ~per cm2 of the capacitor formed by the adjacent surfaces of the floating gate112, defined as ~ R Nx CO = x ~ and B = q~S
where ~ is the dielectric constant of the silicon dioxide region 121 between the floating gate 112and the bias electrode 113, x is the thickness o the dielectric region between the floating gate 112 and the bias electrode 113, q is the electronic charge, Ks is the re]ative dielectric constant of silicon, Kd is the relative dielectric constant of the region121 separating the bias electrodell3 and the float-ing gate 112, N is the doping density of the bias electrode113, ~V is the potential ~N+ f the bias electrode 113 minus the potential VFG of the floating gate 112,where ~V is approYimately greateL than zero, and VFB is the flat band voltage.
Accordingly, CC~ can vaxy from being almost equal to CO
(a constant) for very high doping density (N) to almost zero for very low doping density (N), with other para-meters being constant. The capacitance CC2 thus becomes less as the floating gate 112 begins to receive electrons and falls negative. However, when AV is less than zero, capacitance CC2 is substantially at its relatively con-stant, maximum value, CO.
The variable capacitance CC2 controls the voltage coupling of the floating gate 112 to the bias electrode zone 113, and accordingly the potential dif-erence between the programming electrode 130 and the floating gate which drives the tunneling current, may be - beneficially controlled by control of the doping density N in the bias electrode. The variation in capacitance CC2 for the device structure of the type shown in the illustrated embodiment is graphically shown in FIGURE 9 for various doping levels of the bias electrode113. In FIGURE 9, the ratio of CC2 to CO is plotted against the - voltage difference ~V between the bias electrode poten-tial VN~ and the po~ential V~G of the floating gate 112,-for doping levels of 1 x 10 donor atoms/cm3, 1 x 10 7 .

donor atoms/cm3, and 1 x 1018 donor atoms/cm3, for a silicon dioxide dielectric thickness of about ~00 Ang-stroms. A particularly pxeferred range of variability of the capacitance CC2 during the write cycle is shown for a bias electrode doping level of N = 10 7 atoms/cm , which produces a CC2/Co ratio between about .5 and .6 during the write cycle, in which ~V ~ill typically be from about 9 to about 10 volts after electron injection.
Accordingly, the capacitance CC2 decreases by a factor of almost 2 during a write cycle for the illustrated 1 x 1017/cm3 doping example. In embodiments of the present devices in which a variable capacitance is provided, the doping concentra-tion will range from about 5 x iol6 to about 5 x 1017 in the bias electrode 113. In such embodi-ments, the capacitance CC2 should best decrease by a factor of from about 3 to about 2 during the ~rite cycle (i.e., will decrease to about .33 to about .5 of the initial value, CO) Since the capacitance CC2 is a func- ~
- tion of and decreases as a function of total tunnel current ~i.e., negative charge~ to the floating gate, the tunnel current itself decreases its own driving potential and is effectively self-limiting when t~e desired amount of charge has been placed on the floating gate during a write cycle.
Thus, it will be appreciated that the device 110 has a structural configuration that self-regulates and controls the tunnel current. The total number of usable cycles availabl~ in this floating gate device depends on peaX current and tunnel current shapes used in writing of the electrons, and the character of capacitance CC2 operates to keep the currents low and impress the mini-mum possible efective stress to enhance device lifetime.
A further feature of the variable CC2 capacitor is that it also tends to provide increased stress when the device becomes more difficult to program, such as after a number of cycles. In this regard, the structure 2~

of the device 110 allows the electrical field stress on the floating gate 112 to rise until programming besins to occur, whereupon the self-regulating action brought about by the decrease of CC2 causes reduction in the driving ield. However, after a number of cycles, the tunnel current may not begin until the field stress reaches a higher value. In this manner, the device 10 ten~s to compensate for the need for increase stress when device use degrades the properties of the oxide in the region.
In summary, a circuit system which is inherently a part of the memory cell 110 has been provided which auto-matically shapes and limits the electron tunnel current, which ~ends to increase the number of write cycles avail-15 - able to tlle device. Further, even when the write proper-ties hegin to degrade, the inherent circuit system also acts to increase the stress to overcome device degradation.
These features tend to substantially aad to the useful length of service for the memory device 110.
The floating gatell20f the devicellO is also electrical- -ly erasable, such that electrons may be re~oved from the floating gate 1120f the memory device by an appropriate "erasing" procedure.
In order to remove electrons stored on the floating gatell2, the erase/store electrodel32is raised to a sufficien~y positive voltage 2S ~ith respect to the floating gatell2sllch ~at electrons are emitted from asperitiesl34 on the ~oating gate upper surfacel4~ to the smooth la ~ surface 1420f the erase/store elec~x~e 132.
In order to remove electrons from the ~loating gate 112, the select gate transistor 124 is rendered con-ductive by applying a potential STET of about 5 volts.
(e.g. via Von/Voff switch shown in FIGURE 6). The select - transistor 24 is maintained in a conduc~ive state during the entixe erase cycle so that the bias electrode is ~ept at the fixed re~ercnce potential Vss by conductive cor-rection to voltage supply zone 126 throughout the cycle.

~.A, Because the floating gate 112 is capacitively coupled to the bias electrode113 it tends to be held capacitively near the fixed reerence potential VSs of the bias elec-trode. The erase/store electrode 132 is then biasea to a sufficiently high potential Vw, such that a voltage diference is developed between the erase/store electrode 132 and the floating gate 112, sufficient to cause elec-- trons to tunnel from the floating gate 112 to the erase/
store electrode 132 from the asperities 134 at the top suf-face 1~0 of the floating gate to the erase/store electrode132,~,~hich leaves the floating gate 112 positively charged.
This relatively positive charge of the floating gate 112 may be sensed by testing the conductivity of the remote sensing transistorl56, the gate of ~hich is formed by an extension of the floating gate. Because the floating gate has a relatively positive potential with respect to the potential Vss, the remote sensin~ transistor 156 is turned on so that current is conducted between the N+
source-drain zones when a suitable potential is applied thereacross.
Thus, in accordance with the present invention, electrically-erasable memory de-~ices and methods have been provided which have desirab]e characteristics and which may incorporate self-regulating and compensating device structure to extend useful life of the device.
Devices in accordance with the invention can be readily fabricated using standard MOS techniques.
The devices in accordance with the invention can be used to form a memory array such as an electrically-alterable read only memory array (EAROM) with addition ofcommonly known decoding and buffering systems. The pre-sent devices may also be utilized to form fault tolerant elements which, for example, may improve device manufac-turing yield or to provide alternate logical paths in a microcomputer chip. These and other circuit combinations may be utilized in useful and readily realizable inte--.

gratcd circuits.
~ lthough the invention has been specifically described with respect to a particular embodiment and operating mode, it will be appreciated that numerous variations, modifications and adaptations may be made.
For e~ample, illustrated in FIGURES lOand 11 is another embodiment 200 of a nonvolatile, electrically alterable memory cell in which an electrode array having laterally arranged asperities and floating gate tunneling currents is provided.
In this regard, the device 200 comprises a monocrystalline p-type silicon substrate 202, having a monocrystalline n-type bias electrode 204 therein con-nected to a suitable bias electrode voltage source via an input transistor (not shown) at the terminal end of a channel extension 206 of the bias electrode 204. Over-lying and in capacitive relationship to the bias elec-trode, and separated therefrom by a suitable silicon dioxide layer 208 (e.g., 500-lOOOA thick) are polysilicon erase/store electrode 210 and the electrically isolated - polysilicon floating gate 212~ An extension 214 of the floating gate 212 forms the gate of MOS-sense transistor 216 comprising n-type source and drain regions, and further extends to be adjacent polysilicon programming 25 electrode 218. The programming electrode 218 may be fab-ricated from a first polysilicon layer, the floating gate 212 from a second polysilicon layer, and the erase~
store electrode from a third polysilicon layer so as to proviae immediately adjacent structures as shown in the drawings. The programming electrode is provided with asperities 220 immediately adjacent (but separated there-from by a 500-lOOOA silicon dioxide layer222~ the floating gate fox tunneling of electrons from the pro-gramming gate to the floating gate. Similarly, the 35 floating gate 212 is pxovided with asperities 224 immed-iately adjacent (but separated therefrom by a 500-lOOOA

.6~z9 silicon dioxide layer 226) the erase/store electrode for tunneling of electrons from the floating gate to the erase/store electrode. The fabrication of such lateral electrode structures may be, or example, fabricated by conventional techniques [e.g., U.S. Patent No. 4,053,349]
and the device 200 may be operated as generally des-cribed in connection with the operation of the devicellO.-As another embodiment, a memory cell in accordance with the invention may be constructed together with a RAM
memory cell to provide for permanent retention of the RAM cell contents. A large array of memory dev-ices may be provided having x and y select electrodes and/or im-plants to produce an addressable nonvolatile memory array. Such adaptations, modifications and variations are intended to be within the spirit and scope of the present invention.

- . .

An important element of the nonvolatile memory cell component of the present devices is an electrically isolatable bias electrode located within the substrate at the substrate surface adjacent a floating gate, and of opposite conductivity type relative to the substrate. The bias electrode may be located in the area partially beneath an erase/store electrode separated from each by an oxide, such that it underlies both the floating gate and the erase/store electrode.
Because the bias electrode is of opposite conductivity type to that of the substrate, it may be separated from the substrate electrically by pn junction action under the influence of a reverse bias potential, and means for so isolating the bias electrode should be provided in lS ~the devices. A primary function of the bias electrode is to properly bias by capacitive action the floating gate during electron injection to (i.e., during a write cycle~ and electron emission from (i.e.,~during an erase cycle) the floating gate.
The bias electrode potential may be controlled by a switching circuit element or device, such as a transistor in the device substrate ~hich connects the bias electrode to a predetermined reference voltag~
~source when the transistor is turned on. When ~he switching element (such as the switching transistor) is off the bias electrode is brought sufficiently positive with respect to the programming electrode underlying the floating gate, that electrons will tunnel from the programming electrode to the floating gate, which in turn alters the floating gate potential by making it relatively more negative. This negative alteration of the floating gate potential by application of electrons Z~

can be sensed by a suitable sensing means such as a MOS
transistor. Similarly, the erase/store electrode, which at least partially overlaps the floating gate and is insulated ~rom the floating gate may be brouyht to a S predetermined positive potential so that electrons will tunnel from the floating gate to the erase/store electrode. In this manner, the floating gate may be provided with a relatively more positive voltage which can be sensed by a suitable means such as the sensing transistor.
An automatic self-regulating compensation circuit feature of the memory devices may be formed physically in the region below the coincident floating gate and bias electrode and substrate in order to shape the current pulse into the floating gate during a ~rite operation when electrons are flowing to the floating gate from the program gate. Such a circuit feature tends to minimize the stress across the tunnel oxide between the programming gate asperities and the floating gate. However, after a large number of cycles of operation, higher stresses are required to write to the floa~ing gate due to trapped charges in the oxide. This circuit adjusts for this condition automatically by providing additional stress when required. It is the combination of providing minimum stress to the floating gate, current pulse shaping, and providing extra stress to compensate for trapped charges which is a principal element in prolonging the number of usef~l cycles in devices in accordance with the present invention.
Further, these features have been implemented in a very compact manner utilizing the semiconductor electrical nat~re of the bias electrode and its placemen~ into the surface o~ the substrate semiconductor. In this regard, when in an electrically isolated condition, the bias 3~ electrode ~unctions as a variable capacitive coupling 3~

, means for capacitively coupling a major proportion o the potential of the erase/store electrode to the floating gate as a funstion of the floating gate potential. In this connection, the capactive coupling S of the erase/store electrode potential to the floating gate is utilized to develop a potential between the floating gate and the programming electrode sufficient to transfer electrons ~rom the programming electrode to the floating gate. However, the capacitance of the capacitive coupling means is variable such that the portion of the erase/store electrode potential which is coupled to the floating gate decreases with decreasing potential o the floating gate, and more specifically decreases with increasing dif~erence between the lS potential of the bias electrode and the floating gate~
Accordingly, the transfer of charge to the floating gate from the programming electrode operates to decrease the capacitive coupling and consequently the transfer of charge to the floating gate.
As shown in the dra~ings, the cell structure of the device 10 is fabricated on a monocrystalline p-type silicon wafer substrate 11 which in the illustrative embodiment 10 may have an acceptor doping level in the range of from abou~ lx1014 to about 1x1016 atoms per cubic centimeter. An electrically isolated, polysilicon - floating gate 2 is provided adjacent the substrate, which is capacitively coupled to a bias electrode 7 in the substrate 11. The bias electrode 7 is formed in the substrat:e 11 of opposite conductivity type from the substrate ll, and in the embodiment 10 may have a donor impurity level o in the range of about 1x1017 atoms/cm3. The bias electrode 13 may be formed in accordance ~ith conventional abrication techniques su~h as diffusion or ion implantation, and the illustrated embodiments may be formed to a thickness of about 1 ~L~41 (D;~9 ~35-micron by ion implantation of a donor impurity at an implantation density of lx1012 to 1x1015 atoms per cm .
The variable capacitance of an electrode in respect of a depletion region may be represented as a function of the potential between the electrode and the substrate.EBoyle & Smith (1970), "Charge Coupled Semiconductor Devices", Bell Systems Technical Journal~
49, pp. 587-593] and in the illustrated embodiment, the variable capaci~ance CC2 of the floating gate 2 with respect to the bias electrode 7 may be substantially represented as: -CC2 = 1 2Co ~ 1+ . (~ V-VFB~
where CO is maximum capacitance value (per cm2 of the capacitor formed by the adjacent surfaces of the floating gate 2, defïned as CO=~, and B - qKsNx x , Kd where ~ is the dielebtric constant of the silicon dioxide region 5 between the floating gate 2 and the . bias electrode 7, x is the thickness of the dielectric region .
~5 5 between the floating gate 2 and the bias electrode : 7, q is the electronic charge, Ks is the relative dielectric constant of silicon, Kd is the relative dielectric con~tant of the region 5 separating the bias electrode 7 and the floating gate 2l N is the doping density of the bias electrode 7, 32~

~V is the potential VN+ of the bias electrode 7 minus the potential VFG of the floating gate 2, where ~V is approximately greater - than zero, and VFB is the flat band voltage.
Accordingly, CC2 can vary from being almost equal to CO (a constant~ for very high doping density (N) to almost zero for very low doping density (N), with - other parameters being constant. The capacitance CC2 thus becomes less as the ~loatin~ gate 2 begins to receive electrons and falls negativeO However, when ~ V is less than zero, capacitance CC2 is substantially at its relatively constant, maximum - . value, CO.
The ~ariable capacitance CC2 controls the voltage coupling of the floating gate 2 to the bias electrode~7, and accordingly the p~tential . difference between the programming electrode and the floating gate, which drives the tunneling current, may be beneficially controlled by control of the doping density N in the bias electrode~ ~
The illustrated random:access memory cell 12 is of conventional MOS RAM dësign comprising two cross coupled static inverter circuits combined to -form a static, six-transistor flip-flop memory element. In this regard, the RAM memory element 12 comprises cross ~oupled flip-flop transistors 27, 28 respectively connected to depletion pull-up transistors 31, 32 through respective data nodes 29, 30. Flip flop transis~ors 27~ 28 are appropriately connected to ground terminal 24, while depletion pull-up transistors 31, 32 are connected to the ~AM
- power supply terminal Vcc. Array ("row" or "word") "X" select transistors 33, 34 are similarly connected to the data nodes 29~ 30 for array ^ ~ Z~

selection purposes, in the overall memory array of which the device 10 forms a part. The selection of the cell 12 in an array of cells may be accomplished by applying a potential of Vcc to the gate of one of the X address transistors 331 34 and one of the Y
("column") address lines, which connect to the complementary data output nodes 35, 36 thereby causing the X address transistor to turn on, thus connecting the flip-flop nodes of the addressed cell 12 to the "bit" lines, Y and Y of the memory arrayO
in accordance with conventional RAM operation and design practice.
Reading of the addressed cell 12 may be -carried out by holding both "bit" lines through high valued resistors to potential Vcc. Depending on the state of the flip-flop (either transistor 27 or 28 will be on and the other will be off) current - will flow in one or the other of the "bit" lines and reading may be accomplished by sensing the differential current. Writing to the cell 12 may be accomplished in a conventional manner by addressing a cell 12 as if to read, and holding one "bit" line at potential Vcc while bringing the other "bit" line to the substrate potential VssO
The cell 12 may thus be accessed through the "word" "X" transistors 33, 34 with Data and complement Data appearing at Y node 35 and Y node 36, respectiveIy. Conventional R~M read/write operations are accordingly performed through data nodes 35 and 36. The cross coupled static flip-flop is formed by transistors 27t 28, 31, 32, having complement states appearing at nodes 29 and 30 as long as power (Vcc) is continuously supplied to terminal 26 of the cell 12.
The construction of the static R~l cell 12 3~9 may be carried out by means of commonly known semiconductor processes and photolithography techniques. While a speci~ic static RAM design is shown in the illustrated embodiment 10, it will be S appreciated that other suitable desi~ns may also be utilized. For example, in the embodiment 10, transistors 31 and 32 are shown in depletion devices, but in other embodiments, these transistors could be replaced by appropriate resistors.
- - As indicated, the RAM cell is interfaced with a non-volatile memory element 14. The illus~rated nonvolatile cell element 14 comprises a floating gate 2, means for transferring electrons into the 10ating gate, and means for removing electrons from the ~loating gate. The cell element 14 further has an automatic self-regulating circuit configuration which tends to enhance the number of useful write cycles in the nonvolatile element 14.
In operation, transferring electrons onto the floating gate to provide a relatively negative potential memory state on the floating gate, and removing electrons from the floating gate to provide a relatively positive potential memory state, forms the basis for memor~ storage on the nonvolatile storage device 14. Charge transfer and removal from the floating gate is accomplished by means of electron tunneling, which results in virtually no DC
current being drawn from the high voltage programming supply~ The small current requirement 3~ on the high voltage supply makes possible "on-chip"
generation of this voltage, and is ~ significant advancement in the art. The tunneling current is aided by sharp island-like asperities which are present in the nonvolatile eleraent, so that 3~ relati.vely thick oxides can be used to separate the ~, ' .
.

tunneling members of the cell and yet draw significant tunneling currents to and from the floating gate at reasonable voltages. Another property of the asperities is that they tend to conduct tunnel current primarily in a singular direction, and do not show symmetric bidirectional current flow properties for reversed fields. A
consequence of this is that the nonvolatile element 14 is relatively immune against loss of memory state by premature, undesiLed discharge of its electronic charge due to read operation or ad]acent cell operation. Since the performance of the illustrated nonvolati]e memory element is controlled by ~unneling properties between polysilicon elements which are locted physically above the substrate ~containing the static RAM cell which is largely controlled by phenomena in the substrate), the static RAM and novolatile elements can be independently optimized. Therefore, this combination of static RAM cell and nonvolatile element can be easily used with many different technologies.
In carrying out the capacitive coupling, one of the nodes 29 of the RAM cell 12 is capacitively coupled via a capacitance circuit element 23 having a capacitance Cl, and transistor 8, to the nonvolatile memory element 14~ Complement data node 30 is similarly capacitively coupled to the nonvolatile element 14 by rneans of transistor 20 to capacitative circuit element 17 having a capacitance C2. The various other circuit coupling elements will be subsequently described in more detail, but it is important to note that the static RAM cell 12 is only capacitively coupled to the nonvolatile element 14. No DC offset current load is applied to flip-flop data nodes 29 ox 30 by the interfaoe with the non-volatile element 14 so that the static RAM oell 12 is substantially balanced in the steady state condition. Ihis is an important impro~Jement over the - prior art and leads to improved operating margins. -Electrode and floating gate structure of the devi oe 10 is shown-in FIGURE 1, ~ile FIGU~E 2 il-lustrates a simplified topographic view of the RAM cell 12 and the nonvolatile elem~nt 14 showing the various oomponents of the static RAM cell 12 and non-volatile electrically-alterable component of the device 10, together with the appropriate relative sizes of the various transistors and capacitance elements.
FIGURES 3 and 4 show cross sections of selected elem~nts taken through FIGURE 2, follcwing a process step in devi oe fabrication commonly called "source-drain doping" with additional dielectric and metallization layers being utilized to ccmplete the devi oe, in accordance with oonventional processing and array design. The structure and operation of the nonvolatile element 14 is generally in accordance with the disclosure of our contenporaneously filed application Serial No. 344,354, with several additional elements which form the interfaoe to the static RAM cell 12. Ihe nonvolatile oe ll 14 in the preferred em~
bodLment 10 utilizes three layers 50, 52, 54 of polysilicon in its fabrication in conjunction with various substrate elements and separating dielectrics.
Although the illustrated devi oe 10 including the nonvolatile cell 14 is fabricated in n-channel M~S technology, other fabrication and design ap-proaches may also be ~tilized.
Ihe illustrated nonvolatile element structure (as shcwn in FlGURæS
2-4) is fabricated on h. ' jr/ ~

3~

a p-type silicon substrate 11, which fur.her includes a bias electrode 7 of opposite conductivity type from the substrate ll. The bias electrode may be introduced by conventional techniques such as diffusion or ion implantation. A thermal oxide 4 which may be grown hy conventional techniques to be about 12000 Angstroms thick is provided on the substrate 11 for cell isolation purposes. It is subsequently etched in the areas of floating gate and non~olatile element electrodes and reoxidized to provide thinner oxides 5, 6 to dielectrically isolate the substrate from the three sequentially deposited, patterned (by conventional photol.ithographic techniques), etched and oxidized polysilicon layers forming the programming electrode l, the floating gate 2, the erase/store electrode 3 and other circuit elements and interconnecting leads. These thermal oxides 5, 6 separating the polysilicon layers from the substrate are grown by conventional techniques to be about lO00 Angstroms thick in the illustrated embodiment. The values of substrate doping and oxide thickness under the control ~ates of the various transistors such as coupling transistor 8 may be chosen to give a desired threshold voltage in accordance with conventional design techniques and the gate of transistors such as transistor 8 may be formed from any polysilicon layer, consistent with cell design.
The first polysilicon layer is oxidized at approximately lO00 degrees C. and a similar procedure is performed on the second layer of polysilicon in order to introduce asperities 56 on the upper surfaces of these polysilicon layers as indicated by the serrations in FIGURES 3 and 4. The - 35 asperities formed under such conditions may have an areal density of about 5 x 10 per cm2, an ; average base width of 456 Angstroms and an average height of 762 Angstroms. The asperities produce very high fields when relatively low voltages are applied between overlapping or adjacent polysilicon layers. When the asperities are biased relatively negatively, these fields are sufficient to inject electrons into the relatively thick oxides 42t 43 (having a thickness of 800-1000 Angs~roms) while applying on the average a relatively low voltage (e.g., 25 volts or less) across the oxide. When only one adjacent surface of the polysilicon layers has asperities, a diode-like effect is provided because the tunneling o~ electrons is not enhanced lS from the flat surface when the asperities are : relatively positively biased. Asperities may be generated over a range of conditions and are not limited to the particu1ar example stated above. ~s indicated, the various layers 50, 52, 54 of polysilicon forming the elctrodes and floating gate of the device 10 are insulated from each other by silicon dioxide dielectrics~ As shown in FIGURES 2, 3 and 4, the overlapping region 18, 43 between the floatin~ gate 2 and the programming electrode 1 is -the area in which electrons tunnel through theseparating oxide from the programming electrode to the floatin~ gate, when a sufficiently relative~ly positive voltage is present on the floa~ing gate~
.. . The overlapping region 25 between the erase/store gate 3 and ~he floating gate 2 is the area in which electrons tunnel through the separating oxide 42 from the floating gate when a sufficiently relatively positive voltage is present on the gate 3. Gate 3 overlaps region 7 to form a coupllng 3s capacitor 21 o capacitance CC3 determined by the .:

overlap area and the thickness of insulation 6, the voltage difference of the erase/store gate 3 relative to the bias electrode 7 and the doping density N of the bias electrode. The floating gate 2 also overlaps the bias electrode 7, forming a coupling capacitor 22 having a capacitance CC2 determined by the overlap area, thickness of insulation 5, voltage difference of the floating gate 2 relative to the bias electrode 7 and the doping density N. The region 9 is a standard, heavily doped region which is nor~ally formed during the process step that forms the source drain regions of the various transistors. Capacitance element 25 having a capacitance CE, capacitance element l9 having a capacitance Csub, and capacitance element 18 having a capacitance Cp are formulated as snown in the figures, and are realized from properties of various of the structural elements of the device 10. In this connection, split capacitor 23 having a total capacitance Cl is formed between the first polysilicon layer and the third polysilic~n layer.
This capacitor, plus the capacitance of the gate of transistor 8 causes node 29 to rise slower than node 30 of the RAM cell 12 during the power-up cycle 2~ (involving application of power with potential Vcc) provided that transistor 2Q is in a nonconductive state. Capacitor 17 having a capacitance C2 is formed between the first polysilicon layer and the substrate area. The total capacitance of capacitance C2 and the gate capacitance o~
transistor 20 is set to be substantially larger that the total capacitance of capacitance Cl and the gate capacitance of transistor 8, to cause node 30 to rise more slowly than node 29 during power-up.
3S Capacitor 18 having a capacitance Cp is formed between the polysilicon floating gate of transistor 20, and the first polysilicon layer 50. This capacitor provides a structure for tunneling of electrons from the programming electrode 1 of the first polysilicon layer 50, to the floating gate 2.
Tunneling occurs when a sufficiently large electric field is developed across the capacitor 1~ during "programmin~ rase capacitor 25 having a capacitance CE is formed between the erase/store electrode 3 of the third polysilicon layer 54, and the floating gate 2. This capacitor 25 provides a structure for tunneling electrons ~rom the ~loating gate 2 to the erase/store electrode 3 ("erasing").
Tunnel~ing occurs when a sufficiently large electric field is developed across the capacitor 25.
Capacitor 25 also couples some potential to the floating gate during programming. Capacitor 21 having a capacitance of CC3 is formed between the erase/store electrode 3 to the substrate n-implanted bias electrode 7. This capacitor provides electric potential coupling to the floating gate 2 through capacitor 22 when transistor 8 is off. Capacitor Z2 having a capacitance CC2 is formed between floating gate 2 and the substrate n-implanted area of the bias electrode 7. When transistor 8 is in a nonconducting state, electric potential couples rom - the erase/store electrode 3 (through capacitor 21) to bias electrode 7, then from the bias electrode 7 to the floating gate 2 (through capacitance 22). If volta~e is applied to electrode 3 when transistor 8 is in a conducting state, bias electrode 7 is held at ground potential, and capacitance 22 holds the - floating gate potential low so that a large field can develop across capacitor 25. Capacitor 19 having a capacitance Csub is an undesired parasitic-p-n junction capacitor which decouples capacitor 22 and capacitor 21 from the erase/store electrode 3 during programming. This capacitor should be minimized. As indicated, transistor 8 is a transistor which senses the state of the RAM cell 12 and instructs the nonvolatile element 14 to "program" or "erase", depending on the memory state of the RAM cell 12, in order to copy the memory state of the RAM cell. Transistor 20 is a transistor which, in turn, communicates the state of the nonvolatile element 14 to the RAM cell 120 The ~unctions of these capacitances and capacitor 21, capacitor 22, capacitor 17 and transistors 8 and 20 will be elaborated upon in the description o~ the cell operation.
By employing an n-channel silicon gate three-]ayer polysilicon fabrication process, a manufacturable, compact, easy~to-operate nonvolatile static RAM device 10 may be provided as illustrated which can be used, for example, in microcomputer applications. An array of the memory devices can be used as a conventional RAM with po~er-down data storage capability ("crash protection"), or as a volatile RAM coexistent with a nonvolatile R0~. The cell can store two independent bits of data, one in - the R~M section 12, and one in the nonvolatile section ~4 o~ each cell.
It is important to note that the RAM cell 12 may function independently of the R0~ cell 14 and that nonvolatile storage does not necessarily occur with every conventional R~ "write" cycle. Instead, the nonvolatile storage occurs only ~hen a "store"
command is given to the memory array~ In RAM arrays of the device 10, the arrays may be used as a system for placing a RAM data pattern into the corresponding nonvolatile floating gate elements.
In this connection, the corresponding nonvolatile element portion of the array may function as an electrically alterable read only memory (ROM). The nonvolatile element 14 may be referred to as a ROM, for simplicity of reference in the following description. Because data may be stored in the nonvolatile ROM element 14 for future recall to the RAM cell 12, this data storage function may desirably be used for a total power-down situation or other such circumstance in which a conventional P~ would irretrievably lose its data.
Furthermore, because the R~M portion 12 and the ROM portion 14 of the cell 10 are "transparent"
to one another, the RAM section can be operated substantially independently of the data state of the ROM section. Because of this feature and because the R~M section copies the true data state of the ROM section upon power~up, an arbitrary starting program such as is conventionally stored in mask programmable ROM memories can be loaded automatically into the RAM array section of a memory array of devices 10 when system power returns. The stored data or program of the ROM may be retained 2S substantially indefinitely for recall to the corresponding ~AM cells. In the operation of the device 10 while power at potential Vcc is being supplied to the R~ cell 12, the memory state content of the static RAM section 12 can be copied into the ROM section 14 by applying a single "store"
pulse of about 25 volts to the erase/store electrode 3 by means of suitable control circuitry (not shown) which may be of on-chip or off-chip design. When power is removed from the ~AM cell 12 the ROM 14 holds that data substantially indefinitely, or until .

it is altered. When operating power (Vcc) is again applied to the static R~l 12 it automatically nondestructively copies the date of the ROM portion 14. The RAM 12 thus remembers where it "left o~f"
when the power was removed, or more precisely, when the 25 volt "store" command pulse last occurred.
In operationl node 29 of the bistable RAM
cell 12 will be either in a higher or in a lower electric potential state, with node 30 having the opposite electric potential state. The capacitive coupling means for coupling the RAM cell 12 to the nonvolatile element 14 is adapted to sense the memory state of the RAM cell 12, and based on such sensing, determines whether to inject electrons onto the floating gate 2 or remove electrons from the gate 2 in order to copy the memory state of the RAM
cell 12. In this connection, when node 29 is high, transistor 18 is conductive and the drain of transistor 8 couples the large inversion plate (n-t~pe) of the capacitors 21 and 22 to ground. If the "store" pulse of about 25V is appl~ed to erase/store electrode 3, an electric field will develop across capacitor 25 which is sufficiently large to tunnel electrons from the floating gate 2 to the electrode 3. The floating gate 2 is in turn the gate of transistor 20. Now, if the entire - circuit 10 is "powered-down" (all voltage removed) and then RAM supply voltage Vcc is powered ~ack up to approximately 5 volts, the state of the non-volatile element 14 will be copied to the RAM cell 12. In this connection, the depletion load transistors 31, 32 will attempt to pull up nodes 29 and 30, respectively. However, because transistor 20 is conductive (its gate is charged positive) and because the capacitance of node 30 plus the - ~ ~
3~

capacitance C2 of capacitor 17, plus the gate capacitance of transistor 20 is greater than.the capacitance of node 29 plus capacitance Cl of capacitor 23 plus the gate capacitance of transistor 8, node 30 will pull up slower than node 29 in the illustrated embodiment, when node 29 reaches approximately 1 volt, the cross-coupled amplifier will engage and set node 29 high and node 30 low.
On the other hand, when node 29 is initia]ly low, transistor 8 is off (nonconductive) and the large n-inversion plate of capacitors 21, 22 of the bias electrode 7 is allowed to float. If a "store" pulse of about 25 volts is applied, to the erase~store electrode 3, capacitor 21 will couple potential through capacitor 22 to the floating gate 2. Also, the 25 vol~ "store" voltage pulse will couple somewhat through capacitor 25 to the floating gate 2~ The net effect is to produce a large enough field across capacitor 18 to cause electrons to tunnel into the floating gate 2 from the programming electrode 1 and charge the floating gate negative.
With the floating gate negative, transistor 20 will be of (noncoductive).
The entire circuit may then be powered down, and then the Vcc supply may be powered up. As before, transistors 31, 32 attempt to pull up nodes 29, 30 respectively. However, in this case, the capacitance of node 29 plus the capacitance Cl of capacitor 23 plus the gate capacitance of transistor 8 is larger than the capacitance of node 30 (transistor 20 is off). Node 30 will accordingly be slightly higher than node 29 and will accordingly cause the cross-coupled amplifier to engage, setting node 30 high and node 29 low as was the case when previous store pulse command occurred to copy the R~M state to the floating gate element 14.
Accordingly it will be seen that in the operation of the device 10, when the RA~S cell 12 is in a certain memory state (node 29 high and node 30 low, or node 29 low and node 30 high) the ROM
section 14 will copy that state in such a way that upon power-up the RA~S cell section 12 will directly copy back the same state from the ROM section 14.
For recalling data from the nonvolatile ROM
cell 14 to the R~M cell 12/ when the voltage supply Vce is powered up ~again~ various capacitance relationships should be fulfilled. For recalling data to the R~ cell 12 from the ROM cell 14 under circuit conditions when transistor 20 is off, the capacitance Cl of capacitor 23 plus the gate capacitance of transistor 8 should be large enough to insure that node 29 will always pull up more slowly than node 30 and cause the cross coupled amplifier of the RAM cell 12 to set the node 29 low (off), and node 30 high (on).
For recalling data to the R~1 cell 12 from the ROM cell 14 under conditions when the transistor 20 is on, capacitance C2 of capacitance 17 plus the gate eapacitance of transistor 20 should be sufficiently greater than capacitance Cl of eapaeitor 23 plus the gate capacitance of transistor 8 to cause the cross coupled amplifier of the RAM
eell 12 to set the node 30 low and the node 29 high.Representative capacitance values of these eapacitances of the illustrated embodiment 10 are as follows:
Node 29 approximately 0.10 pieofarads Node 30 (with transistor 20 on) appro~imately 0.20 pico~arads Node 30 (with transistor 20 off) approximately 0.05 picofarads.
The described nonvolatile static RAM cell also has further advantages due to the presence of a self-regulating and comensation circuit present in the nonvolatile device which tends to increase the number of useful cycles in the nonvolatile device as described in the above referred to co-pending application Serial No. 344,354. As indicated, an array of a number of such memory devices may readily be formed on a substrate chip with suitable support circuitry and interconnections to provide a nonvolatile addressable static RAM memory device. The data of the entire RAM section array may be readily copied to the cor-responding ROM section array, and recopied to the RAM array upon power up of the RAM array.
While the present invention has been particularly described with respect to the illustrated embodiment, it will be appreciated tha-t various alterations; modifications and ; adaptations may be made based on the present disclosure, and are intended to be within the ~cope of the pxesent invention~
Various of -the features of the invention are set ~orth in the followin~ clai~.s.

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jr/ ~

Claims (14)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A nonvolatile memory device comprising a volatile semiconductor memory cell for storing binary data, means for reading from and writing to said volatile memory cell, a non-volatile memory means, comprising an electrically insulated floating gate conductor, for storing binary data as one of two different electric charge levels on said floating gate conductor, means for capacitively coupling said volatile memory cell to said nonvolatile memory means and for copying the memory state of said bistable memory cell to the floating gate conductor at a predetermined one of said electric charge levels, and means for capacitively coupling said floating gate conductor of said nonvolatile memory means to said volatile memory cell for copying the memory state of said floating gate to said volatile memory cell upon application of electrical power to said volatile memory cell.

2. The cell of Claim 1 in which the volatile memory cell is a bistable cross-coupled flip-flop memory cell.

3. The cell of Claim 1 in which the memory cell is a six-transistor n-channel static random-access memory cell.

4. The cell of Claim 1 in which the memory cell is a four-transistor n-channel static random-access memory cell.

5. A cell in accordance with Claim 1 in which said memory cell is a six-transistor CMOS/SOS static random-access memory cell.

6. The cell of Claim 1 in which said memory cell is a six-transistor bulk CMOS static random-access memory cell.

7. A cell in accordance with Claim 1 wherein said volatile memory cell is a dynamic memory cell.

8. A cell in accordance with Claim 1 wherein the non-volatile memory means comprises a plurality of electrodes and wherein at least two of said electrodes and said floating gate are constructed with three layers of polysilicon.

9. A cell in accordance with Claim 1 wherein asperities are provided to promote electron flow to and from said floating gate conductor component of said nonvolatile memory means.

10. A cell in accordance with Claim 1 wherein said means for copying the memory state of said cell to said floating gate conductor includes an electrode positioned capacitively adjacent said floating gate conductor, such that application of a single "store" voltage control signal to said electrode causes the present memory state of said volatile memory cell to be trans-ferred into said nonvolatile memory means.

11. A cell in accordance with Claim 1 in integrated circuit array with a plurality of like cells.

12. The cell of Claim 1 wherein said means for reading from and writing to said volatile memory cell comprises a single erase/store gate capacitively coupled to said floating gate conductor, wherein a single positive polarity voltage enables both the charging and discharging of said floating gate conductor.

13. A method for nonvolatile storage of binary information in a semiconductor integrated circuit, comprising the steps of capacitively sensing the one of two binary memory states of a volatile semiconductor memory cell having binary information stored therein, causing a predetermined one of two electric charge levels to be created on a dielectrically isolated floating gate conductor corresponding to said one capacitively sensed memory state of said volatile memory cell without altering the memory state of said volatile memory cell, and causing said volatile memory cell to capacitively sense the current charge level of said floating gate when power is first coupled to said volatile memory cell, such that the memory state of said volatile memory cell corresponds to said charge level of said floating gate.

14. A method in accordance with Claim 13 wherein the step of providing a predetermined one of two electric charge levels on said floating gate conductor comprises the step of coupling a single positive polarity voltage to an erase/store gate capacitively coupled to said floating gate conductor.