CA1132720A - Two terminal field effect resistor - Google Patents
Two terminal field effect resistorInfo
- Publication number
- CA1132720A CA1132720A CA000316704A CA316704A CA1132720A CA 1132720 A CA1132720 A CA 1132720A CA 000316704 A CA000316704 A CA 000316704A CA 316704 A CA316704 A CA 316704A CA 1132720 A CA1132720 A CA 1132720A
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- Canada
- Prior art keywords
- resistor
- field effect
- layer
- semiconductor layer
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
Abstract
ABSTRACT OF THE INVENTION
A bilateral, two terminal current limiting field effect resistor device that is relatively insensitive to both positive and negative input overvoltages. The disclosed field effect re-sistor device may be utilized to protect the integrity of the gate oxide capacitance of a metal-oxide-semiconductor (MOS) device. In a preferred embodiment, the field effect resistor device is fabri-cated with a n+n-n+ or p+p-p+ semiconductive layer deposited over an insulating (e.g. sapphire) substrate. By virtue of its unique structure the present field effect resistor device has a linear code of operation for low input voltages and a saturation mode of opera-tion for higher overvoltages.
The invention described herein was made in the course of or under a contract or subcontract with the department of the United States Air Force.
A bilateral, two terminal current limiting field effect resistor device that is relatively insensitive to both positive and negative input overvoltages. The disclosed field effect re-sistor device may be utilized to protect the integrity of the gate oxide capacitance of a metal-oxide-semiconductor (MOS) device. In a preferred embodiment, the field effect resistor device is fabri-cated with a n+n-n+ or p+p-p+ semiconductive layer deposited over an insulating (e.g. sapphire) substrate. By virtue of its unique structure the present field effect resistor device has a linear code of operation for low input voltages and a saturation mode of opera-tion for higher overvoltages.
The invention described herein was made in the course of or under a contract or subcontract with the department of the United States Air Force.
Description
7~0 BACKGROU~ID OF THE INVENTION
1. Field of the Invention.
This invention relates to a bilateral, ~"o terminal current limiting field effect resistor device that is fabricated by silicon on sapphire (SOS) techniques.
1. Field of the Invention.
This invention relates to a bilateral, ~"o terminal current limiting field effect resistor device that is fabricated by silicon on sapphire (SOS) techniques.
2- Statement of the Prior Art.
MOS gate protection devices that are fabricated by silicon on sapphire (SOS) techniques have been proven to be less reliable than their bulk counterparts. Because of the relatively thin silicon film used for device fabrication, it is difficult to achieve low dynamic impedance junctions and low current densities.
Further, if conventional laterial device isolation is used li.e.
island etch), junctions terminated at ;sland edges can display anomalous behaviour including soft breakdown characteristics, high leakage, and bias-temperature instability. Moreover, the conven-tional gate protection approaches are inadequate for high performance applications, where severe design constraints may be encountered. For example, several typical high performance environ-mental requirements include survival under high bias-temperature stress, nuclear radiation, and electro-magnetic pulses.
In the range of voltages from 300 to 1,000 volts, the prior art SOS gate protection networks are not adequate due to the failures of convèntional SOS linear resistors. Catastrophlc failure (i.e. burn-out) of the conventional SOS linear resistor due to high current density induced conductivity variations and the resultant for~ation of localized hot spots is a major limitation of the prior art SOS gate protection networks. The conventional SOS current limiting linear resistor is known to fail at vo:ltage levels up to 350 volts for short (01. micro~econd) transient voltag~
pulses. At sufficientLy higll volt<lges (in excess ot 1,000 volts) spark gaps can provide effective gatc protection. rhus, there is a range of voltages (from approximately 300 to 1,000 volts) where the prior art gate protection networks are not adequate due to ~he failure o~ the conventional SOS linear resistor. The current and power handling capabilities of the conventional SOS linear resistor can be increased by increasing the area of the SOS resistor. However, this approach is not desirable for I.SI applications, in as much as the ~raction of the semiconductor chip area that is available for the gate protection network is limited by practical design constraints ~e.g. it would be most desirable to achieve maximum protection within the smallest possible area~.
The ~ollowing U.S. patents are representative of conventional semiconductive devices:
MOS gate protection devices that are fabricated by silicon on sapphire (SOS) techniques have been proven to be less reliable than their bulk counterparts. Because of the relatively thin silicon film used for device fabrication, it is difficult to achieve low dynamic impedance junctions and low current densities.
Further, if conventional laterial device isolation is used li.e.
island etch), junctions terminated at ;sland edges can display anomalous behaviour including soft breakdown characteristics, high leakage, and bias-temperature instability. Moreover, the conven-tional gate protection approaches are inadequate for high performance applications, where severe design constraints may be encountered. For example, several typical high performance environ-mental requirements include survival under high bias-temperature stress, nuclear radiation, and electro-magnetic pulses.
In the range of voltages from 300 to 1,000 volts, the prior art SOS gate protection networks are not adequate due to the failures of convèntional SOS linear resistors. Catastrophlc failure (i.e. burn-out) of the conventional SOS linear resistor due to high current density induced conductivity variations and the resultant for~ation of localized hot spots is a major limitation of the prior art SOS gate protection networks. The conventional SOS current limiting linear resistor is known to fail at vo:ltage levels up to 350 volts for short (01. micro~econd) transient voltag~
pulses. At sufficientLy higll volt<lges (in excess ot 1,000 volts) spark gaps can provide effective gatc protection. rhus, there is a range of voltages (from approximately 300 to 1,000 volts) where the prior art gate protection networks are not adequate due to ~he failure o~ the conventional SOS linear resistor. The current and power handling capabilities of the conventional SOS linear resistor can be increased by increasing the area of the SOS resistor. However, this approach is not desirable for I.SI applications, in as much as the ~raction of the semiconductor chip area that is available for the gate protection network is limited by practical design constraints ~e.g. it would be most desirable to achieve maximum protection within the smallest possible area~.
The ~ollowing U.S. patents are representative of conventional semiconductive devices:
3,9679295 June 29, 1976 to Roger Green Stewart 3,958,266 May 18, 1976 to Terry George Athanas 3,898,68~ August 5, 1975 to Uryon S. Davidsohn~
3,868,721 February 25, 1975to Uryon S. Davidsohn 3,706,91g December 19, 1972to Frank J. Barone 3,696,276 October 3, 1972 to Bernard W. Boland However, none of the above patents shows or suggests a bilateral, two terminal ield effect resistor device for limiting overvoltages of either polarity, and which device is fabricated by silicon on sapphire techniques and adapted to operate in a linear mode for low input voltages or a saturation mode for higher overvoltages.
.~
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SUMMARY OF THE INVE~TIO~l Briefly, and in general terms, a two terrninal, current limitin~ field effect resis~or device is disclosed that is suitable for use in a circuit to pro~ect the gate oxide capacitance of an MOS type transistor from damage as a result of transient and other overvoltage signals. The field effect resistor device is fabricated to include an insulating substrate formed ~rom sapphire, or the like.
A thin layer of silicon, either n-type or p-type, is chemically deposited over the insulating substrate and is selectively doped to form either n n n or p p p adjacent semiconductive regions. A thin dielectric layer of thermal silicon dioxide overlies the n or p region of the silicon layer. To provide symmetry for bilateral operation (i.e.
to limit both positive and negative overvoltages), a pair of gate regions is defined in the thermal silicon dioxide layer. A passivation layer of silicon nitride is selec-tively deposited on the silicon dioxide layer. A metaliz-ation layer covers the gate regions formed in the silicon dioxide layer and forms the contact to the n (p ) regions.
The entire struction may be covered with a layer of insula-ting material, such as silox.
In broad terms, the invention consists of a field effect resistor comprising: a semiconductor layer composed o-f mono-crystalline semiconductor material of a first conductivity type for providing an electrical resistance having a sub-stantially linear resistive operating characteristic for voltages below the saturation voltage thereof and a constant current operating characteristic for voltages above the saturation voltage thereof; conductor means comprising first and second spaced terminals making electrical contact with said semiconductor layer and functioning to apply a potential ~1--~;, , of predetermined m~gnitucle ~nd polarity thereto, and first and second spac~d control elcctr~des making electrical cont~ct with said first and said second tc~rmin~lls respec~iv~ly; ~
dielectric region overlying and making contact with the surface of a porti~n of said semiconductor layer lying between said first and second spaced terminals, said first and second con-trol electrodes extending o~er at least a portion of said dielectric region and functioning to create a depletion region in said semiconductor layer beneath at least a portion o~ one of said control electrodes.
By virtue of the diselosed strueture, the field effeet resistor deviee of the present invention is adapted to operate in a linear mode for relatively low voltages or a saturation mode during relatively high overvoltages that exeeed the normal signal-swing range of the deviee.
For relatively high voltages, the operation of the field effeet resistor deviee is based upon the prineipal of semieonduetor depletion. More partieularly, the instant bilateral SOS field effeet resistor has a region of eon-stant eurrent for voltages of either polarity in exeess ofthe saturation voltage. Therefore, due to power dissipa-tion eonsiderations, the SOS field effeet resistor of the present invention is a reliable eurrent limiting resistor whieh is adapted to endure overvoltages of inereased magnitude (relative to the linear SOS resistors of the prior art) before voltage failure or breakdown oeeurs.
Embodiments of the invention are illustrated by way of example in the aeeompanying drawings.
.,,_, .
.d~
Bl~ DESCRIl'rION 01 ~ DRAWINC;S
FIG. 1 is a prior art yate oxide capacitor protection network including d conventional series connected current limit-ing SOS linear resistor.
FIG. 2 sho~/s the physical structure of a conven~ioral SOS linear resistor.
FIG. 3 represents the electrical current-voltage characteristics of the conventional SOS linear resistor of FIG. 2.
FIG. 4 shows the physical structure of the bilateral SOS current limiting field effect resistor device which forms the present invention.
FIG. 5d is an expanded view of the physical structure ~, of the SOS field effect resistor device of FIG. 4, FIG. Sb represents the electrical characteristics of the SOS field effect resistor device of the present invention for relatively positive input voltage signals.
FIGs. 6a and 6b illustrate the locations of the respective depletion regions occurring within an SOS field effect resistor device of the present ir,vention to achieve current satura-tion with high voltage input signals of either polarity.
FIG. 7 shows the electrical characteristics of the con-ventional SOS linear resistor of FIG. 2 with respect to 'he electrical - characteristics of the bilateral SOS current limiting fleld effect resistor device of FIG. 4.
FIG. ~ represents the ideal bidirectional electrical characteristics of the SOS current limiting field ~,fect resistor of the present invention in both the linear and saturation modes of operati Gll .
Certain features of the apparatus disclosed are 3() claimed in divisional application Serial No. 384,758 filed August 27, 1981.
: - 6 7,~
DESC~IPTION OF THE P~EFERRED EMBODI~ENT
A well known circuit technique for protectlng the gate oxide capacitance of an MOS type transis~or (e,g, FET) device from damage that may be caused by excessive voltage or transient input signals is the voltage divider network illustrated in FIG, 1.
Damage to the ~OS gate oxide can result from high transient over-voltages at the input terminal of a bonding pad, The gate oxide capacitance of the MOS device to be protected is represented by a capacitor 1. The prior art protection çircuit typically includes two clamping diodes 2 and 3 and a conventional linear (i.e. ohmic)~
current limiting resistor 4 connected in series between the bonding pad voltage input terminal 5 and a first common electrical junction 6 formed with one plate of capacitor 1, A first clamping diode 2 is connected between a source of relatively positive voltage +VDD
and common electrical junction 6. A second clamplng diode 3 is connected between the first co~mon electrical junction 5 and a second common electrical junction 7 formed with the second plate of capacitor 1 and a relatively negative source of voltage (e.g, ground), whereby the conduct;on paths of clamping diodes 2 and 3 are connected in electrical series to provide a low resistance shunt path, When a relatively positive input voltage signal +Vj which is greater than the sum of the VDDvoltage and the forward voltage drop o~ diode 2 is applied to input terminal 5, a positive current path is formed, which current path includes the linear current limiting resistor 4, clamping diode 2, and the relatively positive voltage source +VDD. No current passes through clamping diode 3, inasmuch as diode 3 is rendered in a back biased condition with respect to a positive applied voltage. Should a relatively negative voltage . t input signal -Vj be applied to input terminal 5, a correspond;ng negative current path is formed, which current path includes the linear current limiting resistor 4, the c1amping diode 3, and ground (via electrical junction 7). No current passes through clamping diode 2, inasmuch as diode 2 is rendered in a back biased condition with respect to a negative applied voltage.
As shown in FIG. 2, the structure of a conventional linear resistor 4 may be fabricated by the formation of a suitable layer of either p+ or n+ silicon on an insulating (e~g. sapphire) substrate. Either a silicon or aluminum gate integrated circuit fabrication process can be used to make the conventional silicon on sapphire linear resistor 4.
Ho~lever, a limitation in the prior art protection cir-cuit of FIG. 1 resides in the relatively low failure voltage of the conventional silicon on sapphire (SOS) linear resistor 4.
When a relatively high positive or negative voltage signal ~Vj is applied to input terminal 5, a corresponding large voltage drop occurs across the terminals of the linear resistor 4. Therefore, as is known to those skilled in the art, the linear resistor 4 dissipates large amounts of power. Catastrophic failure of the linear current limiting resistor 4 can be caused by high current density induced conductivity variations and resultant formations of localized hot spots. The failure thresholds of conventional protec-tion circuits are determined by the power dissipation or energy deposltion capabilities of the protection circuit. As illustrated in FIG. 3 the current lim;ting S05 linear resistor 4 typically fails at a relatively low voltage level, desisnated VF. Therefore, the conventional protection circuit of FIG. l is highly inefficient for protecting the gate oxide capacitance of an MOS transistor device.
~ ~L;~7 ~0 In accordance with the instant invention, FIG. 4 illustrates a preferred embodiment for the fabricàtion of a t~"o-terminal silicon on sapph;re field efFect resistor device 10, which device provides an overall improvement in the pulse-po~er electrical overstress survivability/failure threshold relative to prior art gate protection circuits. The construction of the field effect resistor device 10 includes a non-conductive sub-strate 12. Substrate 12 is formed from a suitable material having a high breakdown voltage characteristic, such as sapphire, or the like. Overlying the insulating substrate 12 is a layer like body comprising three adjacent regions of semiconductive material.
In a preferred embodiment, a layer of lightly doped mono-crystalline n- silicon is first chemically deposited or grown on the substrate 12. First and third regions 14 and 16 are then formed by heavily doping portions of the n- layer with a dopant to produce n+ type silicon. The second region 15 between regions 14 and 16 on substrate 12 continues to be formed from the lightly doped n- type silicon. Although the field effect resistor 10 that is illustrated in FIG. 4 is fabricated as n+n-n+ stru~ture, it is to be understood tha-t the resistor 10 may also be fabricated as p-l-p-p+ structure (and as either an aluminum gate or silicon gate device).
To provide the required symmetry for bilateral operation (for limiting both positive and negative overvoltages), thin gate silicon dioxide regions 18, 20, and 21 are thermally gro~/n at high termperatures over the n semiconductive region 15. The gate regions 18 and 20 provide a change in the resistance of the field effect resistor device 10 to achieve a non-linear resistance charac-teristic at high input voltages (as will be discussed in greater detail hereinafter).
,~.s,~ .
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A thin passivation layer 22 is deposited over a portion of the thermal silicon dioxide layer 21. Typically, the passiva-tion layer 22 is forlned from silicon nitride and is responsible for chemical and electrical passivation (i.e. to prevent undesirable chemical contamination or electrical changes in the underlying thermal silicon dioxide layer 21). Moreover, the silicon nitride layer 22 also increases the gate-to-silicon breakdown voltage in the dielectric layer 21. A first metalization layer 24, fabricated from aluminum or the like, is defined over portions of the insulating substrate 12, the first n~ sem;conductive region 14, the thermal silicon dioxide layer 21, and the silicon nitrlde passivation layer 22. The first metalization layer 24 terminates in an overhang 25 to be electrically connected to one of the thin gate oxide regions 20. A second metalization layer 26 is defined over portions of the insulating substrate 12, the third n semiconductive region 16, the thermal silicon dioxide layer 21, and the silicon nitride passiva-tion layer 22. The second metalization layer 26 terminates in an - overhand 27 to be electrically connected to a second of the thin gate oxide regions 1~. Each of the metalization layers 24 and 26 and the silicon nitride passivation layer 22 is covered by a suitable protec~ive coating 32 such as, for example, silox glassivation. The protective coating 32 is fabricated from an insulating material and is intended to protect the integrity of the two terminal field effect resistor device 10 from environmental and physical damage as a result of improper handling.
A first terminal (e.g. 29) of the two terminal device 10 is connected between the first metalization layer 2~ and a suitable source of relatively negative reference potential -VR, such as ground.
The second terminal (e.g. 30) of the two terminal device 10 is ...
'7~(3 connected between the second metalization layer 26 and d suitable source o~ relatively positive reference potential ~VR.
The operation of the presently disclosed t~o terminal SOS field effect resistor 10 ;s discussed ~/hile referring con-currently to FIGs. Sa and 5b. ',Jhen the source of reference potential ~VR provides a relatively small voltage signal of either polarity throughout the normal signal-swing range of device 10 (e.g. to approximately 50 volts), the field effect resistor device 10 has a linearly resistive (i.e. ohmic) characteristic. By virtue of the adjacent n+n n+ silicon regions 14, 15, and 16, the t~o terminal SOS field effect resistor device 10 is essentially a linear resistor for voltages VR below the saturation voltage VSAT.
For voltages ~VR in excess of both the saturation voltase VSAT and the normal signal-swing range of device lO, the operation of the field effect resistor device lO is based upon the principal of semiconductor deple~ion. That is, when the source of reference potential +VR provides a high voltage signal of either polarity, a voltage gradient occurs w;thin the lightly doped n silicon region 15, and a high electric field is produced in the areas overlying the n region 15 and underlying one of the overhangs 25 or 27 of a corresponding one of the metalization layers 24 or 26. ~ore particu-larly, depending upon the polarity of the voltage signal +VR
received at terminals 29 and 30, the area that experiences the presence of a high electric field includes portions of both the silicon nitride passivation layer 22 and the thermal silicon dioxide layer 21 which lie underneath one of the gate regions 18 or 20. This is best represented in FIG. Sa. As a result of the voltage gradient ~lithin the n silicon region lS, the gate-to-silicon potential is the highest ~, , ~L~ 7 ~
at the edge of one of the gate regions 1~ or 20. For sufficiently high voltage signals ~VR in excess of the sakuration voltage ~V5 surface accumulation will occur at one end of the n silicon re-gion 15 under one gate region (e.g. 18), and surface depletion will occur at the other end of region 15 under the other sate region (e.g. 20). The location of the respective depletion regions occurring in the n region 15 of the field effect resistor device 10, relative to the polarity of the voltage signal +VR that is applied to terminals 29 and 30, is illustrated in FIGs. 6a and 6b.
Electrically bilateral opera~ion of the field effect resistor device 10 results from the physical symmetry of the device, as disclosed in greatest detail wh;le referring to FIG. 4. The deple tion region occurring in the lightly doped n silicon region 15 results in current pinchoff. That is, for voltages +VR of either polarity that exceed the saturation voltage +VsAT of the device 10, the SOS field effect resistor of the present invention operates with a constant current value +ISAT and reduced power dissipat;on.
The saturation range of operation is besk`lllustrated in F ~ Sc.
As illustrated in FIG. 5a, the dielectric of a gate region (e.g. 20) ln the silicon dioxide layer 21 is subjected to the ~reatest electrical field at the edge of that gate region. How-ever~ the likelihood of voltage breakdown of the gate dielectric 21 is minimized, in accordance with the present invention, by virtue of the dual layer gate dieleckric comprising the silicon nitride passivation layer 22 deposited over the thermal s;l;con dioxide layer 21. This dual layer dielectric (or sandwich) substantially decreases the probability that pin holes or other po;nt defects will cause localized regions of low d;electric stress. This can be explained by tl,~ relatively low probability of a nitride defect aligning vertlcally with an oxide defect. Moreover, the dielectric thickness is (Jrcatest at the edges of the gate reyions 18 and 20.
~hat is more, the resistive silicon depletion region 15 absorbs a portion of the total potential drop between the gate region 18 or 20 and the conducting (i.e. non-depleted) region of the silicon region 15.
FIG. 7 simultaneously shows the voltage-current charac-teristics of the conventional SOS linear resistor 4 (previously indicated while referring to FIG. 3) relative to the voltage-current characteristics of the SOS field effect resistor lO of the present inventiGn (previously indicated wh;le referring to FIG. 5b).
It is apparent that by virtue of the presently disclosed bilateral SOS field effect resistor lO, having a region of constant current ISAT for voltages of either polarity in excess of the saturation voltage YSAT, a reliable current limiting resistor is available which can endure overvoltages of an increased magnitude (in the range of approximately 400 volts) before voltage failure VF occurs.
Thus, the SOS field effect resistor 10 of the present invention is far more suitable to protect the gate oxide capacitance of an MOS
type tranststor device against high transient overYoltages than the conventional SOS current limiting linear resistor 4 of the prior art.
FIG. 8 is a detailed illustration of the preferred voltage-current characteristics of the presently disclosed two terminal, bilateral, current limiting silicon on sapphire field effect resistor device.
It will be apparent that while a preferred embodiment of the invention has been shown and descr;bed, various modifications and changes may be made without departing from the true spirit and scope of the invention. FGr example, to obtain increas~d protection from transient input signals, a plurality of the presently disclosed ... . .
- 3~ 7 ~C~
field effect resistors may be interconnected together in electrical series between a bonding pad and the gate electrode of the ~',OS de-vice to be protected. Moreover, in place of an insulating substrate, other suitab1e substrates, such as that formed by conventional junc-tion isolation techniques, may also be utilized to fabricate thepresent two terminal field effect resistor. What is more, the adjacent n n n regions 14, 15, and 16 may be formed from any suitable II-YI or III-Y compound semiconductor material1 and the like, or any combination thereof, such as, for example, gallium arsenids, aluminum arsenide, and cadmium telluride.
Having thus set forth a preferred embodiment of the instant invention, what is claimed is:
..... ,~.,_,. .. .
3,868,721 February 25, 1975to Uryon S. Davidsohn 3,706,91g December 19, 1972to Frank J. Barone 3,696,276 October 3, 1972 to Bernard W. Boland However, none of the above patents shows or suggests a bilateral, two terminal ield effect resistor device for limiting overvoltages of either polarity, and which device is fabricated by silicon on sapphire techniques and adapted to operate in a linear mode for low input voltages or a saturation mode for higher overvoltages.
.~
,f~
SUMMARY OF THE INVE~TIO~l Briefly, and in general terms, a two terrninal, current limitin~ field effect resis~or device is disclosed that is suitable for use in a circuit to pro~ect the gate oxide capacitance of an MOS type transistor from damage as a result of transient and other overvoltage signals. The field effect resistor device is fabricated to include an insulating substrate formed ~rom sapphire, or the like.
A thin layer of silicon, either n-type or p-type, is chemically deposited over the insulating substrate and is selectively doped to form either n n n or p p p adjacent semiconductive regions. A thin dielectric layer of thermal silicon dioxide overlies the n or p region of the silicon layer. To provide symmetry for bilateral operation (i.e.
to limit both positive and negative overvoltages), a pair of gate regions is defined in the thermal silicon dioxide layer. A passivation layer of silicon nitride is selec-tively deposited on the silicon dioxide layer. A metaliz-ation layer covers the gate regions formed in the silicon dioxide layer and forms the contact to the n (p ) regions.
The entire struction may be covered with a layer of insula-ting material, such as silox.
In broad terms, the invention consists of a field effect resistor comprising: a semiconductor layer composed o-f mono-crystalline semiconductor material of a first conductivity type for providing an electrical resistance having a sub-stantially linear resistive operating characteristic for voltages below the saturation voltage thereof and a constant current operating characteristic for voltages above the saturation voltage thereof; conductor means comprising first and second spaced terminals making electrical contact with said semiconductor layer and functioning to apply a potential ~1--~;, , of predetermined m~gnitucle ~nd polarity thereto, and first and second spac~d control elcctr~des making electrical cont~ct with said first and said second tc~rmin~lls respec~iv~ly; ~
dielectric region overlying and making contact with the surface of a porti~n of said semiconductor layer lying between said first and second spaced terminals, said first and second con-trol electrodes extending o~er at least a portion of said dielectric region and functioning to create a depletion region in said semiconductor layer beneath at least a portion o~ one of said control electrodes.
By virtue of the diselosed strueture, the field effeet resistor deviee of the present invention is adapted to operate in a linear mode for relatively low voltages or a saturation mode during relatively high overvoltages that exeeed the normal signal-swing range of the deviee.
For relatively high voltages, the operation of the field effeet resistor deviee is based upon the prineipal of semieonduetor depletion. More partieularly, the instant bilateral SOS field effeet resistor has a region of eon-stant eurrent for voltages of either polarity in exeess ofthe saturation voltage. Therefore, due to power dissipa-tion eonsiderations, the SOS field effeet resistor of the present invention is a reliable eurrent limiting resistor whieh is adapted to endure overvoltages of inereased magnitude (relative to the linear SOS resistors of the prior art) before voltage failure or breakdown oeeurs.
Embodiments of the invention are illustrated by way of example in the aeeompanying drawings.
.,,_, .
.d~
Bl~ DESCRIl'rION 01 ~ DRAWINC;S
FIG. 1 is a prior art yate oxide capacitor protection network including d conventional series connected current limit-ing SOS linear resistor.
FIG. 2 sho~/s the physical structure of a conven~ioral SOS linear resistor.
FIG. 3 represents the electrical current-voltage characteristics of the conventional SOS linear resistor of FIG. 2.
FIG. 4 shows the physical structure of the bilateral SOS current limiting field effect resistor device which forms the present invention.
FIG. 5d is an expanded view of the physical structure ~, of the SOS field effect resistor device of FIG. 4, FIG. Sb represents the electrical characteristics of the SOS field effect resistor device of the present invention for relatively positive input voltage signals.
FIGs. 6a and 6b illustrate the locations of the respective depletion regions occurring within an SOS field effect resistor device of the present ir,vention to achieve current satura-tion with high voltage input signals of either polarity.
FIG. 7 shows the electrical characteristics of the con-ventional SOS linear resistor of FIG. 2 with respect to 'he electrical - characteristics of the bilateral SOS current limiting fleld effect resistor device of FIG. 4.
FIG. ~ represents the ideal bidirectional electrical characteristics of the SOS current limiting field ~,fect resistor of the present invention in both the linear and saturation modes of operati Gll .
Certain features of the apparatus disclosed are 3() claimed in divisional application Serial No. 384,758 filed August 27, 1981.
: - 6 7,~
DESC~IPTION OF THE P~EFERRED EMBODI~ENT
A well known circuit technique for protectlng the gate oxide capacitance of an MOS type transis~or (e,g, FET) device from damage that may be caused by excessive voltage or transient input signals is the voltage divider network illustrated in FIG, 1.
Damage to the ~OS gate oxide can result from high transient over-voltages at the input terminal of a bonding pad, The gate oxide capacitance of the MOS device to be protected is represented by a capacitor 1. The prior art protection çircuit typically includes two clamping diodes 2 and 3 and a conventional linear (i.e. ohmic)~
current limiting resistor 4 connected in series between the bonding pad voltage input terminal 5 and a first common electrical junction 6 formed with one plate of capacitor 1, A first clamping diode 2 is connected between a source of relatively positive voltage +VDD
and common electrical junction 6. A second clamplng diode 3 is connected between the first co~mon electrical junction 5 and a second common electrical junction 7 formed with the second plate of capacitor 1 and a relatively negative source of voltage (e.g, ground), whereby the conduct;on paths of clamping diodes 2 and 3 are connected in electrical series to provide a low resistance shunt path, When a relatively positive input voltage signal +Vj which is greater than the sum of the VDDvoltage and the forward voltage drop o~ diode 2 is applied to input terminal 5, a positive current path is formed, which current path includes the linear current limiting resistor 4, clamping diode 2, and the relatively positive voltage source +VDD. No current passes through clamping diode 3, inasmuch as diode 3 is rendered in a back biased condition with respect to a positive applied voltage. Should a relatively negative voltage . t input signal -Vj be applied to input terminal 5, a correspond;ng negative current path is formed, which current path includes the linear current limiting resistor 4, the c1amping diode 3, and ground (via electrical junction 7). No current passes through clamping diode 2, inasmuch as diode 2 is rendered in a back biased condition with respect to a negative applied voltage.
As shown in FIG. 2, the structure of a conventional linear resistor 4 may be fabricated by the formation of a suitable layer of either p+ or n+ silicon on an insulating (e~g. sapphire) substrate. Either a silicon or aluminum gate integrated circuit fabrication process can be used to make the conventional silicon on sapphire linear resistor 4.
Ho~lever, a limitation in the prior art protection cir-cuit of FIG. 1 resides in the relatively low failure voltage of the conventional silicon on sapphire (SOS) linear resistor 4.
When a relatively high positive or negative voltage signal ~Vj is applied to input terminal 5, a corresponding large voltage drop occurs across the terminals of the linear resistor 4. Therefore, as is known to those skilled in the art, the linear resistor 4 dissipates large amounts of power. Catastrophic failure of the linear current limiting resistor 4 can be caused by high current density induced conductivity variations and resultant formations of localized hot spots. The failure thresholds of conventional protec-tion circuits are determined by the power dissipation or energy deposltion capabilities of the protection circuit. As illustrated in FIG. 3 the current lim;ting S05 linear resistor 4 typically fails at a relatively low voltage level, desisnated VF. Therefore, the conventional protection circuit of FIG. l is highly inefficient for protecting the gate oxide capacitance of an MOS transistor device.
~ ~L;~7 ~0 In accordance with the instant invention, FIG. 4 illustrates a preferred embodiment for the fabricàtion of a t~"o-terminal silicon on sapph;re field efFect resistor device 10, which device provides an overall improvement in the pulse-po~er electrical overstress survivability/failure threshold relative to prior art gate protection circuits. The construction of the field effect resistor device 10 includes a non-conductive sub-strate 12. Substrate 12 is formed from a suitable material having a high breakdown voltage characteristic, such as sapphire, or the like. Overlying the insulating substrate 12 is a layer like body comprising three adjacent regions of semiconductive material.
In a preferred embodiment, a layer of lightly doped mono-crystalline n- silicon is first chemically deposited or grown on the substrate 12. First and third regions 14 and 16 are then formed by heavily doping portions of the n- layer with a dopant to produce n+ type silicon. The second region 15 between regions 14 and 16 on substrate 12 continues to be formed from the lightly doped n- type silicon. Although the field effect resistor 10 that is illustrated in FIG. 4 is fabricated as n+n-n+ stru~ture, it is to be understood tha-t the resistor 10 may also be fabricated as p-l-p-p+ structure (and as either an aluminum gate or silicon gate device).
To provide the required symmetry for bilateral operation (for limiting both positive and negative overvoltages), thin gate silicon dioxide regions 18, 20, and 21 are thermally gro~/n at high termperatures over the n semiconductive region 15. The gate regions 18 and 20 provide a change in the resistance of the field effect resistor device 10 to achieve a non-linear resistance charac-teristic at high input voltages (as will be discussed in greater detail hereinafter).
,~.s,~ .
, ~ .
~L~ '7 ~
A thin passivation layer 22 is deposited over a portion of the thermal silicon dioxide layer 21. Typically, the passiva-tion layer 22 is forlned from silicon nitride and is responsible for chemical and electrical passivation (i.e. to prevent undesirable chemical contamination or electrical changes in the underlying thermal silicon dioxide layer 21). Moreover, the silicon nitride layer 22 also increases the gate-to-silicon breakdown voltage in the dielectric layer 21. A first metalization layer 24, fabricated from aluminum or the like, is defined over portions of the insulating substrate 12, the first n~ sem;conductive region 14, the thermal silicon dioxide layer 21, and the silicon nitrlde passivation layer 22. The first metalization layer 24 terminates in an overhang 25 to be electrically connected to one of the thin gate oxide regions 20. A second metalization layer 26 is defined over portions of the insulating substrate 12, the third n semiconductive region 16, the thermal silicon dioxide layer 21, and the silicon nitride passiva-tion layer 22. The second metalization layer 26 terminates in an - overhand 27 to be electrically connected to a second of the thin gate oxide regions 1~. Each of the metalization layers 24 and 26 and the silicon nitride passivation layer 22 is covered by a suitable protec~ive coating 32 such as, for example, silox glassivation. The protective coating 32 is fabricated from an insulating material and is intended to protect the integrity of the two terminal field effect resistor device 10 from environmental and physical damage as a result of improper handling.
A first terminal (e.g. 29) of the two terminal device 10 is connected between the first metalization layer 2~ and a suitable source of relatively negative reference potential -VR, such as ground.
The second terminal (e.g. 30) of the two terminal device 10 is ...
'7~(3 connected between the second metalization layer 26 and d suitable source o~ relatively positive reference potential ~VR.
The operation of the presently disclosed t~o terminal SOS field effect resistor 10 ;s discussed ~/hile referring con-currently to FIGs. Sa and 5b. ',Jhen the source of reference potential ~VR provides a relatively small voltage signal of either polarity throughout the normal signal-swing range of device 10 (e.g. to approximately 50 volts), the field effect resistor device 10 has a linearly resistive (i.e. ohmic) characteristic. By virtue of the adjacent n+n n+ silicon regions 14, 15, and 16, the t~o terminal SOS field effect resistor device 10 is essentially a linear resistor for voltages VR below the saturation voltage VSAT.
For voltages ~VR in excess of both the saturation voltase VSAT and the normal signal-swing range of device lO, the operation of the field effect resistor device lO is based upon the principal of semiconductor deple~ion. That is, when the source of reference potential +VR provides a high voltage signal of either polarity, a voltage gradient occurs w;thin the lightly doped n silicon region 15, and a high electric field is produced in the areas overlying the n region 15 and underlying one of the overhangs 25 or 27 of a corresponding one of the metalization layers 24 or 26. ~ore particu-larly, depending upon the polarity of the voltage signal +VR
received at terminals 29 and 30, the area that experiences the presence of a high electric field includes portions of both the silicon nitride passivation layer 22 and the thermal silicon dioxide layer 21 which lie underneath one of the gate regions 18 or 20. This is best represented in FIG. Sa. As a result of the voltage gradient ~lithin the n silicon region lS, the gate-to-silicon potential is the highest ~, , ~L~ 7 ~
at the edge of one of the gate regions 1~ or 20. For sufficiently high voltage signals ~VR in excess of the sakuration voltage ~V5 surface accumulation will occur at one end of the n silicon re-gion 15 under one gate region (e.g. 18), and surface depletion will occur at the other end of region 15 under the other sate region (e.g. 20). The location of the respective depletion regions occurring in the n region 15 of the field effect resistor device 10, relative to the polarity of the voltage signal +VR that is applied to terminals 29 and 30, is illustrated in FIGs. 6a and 6b.
Electrically bilateral opera~ion of the field effect resistor device 10 results from the physical symmetry of the device, as disclosed in greatest detail wh;le referring to FIG. 4. The deple tion region occurring in the lightly doped n silicon region 15 results in current pinchoff. That is, for voltages +VR of either polarity that exceed the saturation voltage +VsAT of the device 10, the SOS field effect resistor of the present invention operates with a constant current value +ISAT and reduced power dissipat;on.
The saturation range of operation is besk`lllustrated in F ~ Sc.
As illustrated in FIG. 5a, the dielectric of a gate region (e.g. 20) ln the silicon dioxide layer 21 is subjected to the ~reatest electrical field at the edge of that gate region. How-ever~ the likelihood of voltage breakdown of the gate dielectric 21 is minimized, in accordance with the present invention, by virtue of the dual layer gate dieleckric comprising the silicon nitride passivation layer 22 deposited over the thermal s;l;con dioxide layer 21. This dual layer dielectric (or sandwich) substantially decreases the probability that pin holes or other po;nt defects will cause localized regions of low d;electric stress. This can be explained by tl,~ relatively low probability of a nitride defect aligning vertlcally with an oxide defect. Moreover, the dielectric thickness is (Jrcatest at the edges of the gate reyions 18 and 20.
~hat is more, the resistive silicon depletion region 15 absorbs a portion of the total potential drop between the gate region 18 or 20 and the conducting (i.e. non-depleted) region of the silicon region 15.
FIG. 7 simultaneously shows the voltage-current charac-teristics of the conventional SOS linear resistor 4 (previously indicated while referring to FIG. 3) relative to the voltage-current characteristics of the SOS field effect resistor lO of the present inventiGn (previously indicated wh;le referring to FIG. 5b).
It is apparent that by virtue of the presently disclosed bilateral SOS field effect resistor lO, having a region of constant current ISAT for voltages of either polarity in excess of the saturation voltage YSAT, a reliable current limiting resistor is available which can endure overvoltages of an increased magnitude (in the range of approximately 400 volts) before voltage failure VF occurs.
Thus, the SOS field effect resistor 10 of the present invention is far more suitable to protect the gate oxide capacitance of an MOS
type tranststor device against high transient overYoltages than the conventional SOS current limiting linear resistor 4 of the prior art.
FIG. 8 is a detailed illustration of the preferred voltage-current characteristics of the presently disclosed two terminal, bilateral, current limiting silicon on sapphire field effect resistor device.
It will be apparent that while a preferred embodiment of the invention has been shown and descr;bed, various modifications and changes may be made without departing from the true spirit and scope of the invention. FGr example, to obtain increas~d protection from transient input signals, a plurality of the presently disclosed ... . .
- 3~ 7 ~C~
field effect resistors may be interconnected together in electrical series between a bonding pad and the gate electrode of the ~',OS de-vice to be protected. Moreover, in place of an insulating substrate, other suitab1e substrates, such as that formed by conventional junc-tion isolation techniques, may also be utilized to fabricate thepresent two terminal field effect resistor. What is more, the adjacent n n n regions 14, 15, and 16 may be formed from any suitable II-YI or III-Y compound semiconductor material1 and the like, or any combination thereof, such as, for example, gallium arsenids, aluminum arsenide, and cadmium telluride.
Having thus set forth a preferred embodiment of the instant invention, what is claimed is:
..... ,~.,_,. .. .
Claims (10)
- The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows.
l. A field effect resistor comprising:
a semiconductor layer composed of monocrystalline semiconductor material of a first conductivity type for providing an electrical resistance having a substantially linear resistive operating characteristic for voltages below the saturation voltage thereof and a constant current operating characteristic for voltages above the saturation voltage thereof;
conductor means comprising first and second spaced terminals making electrical contact with said semiconductor layer and functioning to apply a potential of predetermined magnitude and polarity thereto, and first and second spaced control electrodes making electrical contact with said first and said second terminals respectively;
a dielectric region overlying and making contact with the surface of a portion of said semiconductor layer lying between said first and second spaced terminals, said first and second control electrodes extending over at least a portion of said dielectric region and functioning to create a depletion region in said semiconductor layer beneath at least a portion of one of said control electrodes. - 2. A resistor as defined in Claim 1 further comprising a substrate of insulating material, and wherein said semi-conductor layer overlies said substrate and makes contact with the major surface thereof.
- 3. A resistor as defined in Claim 2, wherein said semiconductor layer comprises adjacently disposed n+n-n+
regions. - 4. A resistor as defined in Claim 3, wherein said dielectric region overlies the n- region of said semiconductor layer, and said first and second terminals make respective contact with the n+ regions of said semiconductor layer.
- 5. A resistor as defined in Claim 1, wherein said semiconductor layer includes adjacently disposed p+p-p+
regions. - 6. A resistor as defined in Claim 1, wherein said dielectric region comprises a layer formed from thermal silicon dioxide.
- 7. A resistor as defined in Claim 1, further comprising a passivation layer formed from silicon nitride overlying said dielectric region.
- 8. A resistor as defined in Claim 2, wherein said conductor means comprises an electrically conductive layer including first and second metallization regions, said first metallization region forming a first terminal and said first control electrode, and said second metallization region forming said second control electrode.
- 9. A resistor as defined in Claim 8, further comprising a layer formed of insulating material overlying the surface of said electrically conductive layer.
- 10. A resistor as defined in Claim 9, wherein said layer of insulating material is formed from silox glassivation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000384758A CA1135873A (en) | 1977-12-06 | 1981-08-27 | Two terminal field effect resistor |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US85804977A | 1977-12-06 | 1977-12-06 | |
| US858,049 | 1977-12-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1132720A true CA1132720A (en) | 1982-09-28 |
Family
ID=25327353
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000316704A Expired CA1132720A (en) | 1977-12-06 | 1978-11-22 | Two terminal field effect resistor |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS5483782A (en) |
| CA (1) | CA1132720A (en) |
| DE (1) | DE2852776A1 (en) |
| FR (1) | FR2411492A1 (en) |
| GB (1) | GB2009502B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5842269A (en) * | 1981-09-05 | 1983-03-11 | Nippon Telegr & Teleph Corp <Ntt> | Mis-type variable resistor |
| GB2234392B (en) * | 1985-05-15 | 1991-05-01 | Hughes Aircraft Co | Monolithic high-frequency-signal switch and power limiter device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA1040321A (en) * | 1974-07-23 | 1978-10-10 | Alfred C. Ipri | Polycrystalline silicon resistive device for integrated circuits and method for making same |
| US4035757A (en) * | 1975-11-24 | 1977-07-12 | Rca Corporation | Semiconductor device resistors having selected temperature coefficients |
-
1978
- 1978-11-20 GB GB7845243A patent/GB2009502B/en not_active Expired
- 1978-11-22 CA CA000316704A patent/CA1132720A/en not_active Expired
- 1978-11-27 JP JP14643678A patent/JPS5483782A/en active Pending
- 1978-12-05 FR FR7834217A patent/FR2411492A1/en active Granted
- 1978-12-06 DE DE19782852776 patent/DE2852776A1/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| DE2852776A1 (en) | 1979-06-13 |
| FR2411492A1 (en) | 1979-07-06 |
| FR2411492B1 (en) | 1983-06-24 |
| JPS5483782A (en) | 1979-07-04 |
| GB2009502B (en) | 1982-03-10 |
| GB2009502A (en) | 1979-06-13 |
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