CA1102012A - Semiconductor device, in particular integrated monolithic circuit, and method of manufacturing same - Google Patents
Semiconductor device, in particular integrated monolithic circuit, and method of manufacturing sameInfo
- Publication number
- CA1102012A CA1102012A CA117,581A CA117581A CA1102012A CA 1102012 A CA1102012 A CA 1102012A CA 117581 A CA117581 A CA 117581A CA 1102012 A CA1102012 A CA 1102012A
- Authority
- CA
- Canada
- Prior art keywords
- layer
- epitaxial
- semiconductor
- substrate
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 152
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000000758 substrate Substances 0.000 claims abstract description 105
- 238000009413 insulation Methods 0.000 claims abstract description 73
- 238000002955 isolation Methods 0.000 claims abstract description 59
- 239000011810 insulating material Substances 0.000 claims abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 65
- 229910052710 silicon Inorganic materials 0.000 claims description 64
- 239000010703 silicon Substances 0.000 claims description 64
- 239000000463 material Substances 0.000 claims description 50
- 238000000034 method Methods 0.000 claims description 39
- 238000009792 diffusion process Methods 0.000 claims description 13
- 230000000873 masking effect Effects 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 230000001590 oxidative effect Effects 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 230000002068 genetic effect Effects 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 3
- 229910052729 chemical element Inorganic materials 0.000 claims description 2
- 239000010410 layer Substances 0.000 claims 92
- 230000004888 barrier function Effects 0.000 claims 4
- 239000011241 protective layer Substances 0.000 claims 3
- 230000002730 additional effect Effects 0.000 claims 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 239000004020 conductor Substances 0.000 description 16
- 230000015572 biosynthetic process Effects 0.000 description 7
- 239000000543 intermediate Substances 0.000 description 7
- 150000004767 nitrides Chemical class 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 3
- 229910052733 gallium Inorganic materials 0.000 description 3
- 230000001976 improved effect Effects 0.000 description 3
- 238000005304 joining Methods 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 239000007858 starting material Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000014509 gene expression Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- SVTBMSDMJJWYQN-UHFFFAOYSA-N 2-methylpentane-2,4-diol Chemical compound CC(O)CC(C)(C)O SVTBMSDMJJWYQN-UHFFFAOYSA-N 0.000 description 1
- 241001181951 Glacies Species 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 101150072242 ccmO gene Proteins 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 235000014786 phosphorus Nutrition 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 230000000391 smoking effect Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000002311 subsequent effect Effects 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0635—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors and diodes, or resistors, or capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
- H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
- H01L27/0652—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
- H01L27/0658—Vertical bipolar transistor in combination with resistors or capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Element Separation (AREA)
- Bipolar Transistors (AREA)
Abstract
Abstract:
Semiconductor device, i.e. integrated circuit, having a monocrystalline semiconductor substrate body and a semiconductor layer provided thereon divided into islands separated by isolation zones comprising an insulation layer of insulating material sunken in the semiconductor. A connection zone locally passed underneath the sunker insulation layer interconnects two adjoining zones associated with two islands comprising circuit elements.
Semiconductor device, i.e. integrated circuit, having a monocrystalline semiconductor substrate body and a semiconductor layer provided thereon divided into islands separated by isolation zones comprising an insulation layer of insulating material sunken in the semiconductor. A connection zone locally passed underneath the sunker insulation layer interconnects two adjoining zones associated with two islands comprising circuit elements.
Description
PHN. 5678 Bks/WG
"Semiconductor device, in par-ticular integrated mono-lithic circuit, and method of manufacturing sameO"
_ The invention relates to a semiconductor device, in particular a monolithic integrated circuit, having a monocrystalline semiconductor substrate body and a semiconductor layer provided on one side thereof and divided into islands which are separated from each ; other by an isolation zone, at least one circuit element being formed in such an island, said island being isolated from the substrate body by at least one ~-n junction~ The invention further more relates to a method of manufacturing such a semiconductor device.
A ~-n junction of the above-mentioned type need not necessarily coincide with the original surface of the substrate body but may also be present in the semiconductor layer or in the substrate body, for example, by diffusion of impurities or by doping dif-ferently, for example, by ion implantation~
The doping to obtain such a ~-n junction may even be carried out prior to the provision of the semicon-ductor layer, so-called buried layers being formed.
In expressions of the type "isolation relative to the q~
1102Q12 PHN. 5678 substrate body" or "conductivity type of the substrate body", for substrate body, the material having the original conductivity is to be considered, for example, as it has remained below buried layers and/or redoped zones formed possibly at the substrate surfaceO
According to a known embodiment of the above-mentioned semiconductor device, the semiconductor layer is provided epitaxially on a substrate body of the op-posite conductivity type. The isolation zone is generally Se~oa l~a ~ e.
~J 10 obtained by s~paration diffusion to form isolation zones having a conductivity type opposite to the conductivity type of the epitaxial layer, said isolation zone ad-joining the substrate body.
Another known example is constituted by the struc-tures described by Murphy et al in "Proceedings IoE~E~E~
September, 1969, ppc 1523-15280 The substrate body and the semiconductor layer provided epitaxially thereon are of the same conductivity type. At its lower boundary the island has a buried layer of the opposite conduc-tivity type and a laterally surrounding zone of the opposite conductivity type which adjoins the buried layer~ The isolation zone consists of the epitaxial material of the original conductivity type and adjoins the substrate body.
These known structures suffer from drawbacksO For example, an isolation by means of a ~-n junction biased il~2~12 PHN. 5678 in the reverse direction has a certain leakage current, a certain breakdown -voltage and a noticeable capacity~
Furthermore the possibîlity exists of the occurrence of a stray transis-tor effect and leakage paths along the surface of the semiconductor layer to the isolation zone or between regions of juxtaposed islands by in-version at said surfaceO The low breakdown voltages and high capacitance leakage near the junction to an isolation zone were generally avoided by avoiding sharp ~-n junctions between highly doped zones. This was done, for example, by choosing at least one zone to be comparatively high-ohmic~ for example, a zone of the comparatively high~ohmic epitaxially deposited ma-terial of the provided semiconductor layer. In order to avoid short-circuit connections by inversion, channel stopping diffusion zones were often used which had to be present at some distance from the ~-n junc-tion between isolation zone and island, for which extra space was requiredO
~hen several semiconductor zones for a semicon-ductor circuit element are provided in such an island, said zones should in many cases be connected electrically9 either to connection conductors or to zones of other islands. For that purpose9 deeper situated zones also Z5 had to be conducted locally to the surface, in which generally a highly doped contact zone was also used, for which the required space should be reserved.
PHN. 5678 11~2~12 According to a known method, said connections were produced via metal tracks which generally were vapour-deposited and provided on an insulating coating present on the semiconductor surface, which coating was provided with windows where the contact with the zones was effected. A pattern of conductors was preferably designed so that it was not necessary for the various metal tracks to cross each other, if possible. For this purpose, a metal track had often to be conveyed from one contact place to another via a considerable roundabout way. This again resulted in an increase of stray capa-citances.
One of the objects of the present invention is to providea more compact structure and/or an improved isolation. The invention uses an improved isolation by using a local insulation layer of insulating material sunken (here also named inset) in the semiconductor layer. .
It is based on the recognition of the fact that when such a sunken insulation layer of insulating material is used in the isolation zone, in which for a good isolation one is less dependent upon the use p-n junctions, one has a larger freedom in the location and shape of the zones applied in one island. It furthermore provides an extra possibility for the mutual connection of zones in various juxtaposed islands. According to the invention, a semiconductor device, in par-ticular a monolithic integrated circuit, having a monocrystalline C semiconductor substrate body and a semiconductor~
11~)2~i2 PHN. 5678 l.ayer provided on one side thereof, divided into islands which are separated from each other by an isolation zone, at least one circui.t element being formed in such an island, said island being isolated from the substrate body by at least one ~-n junction, is characterized in that at least the part of the isolation zone ad-joining the surface of the semiconductor layer is formed B by an insulation layer of insulating material sunke~
in the semiconductox .l.ayer and that a semiconductor zone associated with the said island is connected in an electrically conducti~e manner to a zone associated with an adjacent island by means of a connection zone whi.ch is passed underneath the sunke~ i.nsulation layer, is isolated from the substrate body and ad~oins the zones associated with the two islands, which zones are connected by the connection zoneO
In particular when deep-situated zones of two semi- ~ -; conductor circuit elements are to be connected together electrically, for exampleg -the collectors of two transis-tors of the same typep the invention provides the possi-bility of a compact structure without the danger of strong stray side effectsO In the known formation of islands with isolation zones obtained exclusively by diffusion, the collectors, when the transistors were Z5 arranged in various isl.ands, could be connected via a metal track passed i.n an insulated manner over the isolation zone, in which it had to be ensured that PHNo 5678 there is sufficient place for highly doped contacting zones which had -to be remote far enough from the junction with the diffused isolation zones. Another possibility was the formation of both transistors in a common island in which the -two base zones, each with emitter zones diffused therein, were provided in a common collector zoneO Unfavourable stray transistor effects, thyristor effects, inversion shortcircuit and .
other undesirable effects could occur~ With the measure ~ : :
according to the invention, both collector zones can be ~ -interconnected by a connection zone which adjoins the two zones, passes through the isolation zone, and ex-tends underneath the inset insulation layer which sepa-rates the two islands for the two transistors from each otherO
The inset insulation layer may be inset only over a part of the thickness of the semiconductor layer, in which the isolation zone for the island separation below the inset insulation layer may be formed differently, The two zones of the juxtaposed islands may be connected, for example, by a connection zone of the material of the provided semiconductor layer, as has been deposited ~ epitaxially on the s0mlconductor substrat~ bodyO This : connection zone passes through the isolation zone between the two islandsO The connection zone preferably is a buried layerO It may adjoin a buried layer below one of the islands or both islands, which latter buried 1~2~2 PHNo 5678 layer or layers from the zone or zones to be connected or form part thereof`0 The assembl-y of the connected buried layers may be formed in one step as one buried layer. The said buried layer or buried l.ayers should be insulated from the semiconductor substrate body and will therefore preferably be of a conductivity type opposite to that of the substrate. Since such a buried layer usual.ly extends al.so in the original semiconductor substrate body, the inset insulation layer may be inset also at least throughout the thickness of the provided semlconductor layerO
; When the substrate body and the semiconductor zones . mutually are of opposite conductivity types, the locally provided connection zone preferably is of a conductivity type equal to that of the epitaxial layer~ Since in that case a connection between zones of two juxtaposed islands is not desirable, a buried layer is preferably applied along the lower side of the inset insulation layer, said buried layer then being of the same conductivity type as the substrateO Also in the case in which the inset insula-tion layer is inset to the surface of, or to just in the semiconductor substrate body9 such a buried layer of the same conductivity type as the substrate body may be used as a channel. interrupting zoneO However~ at the area where the connection zone is to be produced 3 the sai.d buried layer of the conductivity type of the sub-strate body is preferably interrupted.
~1102~12 PHN. 5678.
In the case in which the substrate body and the semicon-ductor layer provided thereon are of the same conductivity type, the separation between island and substrate body is obtained in known manner by using a buried layer along the lower side of such an island, said buried layer being of a conductivity type opposite to that of the substrate body and of the epitaxial layer. This buried layer may then adjoin the isolation zone, in particular the isolation zone inset in the semiconductor layer. The buried layers of various islands may be insulated from each other by a sufficient intermediate space at the area of the isolation zone. If desirable, however, said buried layers, according to a preferred embodiment, may be connected underneath the inset insulation layer by means of a buried connection zone. This connection zone may form one assem-bly with the buried layers.
It is to be noted that in applicants Canadian Patent Application 117,579 filed July 7, 1971 (PHN. 4899) of the same priority date a semiconductor device has been proposed having a semiconductor substrate body and a semiconductor layer provided thereon, both of a first conductivity type, having therein an island-shaped region of the first conductivity type adjoining the surface of the layer, which region comprises at least one semicon-ductor circuit element and is fully bounded on its lower side by a - buried layer of a second conductivity type opposite to the first conductivity type extending below the island. The lateral insula-tion is i~2C~2 PHN~ 5678 formed by an electri.cal.ly insulating oxide pattern inset in the semiconductor l.ayer and surrounding the i.sland, and a ~one of the second conductivity type adjoi.ning the semiconductor surface and the inset oxide and which separates the inset oxide from the island and adjoins the buried layer~ Such a ~one of the second conductivity type adjoining the surface and the inset oxide may also be present in an adjacent islandO According to an embo-diment of the present i.nvention9 the buried layer of the second conducti.vity type with the adjoining zone adjoining the surface and the inset insulation l.ayer associated with the said island with the semiconductor circuit element may be connected9 via a connection of the second conductivity type below the inset insula-tion layer, with such a ~one emerging at the surface and the adjoinî.ng buri.ed :I.ayer9 both of -the second ~ conductivity type9 p-resent in an adjacent islandO
In the present application, the expression "i.nset insulation layer" is to be understood to mean an i.nsula-tion layer which9 as regards its depth in the semi-d;S~jng~/;~hcd i B conductor, is clearl.y Q:~tin~uishcd from differences in height at the surface as a resul.t of u.sual. planar methods with diffusions and oxide maskings 9 in which differences in height at the surface may occur of only a few tenths o:f a micronO The inset insulation layer preferably is a genetic insulation layer manufactured by the conversion of t:he semiconductor materialO When ~ 1 (3--11~2~12 PEINo 5678 silicon is used dS a iemiconductor material~ the insula-tion layer is preferably obt,ained by oxid.ationO
For the formation of an inset ins-ulation layer of genetic insulati.ng material formed hy c.onversion of the semiconductor material 9 surface parts of the semi.conduc-tor may be locall.y sc:reened by using a suitable mask, The thickness of the insul.ation layer is c,orrelated with the thickness of the semi.conductor material. whi.ch has been converted, The rati.o between said thicknesses is determined by the volume occupi.ed by the reaction product relative to the volume of the converted semi-conductorO In the case of conversion of silicon into C silicon dioxide, this rat;io is approximately ~
In connection wit:h its function as a part of the isolation zone 9 the lnset insulation l.ayer s:hould-be ~ given a reasonable inset depth in the semi.conductorO
,' This is desirable not; onl.y to obtain impro-ved iso:lation . zones between the isl.ands, but the insulation layer may also create a sufficient d.istance between the underlying semiconductor mater.i.al and conductors possibl.y passed over the insulation layer so that the capacitive coup-ling between them wi.l.l be smallO The i.nset i.nsuiati.on layer preferabl.y extends in the semiconduct,or ove:r a / L/~77 depth of more than 005 ~0 According to a further preferred embodi.ment~ the semiconductor devic:e on the side of the epitaxial. layer has a substanti.ally flat surface, A substantially flat surface is to be understood to mean herein a flatness which is of the same order as is obtained with conventi~
onally used planar met,hods~ Oxi.de layers of at most ~2~12 PHNo 5678 /u~
C 005 ~ are used in conventional.1.y used planar methodsO
If in the convent:ionall.y used planar methods thick, non-inset oxide ski.ns ofg fo:r example, 2 ~ shoul.d be used to decrease the wiring c.apacity by capacitive coupling between condu.c:tive strips on the o:~ide and the underlying semico:nductor materi.al and if wi.ndows ; should be etched in s1lch a thick oxide, for e~ampl.e to provide contacts, the drawback of such a thi.ck oxide is that the etching of sai.d windows is associated with considerabl.e underetchi.ng9 while a difference in hei.ght ~U~?
of 2 ~ should be bridged with the conductive connection between a contact in t.he window and a supply conductor on the oxide~
: By using inset insul.ation9 for exampl.e :inset sl:licon 15 oxide9 obtained by local o~id.at:ion of sil:icon while using ~ a masking on adjacent ssmiconductor parts9 for example ; by means of silicon nitrid.e9 substantiall.y flat junctions can be obtained whiLe nevertheless very thîck insulating material suitable for a low wiring capaci-ty is usedO The original thickness of t.he converted semiconductcr material actually dete:rmines9 as already said9 the thickness of the resul.t..i.ng insul.ation layer0 Tak:ing into account the ultimate hei.ght of the insulation on the semiconductor bsside the inset insulation l.aye:rg the semiconductor surface may previ.ously be giv~n such a profile that after the formati.on of the inset insul.ation layer the surface of sai.d layer comes at appro-~i.mately the same level. as the semi.conductor surface besi.de the inset insulation laye70 Tn the t:heoret::ical ca,e :in which the formation of the insulation layer by- rsaction w:ith ~12~
~02~2 PHNo 5678 the semiconduc-tc>r wou.ld g.ive rise to reduction in volume, some semi.conducior materi.al. beside the inset insulati.on layer to be formed may previously be removed by etching while using a masking. I:n such cases9 however9 as in the formation of` an inse-t insulation layer by masking oxidation of epita.xial. silicon, a conside:rable :i.ncrease in volume takes place by the conversionO In that case semiconductor material may be etched away at the area of the inset insul.ation l.ayer to be provided9 pref`erabl.y by using the masking which i.s also used in the conversion for the formation of the inset insulation layer, so that at the area where the inset i.nsulation layer i.s to be formed the semiconductor surface becomes l.ocated at a :. lower level tha.n the adjacent semiconductor surface, .15 namely to such a depth that after the formati.on of the inset insulation layer the surface of the inset insula-tion layer, due to the i.ncrease in volume9 becomes located at approximately the same level as the adjacent semi-conductor surface on the insulation ultimatel.y appl.ied thereonO Small unevenesses can be formed at most near the junction but they are of such a nature ~;hat th.ey are not annoying for provi~ing metal conductors over the isolation zoneO
In order that the invention may be readi.ly carried into effect, a few embodiment thereof wil.l. now be des-cribed in greater detail.~ by way of exampleg with re~
ference to the accompanying drawings 9 in which . 1~i=~ .
11~2~1Z PHNo 5678 Figures 1 -to 4 are detail.ed diagrammatic cross-sectional views of' successi-ve stages i.n the manufacture of' a semiconductor device having island structure9 Figures 5 to 8 are detailed diagrammatic cross-sectional views of successi-ve stages in the manufacture of a semiconductor devîce having island struct-ure of a different typeO
Figure 9 is a det,ai.l.ed diagrammatic cross-sectional view of again another embodiment of a semiconductor .~ 10 device having island s-tructure.
Starting material. (see Figure 1) is a structure manufactured accordi.ng to methods conventional.ly used in semiconductor technology and consisting of a mono~
crystalline semiconductor substrate body 2 of n~type : 15 silicon having a resistivity of 1 Ohm cm9 whic:h body has a thickness of 200 mi.c:rons~ and an n-type silicon layer ~ 3 deposited epitaxiall.y on the body 29 which layer 3 has : a thickness of 3 microns and a resistivity of 0~1 Ohm cm, .
and ~-type buried layers 5 having a boron doping of 10 atoms/ccmO A layer l9 of silicon nitri.de9 0015 micron thick9 is provided thereon by heating in an atmosphere containing SiH4 and NH3 at: a temperature of approximately 1000 ~0 By heating in an atmosph.ere containing SiH~9 ~2 ~:
and H2 a layer of silicon oxi.de is provi.ded on said layer 190 For al.l the detail.s of the methods to be used for the provision of the silicon nitride and sil.:icon oxide layers mentioned in this example 9 as well as for the 11~2g~12 PHNo 5678 masking and etching of said Layers, reference is made - to Phil.ips Research Reports, April, 1970, ~0 118-132,in which paper all the information necessary to those skilled i.n the art is gi.venO
While using ph.otoresist methods conventi.onally used in semiconductor technology, an annular opening is etched in said dou.bl.e layer of silicon ni.tri.d.e and silicon oxide9 after whi.ch the said oxide layer is removed in a HF hu.ffer sol.uti.on9 grooves 20, dept.h 0.8 micron (see Figure 1)9 being then etched i.n the : layer 3 by etching at 2C with a liquid co~sisting of170 ccm~
of 60% HN03, 280 ccm of smoking HN03, 110 ccm of 40~
: HF and 440 ccm of glaci.al acetic acidO In general the grooves are provided. above those part.s of the ju.ncti.on between the substrate hody 2 and the semico:nductor 3 where an intermedia$e space is present between. the buried layers 59 but locally a groove 20 is present above such a buried. layer 50 By oxidation in water vapour which i.s .saturated at 95 C, the silicon surface i.n the grooves 20 ~see Figure 2) is then oxidized at 1000C during which the nitride layer 19 is al.so covered with a thin oxide layer 21 until an oxide pattern 8 is formed i:n the grooves 20, the upper surface of said pattern substant-ially coinciding with the interface between the layers 3 and 1~o A layer 22 of si.licon nitride (see Figure 3) i.s ~1~2~i~
PHNo 5678 then provided throughout t:h.e surface by means of the already mentioned methods9 and this layer is coated with a layer 23 o:f sil.icon oxide, By using a photo-resist method, the oxide layer 23 is locall.y etc,hed away after which apertures 24 are etched in the nitride layer 22 ~hil.e using the remaining parts of the layer 23 as a mask (see Figure 4)0 The fi.rst nitride layer 19 is maintained since it is covered with the oxide layer 2l which is substantially not attacked by the etchant (usually phosphoric acid) with which the nitride is etched away.
: Gallium is then indiffusedO This is carried out at 1050C in argon us:ing gall.ium-doped sil.icon powder as a source, for 15 minutesO The gallium diffuses through the oxi.de but i.s masked by the ~silic,on ni.~
trideO As a resul.t o,~ thls a.n approximately 007 micron thick ~-type zone 9 i.s obtained (see Figure 7) which adjoins the buried ~type layer 5 of which in this example the distance to the surface is approxi.mately
"Semiconductor device, in par-ticular integrated mono-lithic circuit, and method of manufacturing sameO"
_ The invention relates to a semiconductor device, in particular a monolithic integrated circuit, having a monocrystalline semiconductor substrate body and a semiconductor layer provided on one side thereof and divided into islands which are separated from each ; other by an isolation zone, at least one circuit element being formed in such an island, said island being isolated from the substrate body by at least one ~-n junction~ The invention further more relates to a method of manufacturing such a semiconductor device.
A ~-n junction of the above-mentioned type need not necessarily coincide with the original surface of the substrate body but may also be present in the semiconductor layer or in the substrate body, for example, by diffusion of impurities or by doping dif-ferently, for example, by ion implantation~
The doping to obtain such a ~-n junction may even be carried out prior to the provision of the semicon-ductor layer, so-called buried layers being formed.
In expressions of the type "isolation relative to the q~
1102Q12 PHN. 5678 substrate body" or "conductivity type of the substrate body", for substrate body, the material having the original conductivity is to be considered, for example, as it has remained below buried layers and/or redoped zones formed possibly at the substrate surfaceO
According to a known embodiment of the above-mentioned semiconductor device, the semiconductor layer is provided epitaxially on a substrate body of the op-posite conductivity type. The isolation zone is generally Se~oa l~a ~ e.
~J 10 obtained by s~paration diffusion to form isolation zones having a conductivity type opposite to the conductivity type of the epitaxial layer, said isolation zone ad-joining the substrate body.
Another known example is constituted by the struc-tures described by Murphy et al in "Proceedings IoE~E~E~
September, 1969, ppc 1523-15280 The substrate body and the semiconductor layer provided epitaxially thereon are of the same conductivity type. At its lower boundary the island has a buried layer of the opposite conduc-tivity type and a laterally surrounding zone of the opposite conductivity type which adjoins the buried layer~ The isolation zone consists of the epitaxial material of the original conductivity type and adjoins the substrate body.
These known structures suffer from drawbacksO For example, an isolation by means of a ~-n junction biased il~2~12 PHN. 5678 in the reverse direction has a certain leakage current, a certain breakdown -voltage and a noticeable capacity~
Furthermore the possibîlity exists of the occurrence of a stray transis-tor effect and leakage paths along the surface of the semiconductor layer to the isolation zone or between regions of juxtaposed islands by in-version at said surfaceO The low breakdown voltages and high capacitance leakage near the junction to an isolation zone were generally avoided by avoiding sharp ~-n junctions between highly doped zones. This was done, for example, by choosing at least one zone to be comparatively high-ohmic~ for example, a zone of the comparatively high~ohmic epitaxially deposited ma-terial of the provided semiconductor layer. In order to avoid short-circuit connections by inversion, channel stopping diffusion zones were often used which had to be present at some distance from the ~-n junc-tion between isolation zone and island, for which extra space was requiredO
~hen several semiconductor zones for a semicon-ductor circuit element are provided in such an island, said zones should in many cases be connected electrically9 either to connection conductors or to zones of other islands. For that purpose9 deeper situated zones also Z5 had to be conducted locally to the surface, in which generally a highly doped contact zone was also used, for which the required space should be reserved.
PHN. 5678 11~2~12 According to a known method, said connections were produced via metal tracks which generally were vapour-deposited and provided on an insulating coating present on the semiconductor surface, which coating was provided with windows where the contact with the zones was effected. A pattern of conductors was preferably designed so that it was not necessary for the various metal tracks to cross each other, if possible. For this purpose, a metal track had often to be conveyed from one contact place to another via a considerable roundabout way. This again resulted in an increase of stray capa-citances.
One of the objects of the present invention is to providea more compact structure and/or an improved isolation. The invention uses an improved isolation by using a local insulation layer of insulating material sunken (here also named inset) in the semiconductor layer. .
It is based on the recognition of the fact that when such a sunken insulation layer of insulating material is used in the isolation zone, in which for a good isolation one is less dependent upon the use p-n junctions, one has a larger freedom in the location and shape of the zones applied in one island. It furthermore provides an extra possibility for the mutual connection of zones in various juxtaposed islands. According to the invention, a semiconductor device, in par-ticular a monolithic integrated circuit, having a monocrystalline C semiconductor substrate body and a semiconductor~
11~)2~i2 PHN. 5678 l.ayer provided on one side thereof, divided into islands which are separated from each other by an isolation zone, at least one circui.t element being formed in such an island, said island being isolated from the substrate body by at least one ~-n junction, is characterized in that at least the part of the isolation zone ad-joining the surface of the semiconductor layer is formed B by an insulation layer of insulating material sunke~
in the semiconductox .l.ayer and that a semiconductor zone associated with the said island is connected in an electrically conducti~e manner to a zone associated with an adjacent island by means of a connection zone whi.ch is passed underneath the sunke~ i.nsulation layer, is isolated from the substrate body and ad~oins the zones associated with the two islands, which zones are connected by the connection zoneO
In particular when deep-situated zones of two semi- ~ -; conductor circuit elements are to be connected together electrically, for exampleg -the collectors of two transis-tors of the same typep the invention provides the possi-bility of a compact structure without the danger of strong stray side effectsO In the known formation of islands with isolation zones obtained exclusively by diffusion, the collectors, when the transistors were Z5 arranged in various isl.ands, could be connected via a metal track passed i.n an insulated manner over the isolation zone, in which it had to be ensured that PHNo 5678 there is sufficient place for highly doped contacting zones which had -to be remote far enough from the junction with the diffused isolation zones. Another possibility was the formation of both transistors in a common island in which the -two base zones, each with emitter zones diffused therein, were provided in a common collector zoneO Unfavourable stray transistor effects, thyristor effects, inversion shortcircuit and .
other undesirable effects could occur~ With the measure ~ : :
according to the invention, both collector zones can be ~ -interconnected by a connection zone which adjoins the two zones, passes through the isolation zone, and ex-tends underneath the inset insulation layer which sepa-rates the two islands for the two transistors from each otherO
The inset insulation layer may be inset only over a part of the thickness of the semiconductor layer, in which the isolation zone for the island separation below the inset insulation layer may be formed differently, The two zones of the juxtaposed islands may be connected, for example, by a connection zone of the material of the provided semiconductor layer, as has been deposited ~ epitaxially on the s0mlconductor substrat~ bodyO This : connection zone passes through the isolation zone between the two islandsO The connection zone preferably is a buried layerO It may adjoin a buried layer below one of the islands or both islands, which latter buried 1~2~2 PHNo 5678 layer or layers from the zone or zones to be connected or form part thereof`0 The assembl-y of the connected buried layers may be formed in one step as one buried layer. The said buried layer or buried l.ayers should be insulated from the semiconductor substrate body and will therefore preferably be of a conductivity type opposite to that of the substrate. Since such a buried layer usual.ly extends al.so in the original semiconductor substrate body, the inset insulation layer may be inset also at least throughout the thickness of the provided semlconductor layerO
; When the substrate body and the semiconductor zones . mutually are of opposite conductivity types, the locally provided connection zone preferably is of a conductivity type equal to that of the epitaxial layer~ Since in that case a connection between zones of two juxtaposed islands is not desirable, a buried layer is preferably applied along the lower side of the inset insulation layer, said buried layer then being of the same conductivity type as the substrateO Also in the case in which the inset insula-tion layer is inset to the surface of, or to just in the semiconductor substrate body9 such a buried layer of the same conductivity type as the substrate body may be used as a channel. interrupting zoneO However~ at the area where the connection zone is to be produced 3 the sai.d buried layer of the conductivity type of the sub-strate body is preferably interrupted.
~1102~12 PHN. 5678.
In the case in which the substrate body and the semicon-ductor layer provided thereon are of the same conductivity type, the separation between island and substrate body is obtained in known manner by using a buried layer along the lower side of such an island, said buried layer being of a conductivity type opposite to that of the substrate body and of the epitaxial layer. This buried layer may then adjoin the isolation zone, in particular the isolation zone inset in the semiconductor layer. The buried layers of various islands may be insulated from each other by a sufficient intermediate space at the area of the isolation zone. If desirable, however, said buried layers, according to a preferred embodiment, may be connected underneath the inset insulation layer by means of a buried connection zone. This connection zone may form one assem-bly with the buried layers.
It is to be noted that in applicants Canadian Patent Application 117,579 filed July 7, 1971 (PHN. 4899) of the same priority date a semiconductor device has been proposed having a semiconductor substrate body and a semiconductor layer provided thereon, both of a first conductivity type, having therein an island-shaped region of the first conductivity type adjoining the surface of the layer, which region comprises at least one semicon-ductor circuit element and is fully bounded on its lower side by a - buried layer of a second conductivity type opposite to the first conductivity type extending below the island. The lateral insula-tion is i~2C~2 PHN~ 5678 formed by an electri.cal.ly insulating oxide pattern inset in the semiconductor l.ayer and surrounding the i.sland, and a ~one of the second conductivity type adjoi.ning the semiconductor surface and the inset oxide and which separates the inset oxide from the island and adjoins the buried layer~ Such a ~one of the second conductivity type adjoining the surface and the inset oxide may also be present in an adjacent islandO According to an embo-diment of the present i.nvention9 the buried layer of the second conducti.vity type with the adjoining zone adjoining the surface and the inset insulation l.ayer associated with the said island with the semiconductor circuit element may be connected9 via a connection of the second conductivity type below the inset insula-tion layer, with such a ~one emerging at the surface and the adjoinî.ng buri.ed :I.ayer9 both of -the second ~ conductivity type9 p-resent in an adjacent islandO
In the present application, the expression "i.nset insulation layer" is to be understood to mean an i.nsula-tion layer which9 as regards its depth in the semi-d;S~jng~/;~hcd i B conductor, is clearl.y Q:~tin~uishcd from differences in height at the surface as a resul.t of u.sual. planar methods with diffusions and oxide maskings 9 in which differences in height at the surface may occur of only a few tenths o:f a micronO The inset insulation layer preferably is a genetic insulation layer manufactured by the conversion of t:he semiconductor materialO When ~ 1 (3--11~2~12 PEINo 5678 silicon is used dS a iemiconductor material~ the insula-tion layer is preferably obt,ained by oxid.ationO
For the formation of an inset ins-ulation layer of genetic insulati.ng material formed hy c.onversion of the semiconductor material 9 surface parts of the semi.conduc-tor may be locall.y sc:reened by using a suitable mask, The thickness of the insul.ation layer is c,orrelated with the thickness of the semi.conductor material. whi.ch has been converted, The rati.o between said thicknesses is determined by the volume occupi.ed by the reaction product relative to the volume of the converted semi-conductorO In the case of conversion of silicon into C silicon dioxide, this rat;io is approximately ~
In connection wit:h its function as a part of the isolation zone 9 the lnset insulation l.ayer s:hould-be ~ given a reasonable inset depth in the semi.conductorO
,' This is desirable not; onl.y to obtain impro-ved iso:lation . zones between the isl.ands, but the insulation layer may also create a sufficient d.istance between the underlying semiconductor mater.i.al and conductors possibl.y passed over the insulation layer so that the capacitive coup-ling between them wi.l.l be smallO The i.nset i.nsuiati.on layer preferabl.y extends in the semiconduct,or ove:r a / L/~77 depth of more than 005 ~0 According to a further preferred embodi.ment~ the semiconductor devic:e on the side of the epitaxial. layer has a substanti.ally flat surface, A substantially flat surface is to be understood to mean herein a flatness which is of the same order as is obtained with conventi~
onally used planar met,hods~ Oxi.de layers of at most ~2~12 PHNo 5678 /u~
C 005 ~ are used in conventional.1.y used planar methodsO
If in the convent:ionall.y used planar methods thick, non-inset oxide ski.ns ofg fo:r example, 2 ~ shoul.d be used to decrease the wiring c.apacity by capacitive coupling between condu.c:tive strips on the o:~ide and the underlying semico:nductor materi.al and if wi.ndows ; should be etched in s1lch a thick oxide, for e~ampl.e to provide contacts, the drawback of such a thi.ck oxide is that the etching of sai.d windows is associated with considerabl.e underetchi.ng9 while a difference in hei.ght ~U~?
of 2 ~ should be bridged with the conductive connection between a contact in t.he window and a supply conductor on the oxide~
: By using inset insul.ation9 for exampl.e :inset sl:licon 15 oxide9 obtained by local o~id.at:ion of sil:icon while using ~ a masking on adjacent ssmiconductor parts9 for example ; by means of silicon nitrid.e9 substantiall.y flat junctions can be obtained whiLe nevertheless very thîck insulating material suitable for a low wiring capaci-ty is usedO The original thickness of t.he converted semiconductcr material actually dete:rmines9 as already said9 the thickness of the resul.t..i.ng insul.ation layer0 Tak:ing into account the ultimate hei.ght of the insulation on the semiconductor bsside the inset insulation l.aye:rg the semiconductor surface may previ.ously be giv~n such a profile that after the formati.on of the inset insul.ation layer the surface of sai.d layer comes at appro-~i.mately the same level. as the semi.conductor surface besi.de the inset insulation laye70 Tn the t:heoret::ical ca,e :in which the formation of the insulation layer by- rsaction w:ith ~12~
~02~2 PHNo 5678 the semiconduc-tc>r wou.ld g.ive rise to reduction in volume, some semi.conducior materi.al. beside the inset insulati.on layer to be formed may previously be removed by etching while using a masking. I:n such cases9 however9 as in the formation of` an inse-t insulation layer by masking oxidation of epita.xial. silicon, a conside:rable :i.ncrease in volume takes place by the conversionO In that case semiconductor material may be etched away at the area of the inset insul.ation l.ayer to be provided9 pref`erabl.y by using the masking which i.s also used in the conversion for the formation of the inset insulation layer, so that at the area where the inset i.nsulation layer i.s to be formed the semiconductor surface becomes l.ocated at a :. lower level tha.n the adjacent semiconductor surface, .15 namely to such a depth that after the formati.on of the inset insulation layer the surface of the inset insula-tion layer, due to the i.ncrease in volume9 becomes located at approximately the same level as the adjacent semi-conductor surface on the insulation ultimatel.y appl.ied thereonO Small unevenesses can be formed at most near the junction but they are of such a nature ~;hat th.ey are not annoying for provi~ing metal conductors over the isolation zoneO
In order that the invention may be readi.ly carried into effect, a few embodiment thereof wil.l. now be des-cribed in greater detail.~ by way of exampleg with re~
ference to the accompanying drawings 9 in which . 1~i=~ .
11~2~1Z PHNo 5678 Figures 1 -to 4 are detail.ed diagrammatic cross-sectional views of' successi-ve stages i.n the manufacture of' a semiconductor device having island structure9 Figures 5 to 8 are detailed diagrammatic cross-sectional views of successi-ve stages in the manufacture of a semiconductor devîce having island struct-ure of a different typeO
Figure 9 is a det,ai.l.ed diagrammatic cross-sectional view of again another embodiment of a semiconductor .~ 10 device having island s-tructure.
Starting material. (see Figure 1) is a structure manufactured accordi.ng to methods conventional.ly used in semiconductor technology and consisting of a mono~
crystalline semiconductor substrate body 2 of n~type : 15 silicon having a resistivity of 1 Ohm cm9 whic:h body has a thickness of 200 mi.c:rons~ and an n-type silicon layer ~ 3 deposited epitaxiall.y on the body 29 which layer 3 has : a thickness of 3 microns and a resistivity of 0~1 Ohm cm, .
and ~-type buried layers 5 having a boron doping of 10 atoms/ccmO A layer l9 of silicon nitri.de9 0015 micron thick9 is provided thereon by heating in an atmosphere containing SiH4 and NH3 at: a temperature of approximately 1000 ~0 By heating in an atmosph.ere containing SiH~9 ~2 ~:
and H2 a layer of silicon oxi.de is provi.ded on said layer 190 For al.l the detail.s of the methods to be used for the provision of the silicon nitride and sil.:icon oxide layers mentioned in this example 9 as well as for the 11~2g~12 PHNo 5678 masking and etching of said Layers, reference is made - to Phil.ips Research Reports, April, 1970, ~0 118-132,in which paper all the information necessary to those skilled i.n the art is gi.venO
While using ph.otoresist methods conventi.onally used in semiconductor technology, an annular opening is etched in said dou.bl.e layer of silicon ni.tri.d.e and silicon oxide9 after whi.ch the said oxide layer is removed in a HF hu.ffer sol.uti.on9 grooves 20, dept.h 0.8 micron (see Figure 1)9 being then etched i.n the : layer 3 by etching at 2C with a liquid co~sisting of170 ccm~
of 60% HN03, 280 ccm of smoking HN03, 110 ccm of 40~
: HF and 440 ccm of glaci.al acetic acidO In general the grooves are provided. above those part.s of the ju.ncti.on between the substrate hody 2 and the semico:nductor 3 where an intermedia$e space is present between. the buried layers 59 but locally a groove 20 is present above such a buried. layer 50 By oxidation in water vapour which i.s .saturated at 95 C, the silicon surface i.n the grooves 20 ~see Figure 2) is then oxidized at 1000C during which the nitride layer 19 is al.so covered with a thin oxide layer 21 until an oxide pattern 8 is formed i:n the grooves 20, the upper surface of said pattern substant-ially coinciding with the interface between the layers 3 and 1~o A layer 22 of si.licon nitride (see Figure 3) i.s ~1~2~i~
PHNo 5678 then provided throughout t:h.e surface by means of the already mentioned methods9 and this layer is coated with a layer 23 o:f sil.icon oxide, By using a photo-resist method, the oxide layer 23 is locall.y etc,hed away after which apertures 24 are etched in the nitride layer 22 ~hil.e using the remaining parts of the layer 23 as a mask (see Figure 4)0 The fi.rst nitride layer 19 is maintained since it is covered with the oxide layer 2l which is substantially not attacked by the etchant (usually phosphoric acid) with which the nitride is etched away.
: Gallium is then indiffusedO This is carried out at 1050C in argon us:ing gall.ium-doped sil.icon powder as a source, for 15 minutesO The gallium diffuses through the oxi.de but i.s masked by the ~silic,on ni.~
trideO As a resul.t o,~ thls a.n approximately 007 micron thick ~-type zone 9 i.s obtained (see Figure 7) which adjoins the buried ~type layer 5 of which in this example the distance to the surface is approxi.mately
2 microns~ The grooves 20 are at l.east so wide that after ~:
the gallium diffusion the zones 9 whlch belong to juxta-posed islands 4 do not touch each otherO ~here an inter-mediate space is present between the buried layers 5, no detrimental stray transi.stor effect is thus formed between the zones with the intermediate part of the layer 3 below the inset insulation l.ayer 89 so that an effective island separation is obtai.nedO
~16~
13~12q~12 PHN. 5678.
Where, however, the buried layer 5 fully extends underneath the oxide 8, parts of said buriecl layer which extend below juxta-posed islands are connected by a part extending locally under-neath the insulation layer 8. By means of zones 9 an assembly of interconnected zones belongins to different islands 4 and extending locally to the surface is obtained.
One or more zones for semiconductor circuit elements to be formed in the islands 4 can be provided in the resulting struc-ture after removing the layers 19, 21, 22 and 23 by means of further oxidation, masking and diffusion. The buried layers may serve for insulation or form part of a semiconductor circuit element in which a through-connection to a zone of an adjacent island can be obtained and moreover connections to the surface can be obtained, for example, for providing a surface contact.
Instead of using a buried layer S extending underneath an oxide layer 8, zones 9 on either side of the oxide layer 8 may locally extend underneath the oxide over such a distance that a continuous zone is obtained.
The method described has been given only by way of example and the device described may also advantageously be manufactured according to various other methods, for example, that which is described in Applicant's Canadian Patent 925,226 issued April 24, 1973 (PHN. 4775). .
The semiconductor circuit elements, for example, ~2~12:
transistors9 dlode~, res:is-to:r33 p-n-~-n elements3 and so on3 can be pro-v:i.~led. ln known manner i.n the i31ands 4 Instead of in an island ll one or more of -these elements may also be present entirel.y or partly in the form of conductive layers3 for examp1e, metal layers3 on the island-shaped region 4 o:r on the oxide layer 130 Furthermore it is not necessary for the region consti-tuted by the buri.ed :Layer 5 and the zones 9 to form part of the said circui.t el.ement although this is -very desirable from a poin.t of view of space sa-vingO
It will be obvious that the invention furthermore is not restricted to the examples described~ For example, the buried. l.ayer 5 can also be provi.ded9 if desirable, by ion implantation or ep:i.taxi.allyO ~n parti-cular, instead of silicon3 other semiconductor materialswhich can form a usefuL ox.ide pattern3 for e:~ample 3 : silicon carbide, may also be used It is also possible to use, exclusively underneath the inset insulation layer9 a buri.ed .layer of a con-ducti-vity type oppos:ite to that of the epitaxi.al layer3 which buried layer has expanded in the epitaxi.al .1ayer from the substrateO At the area of the connection zone between two zones present in adjacent islands said layer may be interruptedO Such a case wil.l hereinafter be described wi.th reference to Figures 5 to 80 Starting material. is a monocrystalline semi.conductor body 61 of p-type silicon in which by means of con-ven-tional planar methods arseni.c~doped l.ow~ohmic n~type il~l2 PHNo 5678 zones 62 an.d. a boron-doped .low-ohmic ~-type zone 63 are ~ormed. The zone 63 tas t~e form of a network which7 however, is inte-rrupted l.ocallyO For the re3t, the zone 63 encloses t:he zones 62 laterally At the area . 5 of the interruption in the zone 63, the zone 62 is .: passed through the interruptionO The parts of said zone 63 have a width9 for example, of 3 ~0 The resulting stage is shown in Figure 50 As is usual in planar dif-fusion methods 9 an o:~ide 7.ayer 64 is present on the surface of the semiconductor body 61~ This o~ide layer is now removed in a conventional manner by means of hydrofluoric acid A high-ohmic n-type epitaxial layer 68 is then : deposited on the si.Licon body 61, for exampl.e3 i.n a /~l>77 . 15 thickness of 4 ~0 During said depositi.on the zones 62 and 63 which become hu:ri.ed. l.ayersg can expand into the epitaxial layer 68 by diffusionO In particular the buried layer 63 can expand more rapidly than the buried layer 62 since boron diffusesmore rapidly than arsenicO
In known manner the surface of the epitaxial.. layer 68 is covered with a thin si~icon nitride layer 65 and then with a silicon oxide 1.ayer 660 In this layer apertures are provided above th.e ~-type buried zone 639 also in the form of a network, but now expanded above the interrupt-ion(s) in the network of the bu.ried zone 630 The width of /~
said apertures is at least 5 ~0 While u.si.ng the nitride oxide masking 659 66, grooves 67 are etched in the sil.icon ~9_ ~1~2~i2 PHNo 5678 C in a depth of` wel..l over l ~ 0 The resultl.ng stage :îs shown in Figure 6~
The oxide layer 66 is now removed by a conventional hydrofluoric acid etcha.nt and the assembly is then subjected to an oxidizing treatment in steam of 1 at-mosphere at 1000C to form an inset insulation layer 70 consisting of si.li.con oxide, the sil.icon nitr:ide masking 65 protecting the underlying silicon outside the grooves 670 The ox:idation treatment is continued (approximately 16 hours) until a depth of approximately 2 ~ is achieved, the formed oxide having also fi.ll.ed the original grooves 67 entirelyO In the meantime the boron-doped ~-type burîed layer 63 has expanded further in the epitaxial layerO In this stage or after a subse-quent thermal treatment :i.t may adjoin the l.ower side of the formed inset insulation l.ayerO The resul.ti.ng stage is shown i.n Figure 70 The epitaxial layer 68 is now divided into islands which are separated from each other by means of isolation zones formed by the i.nset insulation layer 70 and the buried ~-type layer 63~
Locally, however9 such an isolation zone bel.ow the Lnset insulation layer is interrupted for pass.ing through an ; n-type conductive connection consisti.ng of a part of the buried layer 62 and posslbl.y a remainder present above said l.ayer of the origin~l epitaxially deposited n-type material 680 For example, by means of planar diffusi.on methods~
~20-PHNo 5678 circuit elements may t;hen be formed in the islands în : known manner9 as the.n~ transistor shown in Flgure 89 in which the collector is formed by the epitaxial. n-type material 78, the arsenic-doped buried. l.ayer 62, and the ~ollector-contacting zone 77 formed during the emitter diffusion, the base is formed by the ~-type zone 75 formed by diffusion of boron9 and the emitter is formed by the n~type zone 76 formed by dif-fusion of phosphoru.s~ The resulting stage is shown in Figure 8.
By means of the n-type buried layer 62, the col-lector zone belonging to the island 78 is through-connected to an n-type zone associated with an adjacent island via an interrupt.i.on in the p-type buri.ed la-yer 63 which together with the inset insul.ati.on layer 70 forms the isolation zone between the isl.andsO
Since it had. been ensured in the manufacture that the inset insulation layer was wider than the buried ~-type layer 63, the distance between the buried layer ; 20 63 and the base zone 75 i.s maintained large notwith-standing the fact that the base layer 75 adjoins the inset insulation layer 700 Also in the case of the device shown diagrammatic-ally in Figure 8, th.e advantage is obtained that the upper side of the inset lnsulation layer 70 is present approximately at the same level as the adjacent surface of the epitaxial layerO In known manner9 adjoining ~2l~
1~2~ PHN~ 5678 contacts in window-s i.n thin insulation layers used on the island surface may be provided and suppl.y conductors used which preferably extend over the insul.ation layer 70 as much as possi.bl.eO
In the case described in Figure 8 a thick epitaxial layer is used in which it is avoided, however3 for the good formation of isolation zones, to use a proportiona..ly thicker inset insulation layerO If desirabl.e, the thick-ness of the epitaxial. layer 68 may also be chosen to be smaller so that the inset insulation layer 70 reaches at least to the junction between the substrate 61 and the provided semiconductor layer 680 Since the buried layer 62 extends in the original substrate, said layer can also produce locally below the inset insulation layer a con-ductive connection be$ween two zones on either side of the isolation zoneO
It is obvious that in the islands beside the island in which the transistor shown in Figure 8 is provided9 ~ other circuit elements9 for example, other transistors 9 : 20 may also be providedO
In the embodiment shown in Figure 8 in whi.ch an n-type epitaxial layer is used on a ~-type substrate and an insulation layer which is partly inset in said epitaxial layer, use is made of a highly doped bur.ied layer of the p-type provided in t:he substrate, which layer has ex-panded to the lower sid.e of the insulation layer by dif-fusionO It is of course also possible, for exampl.e in ~22-~2~
PHNo 5678 th0 case of an ep:i.taxi.al. l.ayer of the n-type on a substrate of the p-~ype and an insu.l.ation la.yer inset;
over part of the thickness of the epitaxial layer3 to use a zone present on the lower side of th0 isolation zone in the epitaxial :1.ayer of the conductivity type of the substrateO Th.is ~-type zone present bel.ow the inset insulation layer may have expanded, for exampl.e, by diffusion to the p n junction formed between the substrate and t,he epitaxial .layerO It is al.so possi.ble that said ~-type zone ad.joining the inset insulation layer has expanded to the depletion layer formed between the ~-type substrate and the epitaxial layerO
The above examp:le described with reference to Figures 5 to 8 related to a p-type semi.conduc-t;or substrate body and an n-type epitaxi.al semi.conductor l.ayerO.Of course, in a corresponding manner the starting material may be an n-type semiconductor substrate body and a ~
type semiconductor layer in which the various zones and buried layers may also be chosen to be of correspondingly different conductivity type in a corresponding mannerO
In that case as an n~type doping material in silicon9 for example3 phosphorus3 may be u.sed as a doping for the buried layers 63 of Figure 80 Both boron and ph.osphorus have a very high solu.bil.ity in silicon3 -wh.il.e t;heir dif~
fusion properties do not di.ffer muchO
Figure 9 shows possibilities of island isolation according to the invention in the case in which a mono-crystalline substrate body is used of the same cond.ucti-vity type as the epi.taxia]. l.ayer provided thereonO The monocrystalline silicon substrate body 100 consists3 ~3~
1~02~1~
PHNo 5678 for example, of n~t.ype material having a resisti-vity of, for example, 1 o:hm cmO An epitaKial. layer 101 provided thereon consîsts of silicon of the same con-ductivity type and approximatel.y the same resistivity, while on the boundary of` the substrate body and the epitaxial layer a numher of buried layers 1010 102 and 103 of ~-type sllî.con are provided which are separa-ted from each other by a network of narrow zones 111 of the high-ohmic n-type material. of the su.bstrate and the epitaxial layerO The bur:ied layers are doped9 for example 9 with boron and have expanded from the boundary between :~
the substrate and the epitaxial layer :~ From the upper side of the epitaxial layer an inset insulation layer is provided as described above D the upper 15 surface of which i.s app:roximately at the same lev~l. with the upper side of t:h.e adjacent parts of the epitaxlal ; layerO The inset in~u.Lation layer 109 overl.aps inter alia the n-type zones between the buried layers 101~ l02 and 1030 Furthermore, it ls a.l.so provided locall.y according to intermediate strips f:rom above 9 for example, to a central portion of the buri.ed layer 1020 In this manner the epitaæial layer 104 is divided int.o n~type isl.ands 105, 106, 107 and l08 which are separated from the n type substrate 100 by two ~n junctions and are separated from each other by isol.ation zones which partly consist of the buried insulatl.on 1.ayer 1090 For example 9 the islands 105 and 106 are separated from each other by the ~4_ ~1~32~
PHN~ 5678 inset insulati.on layer lO9, the parts faci,ng each other ; of the buried l.ayers 102 and lO3~ and the intermediate high-ohmic n-type zone 1l1, the islands 106 and 107 are separated from each other by the inset insul.at:i.on layer 109 and the buried layer 102 3 and the islands 107 and 108 are separated from each other by the inset insulation layer 109, the end parts facing each other of the buried layers 101 and 102 and the intermediate high-ohmi.c n-type zone 111, Semi.conductor circuit elements can be formed in known manner in the islands which are separatad from each otherO It is possible that such an underlying ,~ buried layer serves for double insul.ation but it is also . possible that such a buried layer which actuall.y is separated from the substrate by a ~-n junction of the n-type material, forms a functional. part of a circuit element to be provîded9 for example, the collector of a ~-n-~ transistor~ Where it is provided below more than one island, it may al.so serve as a through~connection~
for example, as a common~ possibly floating9 el.ectrode of two circuit elements provided in the islands 106 and 107~ Such a buried layer may also form a functional. part of a circuit element and an insulation for another circuit element. Furthermore, in order to obtain islands of' larger depth it is possibl.e to use layers the upper side of which is situated deeper than the lower side of the inset insulation layer~ narrow intermediate zones of the conductivity type of the bu.ried layers producing a con ~2~-11C)~12 PHNo 5678 nection between the inse-t insulation l.ayers and the buried layers in such manner that islands wh:i.rh are separated from each ot:her are formed which, however, can locally have a larger depth than the inset însul.a-tion layer 109.
A structure of islands correspondlng to Figure 9 may also be obtained by using a p-type substrate 100 on which ~-type epita~i.al material 104 is provided and in which n-type buried layers 1013 102 and 103 are used It is to be noted t:hat it is the object of the Figures to denote that a variety of embodiments are possible without departing from the scope of this in-vention. The number of circuit elements shown is furthermore not limitativeO Semi.conductor circuit ele-ments having contacts of the Schottky type may also be used, while field effect transistors can be real.i.zed in known manner having a conducting path between ?'source"
and "drain" to be cut-off by variation of the depletion layer of a ~-n junction9 in particular in the device shown in Figure 90 For e~ample, in the island 107 a ~-type zone l13 may be diffused-in which, with the buried layer 102 9 forms a gate for the current path from source 114 to drain 115 via the narrow gate zone 116 which can be cut-off by applying a sufficient reverse voltage at the gate electrode 1130 It is also possible to use the narrowed part 116 of the hi.gh ohmic resist~r ~J n-type material as a resiDtO
~Z5-1~2~1Z
PHN, 5678 Many variations are possible within the scope o-~ the present inventionO In Figure 79 for example, two islands can be connected electricaLly, if desirable, also via the epitaxial material 68 or alone via the buried n-type layer 62 with a local interruption of the ~-type buried 5~17~7 C layer 63. If desirable, the 4~k~r insulation layer may also comprise extensions present in the islands, for S~
example, as a substratum for wiringO The sunl~cl insula-. tion layer may comprise widenings, for example, to serve as a substratum of a number of conductive strips or at the area where external supply conductors can be :~ secured, for example, by soldering.
-27~
the gallium diffusion the zones 9 whlch belong to juxta-posed islands 4 do not touch each otherO ~here an inter-mediate space is present between the buried layers 5, no detrimental stray transi.stor effect is thus formed between the zones with the intermediate part of the layer 3 below the inset insulation l.ayer 89 so that an effective island separation is obtai.nedO
~16~
13~12q~12 PHN. 5678.
Where, however, the buried layer 5 fully extends underneath the oxide 8, parts of said buriecl layer which extend below juxta-posed islands are connected by a part extending locally under-neath the insulation layer 8. By means of zones 9 an assembly of interconnected zones belongins to different islands 4 and extending locally to the surface is obtained.
One or more zones for semiconductor circuit elements to be formed in the islands 4 can be provided in the resulting struc-ture after removing the layers 19, 21, 22 and 23 by means of further oxidation, masking and diffusion. The buried layers may serve for insulation or form part of a semiconductor circuit element in which a through-connection to a zone of an adjacent island can be obtained and moreover connections to the surface can be obtained, for example, for providing a surface contact.
Instead of using a buried layer S extending underneath an oxide layer 8, zones 9 on either side of the oxide layer 8 may locally extend underneath the oxide over such a distance that a continuous zone is obtained.
The method described has been given only by way of example and the device described may also advantageously be manufactured according to various other methods, for example, that which is described in Applicant's Canadian Patent 925,226 issued April 24, 1973 (PHN. 4775). .
The semiconductor circuit elements, for example, ~2~12:
transistors9 dlode~, res:is-to:r33 p-n-~-n elements3 and so on3 can be pro-v:i.~led. ln known manner i.n the i31ands 4 Instead of in an island ll one or more of -these elements may also be present entirel.y or partly in the form of conductive layers3 for examp1e, metal layers3 on the island-shaped region 4 o:r on the oxide layer 130 Furthermore it is not necessary for the region consti-tuted by the buri.ed :Layer 5 and the zones 9 to form part of the said circui.t el.ement although this is -very desirable from a poin.t of view of space sa-vingO
It will be obvious that the invention furthermore is not restricted to the examples described~ For example, the buried. l.ayer 5 can also be provi.ded9 if desirable, by ion implantation or ep:i.taxi.allyO ~n parti-cular, instead of silicon3 other semiconductor materialswhich can form a usefuL ox.ide pattern3 for e:~ample 3 : silicon carbide, may also be used It is also possible to use, exclusively underneath the inset insulation layer9 a buri.ed .layer of a con-ducti-vity type oppos:ite to that of the epitaxi.al layer3 which buried layer has expanded in the epitaxi.al .1ayer from the substrateO At the area of the connection zone between two zones present in adjacent islands said layer may be interruptedO Such a case wil.l hereinafter be described wi.th reference to Figures 5 to 80 Starting material. is a monocrystalline semi.conductor body 61 of p-type silicon in which by means of con-ven-tional planar methods arseni.c~doped l.ow~ohmic n~type il~l2 PHNo 5678 zones 62 an.d. a boron-doped .low-ohmic ~-type zone 63 are ~ormed. The zone 63 tas t~e form of a network which7 however, is inte-rrupted l.ocallyO For the re3t, the zone 63 encloses t:he zones 62 laterally At the area . 5 of the interruption in the zone 63, the zone 62 is .: passed through the interruptionO The parts of said zone 63 have a width9 for example, of 3 ~0 The resulting stage is shown in Figure 50 As is usual in planar dif-fusion methods 9 an o:~ide 7.ayer 64 is present on the surface of the semiconductor body 61~ This o~ide layer is now removed in a conventional manner by means of hydrofluoric acid A high-ohmic n-type epitaxial layer 68 is then : deposited on the si.Licon body 61, for exampl.e3 i.n a /~l>77 . 15 thickness of 4 ~0 During said depositi.on the zones 62 and 63 which become hu:ri.ed. l.ayersg can expand into the epitaxial layer 68 by diffusionO In particular the buried layer 63 can expand more rapidly than the buried layer 62 since boron diffusesmore rapidly than arsenicO
In known manner the surface of the epitaxial.. layer 68 is covered with a thin si~icon nitride layer 65 and then with a silicon oxide 1.ayer 660 In this layer apertures are provided above th.e ~-type buried zone 639 also in the form of a network, but now expanded above the interrupt-ion(s) in the network of the bu.ried zone 630 The width of /~
said apertures is at least 5 ~0 While u.si.ng the nitride oxide masking 659 66, grooves 67 are etched in the sil.icon ~9_ ~1~2~i2 PHNo 5678 C in a depth of` wel..l over l ~ 0 The resultl.ng stage :îs shown in Figure 6~
The oxide layer 66 is now removed by a conventional hydrofluoric acid etcha.nt and the assembly is then subjected to an oxidizing treatment in steam of 1 at-mosphere at 1000C to form an inset insulation layer 70 consisting of si.li.con oxide, the sil.icon nitr:ide masking 65 protecting the underlying silicon outside the grooves 670 The ox:idation treatment is continued (approximately 16 hours) until a depth of approximately 2 ~ is achieved, the formed oxide having also fi.ll.ed the original grooves 67 entirelyO In the meantime the boron-doped ~-type burîed layer 63 has expanded further in the epitaxial layerO In this stage or after a subse-quent thermal treatment :i.t may adjoin the l.ower side of the formed inset insulation l.ayerO The resul.ti.ng stage is shown i.n Figure 70 The epitaxial layer 68 is now divided into islands which are separated from each other by means of isolation zones formed by the i.nset insulation layer 70 and the buried ~-type layer 63~
Locally, however9 such an isolation zone bel.ow the Lnset insulation layer is interrupted for pass.ing through an ; n-type conductive connection consisti.ng of a part of the buried layer 62 and posslbl.y a remainder present above said l.ayer of the origin~l epitaxially deposited n-type material 680 For example, by means of planar diffusi.on methods~
~20-PHNo 5678 circuit elements may t;hen be formed in the islands în : known manner9 as the.n~ transistor shown in Flgure 89 in which the collector is formed by the epitaxial. n-type material 78, the arsenic-doped buried. l.ayer 62, and the ~ollector-contacting zone 77 formed during the emitter diffusion, the base is formed by the ~-type zone 75 formed by diffusion of boron9 and the emitter is formed by the n~type zone 76 formed by dif-fusion of phosphoru.s~ The resulting stage is shown in Figure 8.
By means of the n-type buried layer 62, the col-lector zone belonging to the island 78 is through-connected to an n-type zone associated with an adjacent island via an interrupt.i.on in the p-type buri.ed la-yer 63 which together with the inset insul.ati.on layer 70 forms the isolation zone between the isl.andsO
Since it had. been ensured in the manufacture that the inset insulation layer was wider than the buried ~-type layer 63, the distance between the buried layer ; 20 63 and the base zone 75 i.s maintained large notwith-standing the fact that the base layer 75 adjoins the inset insulation layer 700 Also in the case of the device shown diagrammatic-ally in Figure 8, th.e advantage is obtained that the upper side of the inset lnsulation layer 70 is present approximately at the same level as the adjacent surface of the epitaxial layerO In known manner9 adjoining ~2l~
1~2~ PHN~ 5678 contacts in window-s i.n thin insulation layers used on the island surface may be provided and suppl.y conductors used which preferably extend over the insul.ation layer 70 as much as possi.bl.eO
In the case described in Figure 8 a thick epitaxial layer is used in which it is avoided, however3 for the good formation of isolation zones, to use a proportiona..ly thicker inset insulation layerO If desirabl.e, the thick-ness of the epitaxial. layer 68 may also be chosen to be smaller so that the inset insulation layer 70 reaches at least to the junction between the substrate 61 and the provided semiconductor layer 680 Since the buried layer 62 extends in the original substrate, said layer can also produce locally below the inset insulation layer a con-ductive connection be$ween two zones on either side of the isolation zoneO
It is obvious that in the islands beside the island in which the transistor shown in Figure 8 is provided9 ~ other circuit elements9 for example, other transistors 9 : 20 may also be providedO
In the embodiment shown in Figure 8 in whi.ch an n-type epitaxial layer is used on a ~-type substrate and an insulation layer which is partly inset in said epitaxial layer, use is made of a highly doped bur.ied layer of the p-type provided in t:he substrate, which layer has ex-panded to the lower sid.e of the insulation layer by dif-fusionO It is of course also possible, for exampl.e in ~22-~2~
PHNo 5678 th0 case of an ep:i.taxi.al. l.ayer of the n-type on a substrate of the p-~ype and an insu.l.ation la.yer inset;
over part of the thickness of the epitaxial layer3 to use a zone present on the lower side of th0 isolation zone in the epitaxial :1.ayer of the conductivity type of the substrateO Th.is ~-type zone present bel.ow the inset insulation layer may have expanded, for exampl.e, by diffusion to the p n junction formed between the substrate and t,he epitaxial .layerO It is al.so possi.ble that said ~-type zone ad.joining the inset insulation layer has expanded to the depletion layer formed between the ~-type substrate and the epitaxial layerO
The above examp:le described with reference to Figures 5 to 8 related to a p-type semi.conduc-t;or substrate body and an n-type epitaxi.al semi.conductor l.ayerO.Of course, in a corresponding manner the starting material may be an n-type semiconductor substrate body and a ~
type semiconductor layer in which the various zones and buried layers may also be chosen to be of correspondingly different conductivity type in a corresponding mannerO
In that case as an n~type doping material in silicon9 for example3 phosphorus3 may be u.sed as a doping for the buried layers 63 of Figure 80 Both boron and ph.osphorus have a very high solu.bil.ity in silicon3 -wh.il.e t;heir dif~
fusion properties do not di.ffer muchO
Figure 9 shows possibilities of island isolation according to the invention in the case in which a mono-crystalline substrate body is used of the same cond.ucti-vity type as the epi.taxia]. l.ayer provided thereonO The monocrystalline silicon substrate body 100 consists3 ~3~
1~02~1~
PHNo 5678 for example, of n~t.ype material having a resisti-vity of, for example, 1 o:hm cmO An epitaKial. layer 101 provided thereon consîsts of silicon of the same con-ductivity type and approximatel.y the same resistivity, while on the boundary of` the substrate body and the epitaxial layer a numher of buried layers 1010 102 and 103 of ~-type sllî.con are provided which are separa-ted from each other by a network of narrow zones 111 of the high-ohmic n-type material. of the su.bstrate and the epitaxial layerO The bur:ied layers are doped9 for example 9 with boron and have expanded from the boundary between :~
the substrate and the epitaxial layer :~ From the upper side of the epitaxial layer an inset insulation layer is provided as described above D the upper 15 surface of which i.s app:roximately at the same lev~l. with the upper side of t:h.e adjacent parts of the epitaxlal ; layerO The inset in~u.Lation layer 109 overl.aps inter alia the n-type zones between the buried layers 101~ l02 and 1030 Furthermore, it ls a.l.so provided locall.y according to intermediate strips f:rom above 9 for example, to a central portion of the buri.ed layer 1020 In this manner the epitaæial layer 104 is divided int.o n~type isl.ands 105, 106, 107 and l08 which are separated from the n type substrate 100 by two ~n junctions and are separated from each other by isol.ation zones which partly consist of the buried insulatl.on 1.ayer 1090 For example 9 the islands 105 and 106 are separated from each other by the ~4_ ~1~32~
PHN~ 5678 inset insulati.on layer lO9, the parts faci,ng each other ; of the buried l.ayers 102 and lO3~ and the intermediate high-ohmic n-type zone 1l1, the islands 106 and 107 are separated from each other by the inset insul.at:i.on layer 109 and the buried layer 102 3 and the islands 107 and 108 are separated from each other by the inset insulation layer 109, the end parts facing each other of the buried layers 101 and 102 and the intermediate high-ohmi.c n-type zone 111, Semi.conductor circuit elements can be formed in known manner in the islands which are separatad from each otherO It is possible that such an underlying ,~ buried layer serves for double insul.ation but it is also . possible that such a buried layer which actuall.y is separated from the substrate by a ~-n junction of the n-type material, forms a functional. part of a circuit element to be provîded9 for example, the collector of a ~-n-~ transistor~ Where it is provided below more than one island, it may al.so serve as a through~connection~
for example, as a common~ possibly floating9 el.ectrode of two circuit elements provided in the islands 106 and 107~ Such a buried layer may also form a functional. part of a circuit element and an insulation for another circuit element. Furthermore, in order to obtain islands of' larger depth it is possibl.e to use layers the upper side of which is situated deeper than the lower side of the inset insulation layer~ narrow intermediate zones of the conductivity type of the bu.ried layers producing a con ~2~-11C)~12 PHNo 5678 nection between the inse-t insulation l.ayers and the buried layers in such manner that islands wh:i.rh are separated from each ot:her are formed which, however, can locally have a larger depth than the inset însul.a-tion layer 109.
A structure of islands correspondlng to Figure 9 may also be obtained by using a p-type substrate 100 on which ~-type epita~i.al material 104 is provided and in which n-type buried layers 1013 102 and 103 are used It is to be noted t:hat it is the object of the Figures to denote that a variety of embodiments are possible without departing from the scope of this in-vention. The number of circuit elements shown is furthermore not limitativeO Semi.conductor circuit ele-ments having contacts of the Schottky type may also be used, while field effect transistors can be real.i.zed in known manner having a conducting path between ?'source"
and "drain" to be cut-off by variation of the depletion layer of a ~-n junction9 in particular in the device shown in Figure 90 For e~ample, in the island 107 a ~-type zone l13 may be diffused-in which, with the buried layer 102 9 forms a gate for the current path from source 114 to drain 115 via the narrow gate zone 116 which can be cut-off by applying a sufficient reverse voltage at the gate electrode 1130 It is also possible to use the narrowed part 116 of the hi.gh ohmic resist~r ~J n-type material as a resiDtO
~Z5-1~2~1Z
PHN, 5678 Many variations are possible within the scope o-~ the present inventionO In Figure 79 for example, two islands can be connected electricaLly, if desirable, also via the epitaxial material 68 or alone via the buried n-type layer 62 with a local interruption of the ~-type buried 5~17~7 C layer 63. If desirable, the 4~k~r insulation layer may also comprise extensions present in the islands, for S~
example, as a substratum for wiringO The sunl~cl insula-. tion layer may comprise widenings, for example, to serve as a substratum of a number of conductive strips or at the area where external supply conductors can be :~ secured, for example, by soldering.
-27~
Claims (56)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A semiconductor device, in particular a mono-lithic integrated circuit, having a monocrystalline semi-conductor substrate body and a semiconductor layer provided on one side thereof and divided into islands which are separated from each other by an isolation zone, at least one circuit element being formed in at least one island, characterized in said island being isolated from the sub-strate body by at least one laterally extending p-n junc-tion at least the part of the isolation zone adjoining the surface of the semiconductor layer being constituted by a layer of an insulating material inset in the semicon-ductor layer and a semiconductor zone associated with the said island being connected in an electrically conductive manner to a zone associated with an adjacent island by means of a connection zone passing underneath the inset insulation layer, the connection zone being isolated from the substrate body and conductively connecting the zones associated with the two islands and wherein the depth to which the insulation layer is inset in the semiconductor is more than 0.5 µm.
2. A semiconductor device as claimed in Claim 2, characterized in that the difference in height between the inset insulation layer and the adjacent semiconductor surface is at most 0.5 µm.
3. A semiconductor device as claimed in Claim 1 wherein the inset insulation layer is a genetic layer which has been obtained by conversion of the semiconductor material into insulating material and a masking is used which can withstand the conversion reaction.
4. A semiconductor device as claimed in Claim 3 wherein the said masking is constituted by silicon nitride.
5. A device as claimed in Claim 1, 2 or 3, where-in the semiconductor material is silicon, the inset insulation is silicon oxide obtained by oxidation from a groove previously provided in the silicon, the groove being filled by genetic silicon oxide.
6. A semiconductor device as claimed in Claim 1, characterized in that the isolation zone comprises a buried layer of the same conductivity type as the semicon-ductor substrate body present underneath the sunken insulation layer, which buried layer is interrupted at the area of the conductive connection of a conductivity type opposite to that of the substrate.
7. A semiconductor device as claimed in Claim 1, characterized in that the semiconductor substrate body and the semiconductor layer provided thereon are of opposite conductivity types and the locally provided conductive connection zone is of a conductivity type equal to that of the provided semiconductor layer.
8. Structure comprising a semiconductor substrate and a semiconductor epitaxial layer upon one surface of said substrate, said epitaxial layer having a substan-tially flat top surface; and a PN isolation junction extending laterally along the structure forming an isola-tion barrier between regions of said substrate and layer;
characterized in that:
said epitaxial layer comprises pockets of epitaxial semiconductor material laterally spaced from each other and annular-shaped regions formed at least partly of oxidized portions of said epitaxial semicon-ductor material surrounding each pocket, said annular-shaped regions extending through said epitaxial layer to said PN isolation junction, and together therewith elec-trically isolating said pockets of epitaxial semiconduc-tor material from each other, and the top surface of said annular-shaped regions being substantially coplanar with the top surface of said epitaxial layer.
characterized in that:
said epitaxial layer comprises pockets of epitaxial semiconductor material laterally spaced from each other and annular-shaped regions formed at least partly of oxidized portions of said epitaxial semicon-ductor material surrounding each pocket, said annular-shaped regions extending through said epitaxial layer to said PN isolation junction, and together therewith elec-trically isolating said pockets of epitaxial semiconduc-tor material from each other, and the top surface of said annular-shaped regions being substantially coplanar with the top surface of said epitaxial layer.
9. Structure as in Claim 8 wherein said substrate is of one conductivity type and said epitaxial layer of semiconductor material is also of said one conductivity type.
10. Structure as in Claim 8 wherein said substrate is of one type conductivity and said epitaxial layer is of the opposite type conductivity.
11. Structure as in Claim 10 wherein said substrate contains a plurality of lowmresistivity regions of opposite type conductivity formed in the surface of said substrate directly beneath said epitaxial layer.
12. Structure as in Claim 10 wherein said substrate contains a plurality of low resistivity tegions of said one type conductivity formed in the surface of said sub-strate directly beneath said epitaxial layer.
13. Structure as in Claim 10 wherein said substrate is of P-type conductivity.
14. Structure as in Claim 10 wherein said substrate is of N-type conductivity.
15. Structure as in Claim 8 wherein each pocket of epitaxial semiconductor material contains selected regions of differing conductivity type.
16. Structure as in Claim 15 wherein said regions of differing conductivity type comprise active and pas-sive semiconductor devices.
17. A method of making a semiconductor structure which comprises the steps of:
growing a doped epitaxial semiconductor layer on a semiconductor substrate;
forming insulation on said epitaxial semicon-ductor layer;
removing portions of said insulation overlying the regions of said epitaxial semiconductor layer to be converted into oxidized isolation regions;
forming depressions to a specified depth in those portions of said epitaxial semiconductor layer exposed by removal of said insulation; and thermally oxidizing the semiconductor material exposed by said depressions to form in said depressions thermally oxidized semiconductor material extending through said epitaxial layer to an isolation PN junction, thereby to subdivide said epitaxial semiconductor layer into a plurality of electrically isolated pockets of semi-conductor material, each pocket being surrounded by an annular-shaped region of oxidized semiconductor material.
growing a doped epitaxial semiconductor layer on a semiconductor substrate;
forming insulation on said epitaxial semicon-ductor layer;
removing portions of said insulation overlying the regions of said epitaxial semiconductor layer to be converted into oxidized isolation regions;
forming depressions to a specified depth in those portions of said epitaxial semiconductor layer exposed by removal of said insulation; and thermally oxidizing the semiconductor material exposed by said depressions to form in said depressions thermally oxidized semiconductor material extending through said epitaxial layer to an isolation PN junction, thereby to subdivide said epitaxial semiconductor layer into a plurality of electrically isolated pockets of semi-conductor material, each pocket being surrounded by an annular-shaped region of oxidized semiconductor material.
18. The method of Claim 17 wherein said insula-tion layer comprises silicon nitride.
19. The method of Claim 17 wherein prior to the step of growing an epitaxial semiconductor layer on said semiconductor substrate, a low resistivity region of one conductivity type is formed in said substrate.
20. The method of Claim 17 wherein said step of growing an epitaxial semiconductor layer on said semi-conductor substrate comprises the step of growing an epitaxial semiconductor layer of opposite conductivity type on said substrate.
21. The method of Claim 19 including the addi-tional step of removing said layer of insulating after the epitaxial semiconductor material exposed by said depressions is thermally oxidized through to said isola-tion PN junction.
22. Structure comprising:
a semiconductor substrate;
a semiconductor epitaxial layer on one surf-ace of said substrate, said epitaxial layer having a substantially flat top surface;
a PN isolation junction extending laterally along the structure forming an isolation barrier between regions of said substrate and said layer;
wherein said epitaxial layer comprises pockets of epitaxial semiconductor material laterally spaced from each other and annular-shaped regions formed of oxidized portions of semiconductor material surrounding each pocket, said semiconductor material which is oxidized including a part of said epitaxial layer, said annular-shaped region extending through said epitaxial layer to said PN isola-tion junction, and together therewith electrically isola-ting said pockets of epitaxial semiconductor material from each other, the top surface of said annular-shaped region being substantially coplanar with the top surface of said epitaxial layer.
a semiconductor substrate;
a semiconductor epitaxial layer on one surf-ace of said substrate, said epitaxial layer having a substantially flat top surface;
a PN isolation junction extending laterally along the structure forming an isolation barrier between regions of said substrate and said layer;
wherein said epitaxial layer comprises pockets of epitaxial semiconductor material laterally spaced from each other and annular-shaped regions formed of oxidized portions of semiconductor material surrounding each pocket, said semiconductor material which is oxidized including a part of said epitaxial layer, said annular-shaped region extending through said epitaxial layer to said PN isola-tion junction, and together therewith electrically isola-ting said pockets of epitaxial semiconductor material from each other, the top surface of said annular-shaped region being substantially coplanar with the top surface of said epitaxial layer.
23. A silicon structure comprising: a semicon-ductor silicon substrate; a semiconductor silicon epitaxial layer upon one surface of said substrate, said epitaxial layer having a substantially flat top surface, and a PN isolation junction extending laterally along the structure forming an isolation barrier between regions of said substrate and layer; said epitaxial layer compris-ing epitaxial silicon pockets laterally spaced from each other and annular-shaped regions formed of thermally oxidized portions of said epitaxial silicon layer sur-rounding each pocket, said annular-shaped regions extend-ing at least to said isolation junction and together therewith electrically isolating said epitaxial silicon pockets from each other, and the top surface of said annular-shaped regions being substantially coplanar with the top surface of said epitaxial layer.
24. Structure as in Claim 23 wherein said epitax-ial layer has a thickness of less than 5 microns.
25. A semiconductor monolithic integrated circuit comprising a monocrystalline-semiconductor substrate, an epitaxial semiconductor layer of given thickness on a surface of said substrate, at least one isolation zone extending from the epitaxial layer surface down to the sub-strate laterally dividing the epitaxial layer into plural islands, at least one PN junction isolating each of said islands from the substrate, and at least one circuit ele-ment within one of the islands, said isolation zone com-prising insulating material formed of converted epitaxial material and sunk into the epitaxial layer from its surface and extending down to but spaced from the substrate such that said sunken insulating material extends over only part of the epitaxial layer thickness, said isolation zone further comprising means extending from the sunken insulating layer to the substrate to complete the isola-tion of the islands.
26. A semiconductor device as claimed in Claim 25 wherein the epitaxial layer consists of silicon and the sunken insulating layer consists of silicon oxide.
27. A semiconductor device as claimed in Claim 25 wherein the isolation completion means comprises a buried layer of a conductivity type opposite to that of the epitaxial layer and extending below the sunken insulation layer.
28. The method of forming a plurality of electri-cally isolated pockets of semiconductor material in a semiconductor structure comprising a silicon substrate with an epitaxial silicon layer thereon, which comprises the steps of:
growing a doped epitaxial silicon layer on said silicon substrate, said doped epitaxial silicon layer hav-ing a conductivity type relative to the conductivity type of at least a portion of the top surface of said substrate such that a laterally-extending PN junction is formed in at least part of said semiconductor structure;
forming a layer of insulation on said epitaxial silicon layer, said insulation having the properties that it is substantially unaffected by at least one etchant used to remove epitaxial silicon and substantially masks the diffusion of oxygen;
removing portions of said insulating overly-ing regions of said epitaxial silicon layer to be con-verted into oxidized silicon;
forming depressions to a specified depth in said epitaxial silicon exposed by removal of said insula-tion by removing part of said epitaxial silicon exposed by removal of said insulation; and subdividing said epitaxial silicon layer into a plurality of electrically isolated pockets of semicon-ductor material by oxidizing the silicon exposed by said depressions to form oxidized silicon extending through said epitaxial silicon layer to said PN junction thereby both to surround each pocket by an annular-shaped region of oxidized silicon, the top surface of said oxidized silicon being substantially coplanar with the top surface of said epitaxial silicon layer, and to electrically isolate each pocket by an annular-shaped region of oxidized silicon and a portion of said laterally-extending PN junc-tion.
growing a doped epitaxial silicon layer on said silicon substrate, said doped epitaxial silicon layer hav-ing a conductivity type relative to the conductivity type of at least a portion of the top surface of said substrate such that a laterally-extending PN junction is formed in at least part of said semiconductor structure;
forming a layer of insulation on said epitaxial silicon layer, said insulation having the properties that it is substantially unaffected by at least one etchant used to remove epitaxial silicon and substantially masks the diffusion of oxygen;
removing portions of said insulating overly-ing regions of said epitaxial silicon layer to be con-verted into oxidized silicon;
forming depressions to a specified depth in said epitaxial silicon exposed by removal of said insula-tion by removing part of said epitaxial silicon exposed by removal of said insulation; and subdividing said epitaxial silicon layer into a plurality of electrically isolated pockets of semicon-ductor material by oxidizing the silicon exposed by said depressions to form oxidized silicon extending through said epitaxial silicon layer to said PN junction thereby both to surround each pocket by an annular-shaped region of oxidized silicon, the top surface of said oxidized silicon being substantially coplanar with the top surface of said epitaxial silicon layer, and to electrically isolate each pocket by an annular-shaped region of oxidized silicon and a portion of said laterally-extending PN junc-tion.
29. The method of Claim 28 wherein said insulation layer comprises silicon nitride.
30. The method of Claim 28 wherein prior to the step of growing said doped epitaxial silicon layer on said silicon substrate, a low resistivity region of one con-ductivity type is formed in said substrate directly beneath the surface of said substrate on which said epit-axial layer is formed, said low resistivity region extend-ing beneath at least part of one electrically isolated pocket of semiconductor material.
31. The method of claim 30 wherein prior to the step of growing an epitaxial silicon layer on said silicon substrate, a low resistivity region of one con-ductivity type is formed in said substrate.
32. The method of Claim 30 wherein said step of growing an epitaxial silicon layer on said silicon sub-strate comprises the step of growing an epitaxial silicon layer of opposite conductivity type on said substrate.
33. The method of Claim 32 including the addi-tional step of removing said layer of insulation after the epitaxial silicon exposed by said depressions is oxidized through to said PN junction.
34. The method of Claim 33 wherein said doped epitaxial silicon layer is of said opposite conductivity type.
35. The method of Claim 30 wherein said impurity of said one conductivity type is diffused through said selected region of epitaxial silicon all the way to said low resistivity region of said one conductivity type in said silicon substrate.
36. The method of Claim 30 wherein said step of growing an epitaxial silicon layer on said silicon sub-strate comprises the step of growing on said substrate an epitaxial silicon layer of said one conductivity type.
37. The method of Claim 36 wherein said low resis-tivity region extends at least beneath all portions of one electrically isolated pocket of semiconductor material.
38. The method of Claim 37 wherein said substrate is of said opposite conductivity type.
39. The method of Claim 36 wherein said epitaxial silicon layer is of said opposite conductivity type.
40. The method of Claim 28 wherein said step of subdividing said epitaxial silicon layer into a plurality of electrically isolated pockets of semiconductor material comprises oxidizing a significant portion of the epitaxial silicon layer through to said PN junction thereby to sur-round each pocket by an annular-shaped region of oxidized silicon, the top surface of said oxidized silicon being substantially coplanar with the top surface of said epi-taxial silicon layer, and to electrically isolate each pocket by an annular-shaped region of oxidized silicon and a portion of said laterally-extending PN junction.
41. The method of Claim 40 wherein said signifi-cant portion of the epitaxial semiconductor material com-prises a major portion of the silicon surface area.
42. The method of Claim 31 wherein said substrate is of opposite conductivity type.
43. The method of Claim 32 wherein said substrate is of opposite conductivity type.
44. Structure comprising a semiconductor substrate and a plurality of pockets of epitaxial semiconductor material upon one surface of said substrate, said plurality of pockets of epitaxial material having substantially flat top surfaces formed substantially in one plane; and a PN
isolation junction extending laterally along the structure forming an isolation barrier between regions of said sub-strate and pockets, characterized in that: said pockets of epitaxial semiconductor material are laterally spaced from each other by annular-shaped regions formed at least partly of oxidized portions of the epitaxial material from which said pockets are formed, said annular-shaped regions extending through said epitaxial semiconductor material to said PN isolation junction, and together therewith electrically isolating said pockets of epita-xial semiconductor material from each other, and the top surfaces of said annular-shaped regions are substantially coplanar with the top surfaces of said pockets of epita-xial semiconductor material; wherein said substrate is of one conductivity type and said pockets of epitaxial semiconductor material are also of said one conductivity type.
isolation junction extending laterally along the structure forming an isolation barrier between regions of said sub-strate and pockets, characterized in that: said pockets of epitaxial semiconductor material are laterally spaced from each other by annular-shaped regions formed at least partly of oxidized portions of the epitaxial material from which said pockets are formed, said annular-shaped regions extending through said epitaxial semiconductor material to said PN isolation junction, and together therewith electrically isolating said pockets of epita-xial semiconductor material from each other, and the top surfaces of said annular-shaped regions are substantially coplanar with the top surfaces of said pockets of epita-xial semiconductor material; wherein said substrate is of one conductivity type and said pockets of epitaxial semiconductor material are also of said one conductivity type.
45. Structure as in Claim 44 wherein said sub-strate is of P-type conductivity.
46. Structure as in Claim 44 wherein said sub-strate is of N-type conductivity.
47. Structure as in Claim 45 wherein said sub-strate contains a plurality of low resistivity regions of N-type conductivity formed in the surface of said sub-strate directly beneath said epitaxial layer.
48. Structure as in Claim 46 wherein said sub-strate contains a plurality of low resistivity regions of P-type conductivity formed in the surface of said sub-strate directly beneath said epitaxial layer.
49. A method for fabricating a dielectrically isolated semiconductor device comprising:
forming a region of a first conductivity type within a semiconductor body of a second conductivity type;
growing an epitaxial layer onto the surface of said semiconductor body containing said region in a manner which results in a movement of impurities of said first conductivity type into the epitaxial layer during its growth which results in an effective extension of said region into said epitaxial layer to form a buried region located partially within said body and said epitaxial layer;
forming a protective layer on the surface of said epitaxial layer in areas where it is subse-quently intended to have semiconductor devices located;
thermally oxidizing the unprotected areas of said surface of said epitaxial layer to a depth which is at least as deep as said buried region;
removing said protective layer; and forming a semiconductor device in said epit-axial layer.
forming a region of a first conductivity type within a semiconductor body of a second conductivity type;
growing an epitaxial layer onto the surface of said semiconductor body containing said region in a manner which results in a movement of impurities of said first conductivity type into the epitaxial layer during its growth which results in an effective extension of said region into said epitaxial layer to form a buried region located partially within said body and said epitaxial layer;
forming a protective layer on the surface of said epitaxial layer in areas where it is subse-quently intended to have semiconductor devices located;
thermally oxidizing the unprotected areas of said surface of said epitaxial layer to a depth which is at least as deep as said buried region;
removing said protective layer; and forming a semiconductor device in said epit-axial layer.
50. The method of Claim 49 wherein said buried region and the areas thermally oxidized are so aligned as to intersect at the upper and outer edge of said buried region which results in a dielectrically isola-tion of the semiconductor region extending from said buried region to said surface and further wherein said semiconductor device is formed in said semiconductor region.
51. The method of Claim 49 wherein the thermally oxidized areas extend to said semiconductor body to dielectrically isolate a semiconductor region extending from said body to said surface and further wherein said semiconductor device is formed in said semiconductor region.
52. The method of Claim 49 wherein the unpro-tected areas are etched to a predetermined depth prior to said thermally oxidizing step.
53. The method of Claim 50 wherein an emitter and base elements of a bipolar semiconductor device are formed within said semiconductor region and said buried region electrically connected as the collector element of said bipolar device.
54. The method of Claim 49 wherein said protec-tive layer comprises silicon nitride and the semiconduc-tor material is silicon.
55. The method of Claim 52 wherein the said depth is substantially equal to said depth of said buried region.
56. The method of Claim 53 wherein said first conductivity type is P, the said second conductivity is N, the conductivity type of said base region is P, and conductivity type of said emitter region is N.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| NL7010208A NL7010208A (en) | 1966-10-05 | 1970-07-10 | |
| NLAANVRAGE7010205,A NL169936C (en) | 1970-07-10 | 1970-07-10 | SEMI-CONDUCTOR DEVICE CONTAINING A SEMI-CONDUCTOR BODY WITH AN OXYDE PATTERN SATURATED AT LEAST IN PART IN THE SEMI-CONDUCTOR BODY. |
| NL7010205 | 1970-07-10 | ||
| NLAANVRAGE7010204,A NL170902C (en) | 1970-07-10 | 1970-07-10 | SEMICONDUCTOR DEVICE, IN PARTICULAR MONOLITHICALLY INTEGRATED SEMICONDUCTOR CIRCUIT. |
| NL7010208 | 1970-07-10 | ||
| NL7010204 | 1970-07-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1102012A true CA1102012A (en) | 1981-05-26 |
Family
ID=27351584
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA117,581A Expired CA1102012A (en) | 1970-07-10 | 1971-07-07 | Semiconductor device, in particular integrated monolithic circuit, and method of manufacturing same |
Country Status (9)
| Country | Link |
|---|---|
| JP (1) | JPS517550B1 (en) |
| BE (1) | BE769735A (en) |
| CA (1) | CA1102012A (en) |
| CH (1) | CH533364A (en) |
| DE (1) | DE2133982C2 (en) |
| ES (2) | ES393040A1 (en) |
| GB (1) | GB1353997A (en) |
| HK (1) | HK58576A (en) |
| SE (1) | SE368480B (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1095413A (en) * | 1964-12-24 |
-
1971
- 1971-07-07 GB GB3184571A patent/GB1353997A/en not_active Expired
- 1971-07-07 CA CA117,581A patent/CA1102012A/en not_active Expired
- 1971-07-07 CH CH1000771A patent/CH533364A/en not_active IP Right Cessation
- 1971-07-07 SE SE880571A patent/SE368480B/xx unknown
- 1971-07-08 DE DE19712133982 patent/DE2133982C2/en not_active Expired
- 1971-07-08 ES ES393040A patent/ES393040A1/en not_active Expired
- 1971-07-08 BE BE769735A patent/BE769735A/en unknown
- 1971-07-08 ES ES393041A patent/ES393041A1/en not_active Expired
- 1971-07-10 JP JP5073171A patent/JPS517550B1/ja active Pending
-
1976
- 1976-09-23 HK HK58576A patent/HK58576A/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| ES393041A1 (en) | 1975-05-16 |
| DE2133982C2 (en) | 1984-12-13 |
| SE368480B (en) | 1974-07-01 |
| DE2133982A1 (en) | 1972-01-13 |
| CH533364A (en) | 1973-01-31 |
| ES393040A1 (en) | 1974-05-16 |
| GB1353997A (en) | 1974-05-22 |
| JPS517550B1 (en) | 1976-03-09 |
| HK58576A (en) | 1976-10-01 |
| BE769735A (en) | 1972-01-10 |
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