CA1099409A - Charge transfer device differencing circuit - Google Patents
Charge transfer device differencing circuitInfo
- Publication number
- CA1099409A CA1099409A CA293,097A CA293097A CA1099409A CA 1099409 A CA1099409 A CA 1099409A CA 293097 A CA293097 A CA 293097A CA 1099409 A CA1099409 A CA 1099409A
- Authority
- CA
- Canada
- Prior art keywords
- charge
- potential well
- transfer
- electrode plate
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000004065 semiconductor Substances 0.000 claims description 11
- 239000002800 charge carrier Substances 0.000 claims description 8
- 230000000717 retained effect Effects 0.000 claims 1
- 230000008878 coupling Effects 0.000 abstract 1
- 238000010168 coupling process Methods 0.000 abstract 1
- 238000005859 coupling reaction Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/24—Arrangements for measuring quantities of charge
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/10—Measuring sum, difference or ratio
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/762—Charge transfer devices
- H01L29/765—Charge-coupled devices
- H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Measurement Of Current Or Voltage (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
CHARGE TRANSFER DEVICE DIFFERENCING CIRCUIT
ABSTRACT OF THE DISCLOSURE
A circuit is disclosed for obtaining an output signal proportional to the difference between two charge packet quantities nondestructively.
The preferred embodiment includes a substrate with a potential well disposed under a floating gate electrode having charge transfer means for entering and removing charge from the potential well. A first quantity of charge Qa which is stored in the potential well is transferred out of the well at time t1 with a resulting proportional increase in the floating gate voltage which results from capacitor coupling from the charge to the floating gate. At a subsequent time t2 a second charge quantity Qb is transferred into the potential well and causes a proportional decrease in the floating gate voltage. The net change .DELTA.V in the floating gate voltage that results is proportional to the difference between the two charge quantities Q ant Qb.
ABSTRACT OF THE DISCLOSURE
A circuit is disclosed for obtaining an output signal proportional to the difference between two charge packet quantities nondestructively.
The preferred embodiment includes a substrate with a potential well disposed under a floating gate electrode having charge transfer means for entering and removing charge from the potential well. A first quantity of charge Qa which is stored in the potential well is transferred out of the well at time t1 with a resulting proportional increase in the floating gate voltage which results from capacitor coupling from the charge to the floating gate. At a subsequent time t2 a second charge quantity Qb is transferred into the potential well and causes a proportional decrease in the floating gate voltage. The net change .DELTA.V in the floating gate voltage that results is proportional to the difference between the two charge quantities Q ant Qb.
Description
17Field of the Invention 18The present invention relates to a circuit for subtracting or 19 obtaining a signal proportional to the difference between two quantities of charge, and more particularly to a charge quantity differencing 21 circuit including a charge transfer device with a floating gate electrode 22 which provides a time-shared capacitor function.
-23Description of the Prior Art . 24Heretofore, the differencing of charge quantities normally : 25employed circuits including two capacitors wherein the two quantities of 26 charge are stored on sep OE ate capacitors and are converted into two 27 corresponding voltages, one of which is then subtracted from the other.
.. :
' Y0976-081 -1-.
, . . _ , ,, , ,,,,, , ,.. =~
,j:~., . , :
` " '' ' ~ :, ' " ' " "
.
, ' . ~ ~
10~94~)9 1 An example of a circuit of this type is described in the publication "Magnitude Differencing Circuit", by D. L. Critchlow et al, in the 3 IBM Technical Disclosure Bulletin, Vol. 18, No. 9, February 1976 at 4 page 3071.
Two capacitor circuits exhibit the undesirable feature that 6 the two capacitors may have inherently different characteristics which 7 effect the charge stored thereon, and when the two resultant voltages 8 are subtracted the effect of the characteristic differences is included g in the difference voltage as a distortion and poses a limit on the accuracy 10 - of the circuit.
11 The present invention is distinct from the two-capacitor 12 devices of the prior art in that it is embodied with a single time-shared 13 floating gate capacitor. Since both charge quantities are sequentially 14 placed on the same capacitor there is no tracking error which might arise if the charge quantities were placed on two separate capacitors.
16 The use of floating gate techniques in charge-coupled devices 17 have been shown in the prior art however, no references are known which -18 employ a floating gate as a time-shared capacitor for-charge differencing.
19 A typical example of a floating gate in a charge-coupled device environ-ment is shown in U.S. patent 3,623,132, issued November 23, 1971, to 21 R. D. Green on an application filed December 14, 1970, and assigned to 22 North American Rockwell Corporation. This patent is cited as being of 23 general background interest and does not relate to the-use of a time-24 shared-capacitor function for charge differencing.
.
SUMMARY OF THE INVENTION
26 An object of the present invention is to provide a charge 27 transfer device employing a single time-shared capacitor for charge 28 differencing.
, .
10~94~9 1 Another object of the present invention is to provide a time-
-23Description of the Prior Art . 24Heretofore, the differencing of charge quantities normally : 25employed circuits including two capacitors wherein the two quantities of 26 charge are stored on sep OE ate capacitors and are converted into two 27 corresponding voltages, one of which is then subtracted from the other.
.. :
' Y0976-081 -1-.
, . . _ , ,, , ,,,,, , ,.. =~
,j:~., . , :
` " '' ' ~ :, ' " ' " "
.
, ' . ~ ~
10~94~)9 1 An example of a circuit of this type is described in the publication "Magnitude Differencing Circuit", by D. L. Critchlow et al, in the 3 IBM Technical Disclosure Bulletin, Vol. 18, No. 9, February 1976 at 4 page 3071.
Two capacitor circuits exhibit the undesirable feature that 6 the two capacitors may have inherently different characteristics which 7 effect the charge stored thereon, and when the two resultant voltages 8 are subtracted the effect of the characteristic differences is included g in the difference voltage as a distortion and poses a limit on the accuracy 10 - of the circuit.
11 The present invention is distinct from the two-capacitor 12 devices of the prior art in that it is embodied with a single time-shared 13 floating gate capacitor. Since both charge quantities are sequentially 14 placed on the same capacitor there is no tracking error which might arise if the charge quantities were placed on two separate capacitors.
16 The use of floating gate techniques in charge-coupled devices 17 have been shown in the prior art however, no references are known which -18 employ a floating gate as a time-shared capacitor for-charge differencing.
19 A typical example of a floating gate in a charge-coupled device environ-ment is shown in U.S. patent 3,623,132, issued November 23, 1971, to 21 R. D. Green on an application filed December 14, 1970, and assigned to 22 North American Rockwell Corporation. This patent is cited as being of 23 general background interest and does not relate to the-use of a time-24 shared-capacitor function for charge differencing.
.
SUMMARY OF THE INVENTION
26 An object of the present invention is to provide a charge 27 transfer device employing a single time-shared capacitor for charge 28 differencing.
, .
10~94~9 1 Another object of the present invention is to provide a time-
2 shared capacltor charge differencing circuit~wherein tracking and non-
3 linearity errors are cancelled.
4 A further object of the present invention is to provide a charge transfer circuit for comparing two charge quantities on a 6 single capacitor nondestructively.
7 The foregoing and other ob;ects, features and advantages 8 of the inventlon will be apparent from the following more particular 9 description of preferred embodiments of the invention, as illustrated in the accompanying drawings.
12 FIG. 1 is a partial schematic illustration of an embodiment of 13 a charge transfer circuit including a time-shared capacitor for charge 14 differencing.
FIG. 2 is a schematic diagram of an equivalent circuit of the 16 device shown in FIG. 1.
, 18 -In charge transfer device technology involving charge coupled 19 devices and bucket brigade devices, an often required function is the determination of the difference between two charge quantities. Since 21 there is no effective way of directly subtracting one charge packet from 22 another, a simple approach is to convert the charge packets to voltages 23 and then subtract. Heretofore, the conventional approach was to introduce 24 the two charge packets to two capacitors and then determine the difference between the resulting voltages. Since the characteristics of the two 26 capacitors are never identical, an inherent capacitor tracking error and 27 non-linearity error will be present in the difference voltage.
Y0976-081 - }
~ sss;l~s 1 FIG. 1 illustrates an embodiment of an n-channel charge 2 traasfer device wherein a single capacitor function of a floating gate 3 electrode is time-shared by the two charge packets and a difference 4 voltage is produced which avoids the aforementioned errors. Charge coupled devices are well known in the art as are the techniques for 6 charge retentlon and transfer used in the description of the embodiment 7 of FIG. 1, and need not be described in detail.
8 More particularly, FIG. 1 shows a schematic view of a charge g coupled device embodiment on the invention including semiconductor substrate 10. A plate 12 of capacitor 14 i9 disposed over semiconductor 11 substrate 10 and insulated from semiconductor substrate 10 by an insulating 12 layer, for example silicon dioxide or a silicon nitride. Plate 12 is -13 referred to as a floating gate Connected to it is a total loading capaci-14 tance CL. Plate 12 is connected to a bias voltage source 13 through switch 15. With appropriate bias voltage on plate 12, the region sub-16 jacent plate 12 in the silicon surface becomes what is referred to in 17 the art as a potential well in which mobil minority charge carriers can 18 be stored, entered, or removed by charge transfer techniques. The 19 mobile charge carriers in the potential well plus the immobile charge in the depletion region of the potential well form the second plate of 21 capacitor 14. The potential well is represented in FIG. 1 as region 16.
Z2 Two charge transfer electrodes 18 and 20 are disposed over 23 semiconductor substrate 10 on either side of plate 12. Transfer electrodes 24 18 and 20 are connected to pulse sources such that quantities of charge may be transferred into and out of potential well 16 in response to 26 transfer pulses applied to electrodes 18 and 20.
Y0976-081 -4~
-~(i. 94~9 1 Additional electrodes 22 and 24 are disposed over semiconductor 2 substrate 10 on the opposite sides of transfer electrodes 18 and 20 and 3 are connected to voltage sources to create respectively potential wells 4 26 and 28 which serve to store quantities of charge carriers which may be transferred into or out of potential well 16.
6 In operation, assume that the difference is to be determined 7 between a charge quantity deslgnated as charge packet Q and a different 8 charge quantity designated as charge packet Qb. Initially, one charge 9 packet, for example Q , is stored in potential well 16, having been transferret therein at a previous time to. In order to effect the 11 transfer of charge packet Qa i~to potential well 16, switch 15 is temporarl-12 ly closed to establish the patential well 16 under plate 12. At the 13 completion o the transfer of charge packet Qa into potential well 16 14 plate 12 and output terminal 30 have an initial voltage condition, and switch 15 is open, allowing plate 12 to float.
16 The second charge packet Qb is initially stored in potential lJ well 28, having been inserted therein by conventional charge coupled 18 device charge transfer techniques well known to those skilled in the 19 art.
At a time tl a clocking pulse is applied to transfer electrode 21 18 causing charge packet Qa to be transferred from potential well 16 and 22 into potential well 26. After a sufficient time to allow the clocking 23 transients to decay, the transferring of Qa out from under plate 12 24 produces a proportional increase in the floating gate voltage at terminal 30 as follows:
Q C
26 V , a ox [ t ( COX + C )] (COX + CL) (1) Y097~-081 -5-". . .
.
~a~s~s 1 where CL is the previously mentioned loading capacitance, 2 COX is the oxide capacitance of capacitor 14, 3 Cd is the non-linear depletion capacitance of capacitor 14.
4 At a time t2 a second clocking pulse is applied to transfer electrode 20 and charge packet Qb is transferred into potential well 16, 6 which,after transient decay, produces a proportional decrease in the 7 floating gate voltage as follows:
b C C
[ ( C~x + CL ) ] L (2) 9 Thus, a net change in the floating gate voltage ~V results that is related to Qa ~ Qb; to the extent that non-linearities are 11 small, 12 ~V a (Qa ~ Qb) (3) 13 Any error in the difference voltage as a result of the non-14 linearity of Cd can be minimized by using a lightly doped substrate and i~ particularly minimized when ~V is small. Since the capacitance 14 -16 between the floating gate and the substrate 10 is time-shared by both Qa 17 and Qb' the tracking error which would exist between two unmatched 18 capacitors is non-existent. In the specific case where it is only l9 - desired to determine which of the quantities Qa and Qb is larger, any non-linearities will not effect such a determination.
21 Another import-ant feature of the present invention as embodied 22 in FIG. 1 is that the difference voltage QV is independent of the relative 23 amplitudes of the clocking pulses applied to transfer electrode 18 at t 24 and transfer electrode 20 at t2. The two clocking pulses may have different amplitudes, which is the usual situation in~practice, but as ~ .
~q9g~g 1 long as each pulse returns to its o~iginal level the difference voltage 2 ~V will not be affected. Although the charge transfer functions were 3 described using clock pulses applied to electrodes 18 and 20, alternative 4 techniques known in the art, such as varying the potential on electrodes 22 and 24, may also be used.
6 FIG. 2 is a schematic illustration of the equivalent circuit 7 of the structure of FIG. 1 showing the relative arrangement of the C x' 8 Cd and-CL parameters.
9 The present invention can have wide application as a differencing circuit in many charge transfer device systems such as analog-to-digital 11 and digital-to-analog converters. Also, if only an indication of the 12 greater of Qa and Qb is desired, as in comparator circults and many 13 analog-to-digital converters, the polarity of ~V can be detected accurate-14 ly by a non-precision high gain amplifier and latch.
Although the embodiment of FIG. 1 employs an n-channel charge 16 coupled device structure a p-channel device structure may also be employed.
17 Also, one skilled in the art will appreciate that an equivalent bucket 18 brigade device structure can be used rather than a charge coupled device.
19 While the invention has been particularly shown and described 2~ with reference to preferred embodiments thereof, it will be understood 21 by those skilled in the art that the foregoing and other changes in form 22 and details may be made therein without departing from the spirit and 23 scope of the invention.
7 The foregoing and other ob;ects, features and advantages 8 of the inventlon will be apparent from the following more particular 9 description of preferred embodiments of the invention, as illustrated in the accompanying drawings.
12 FIG. 1 is a partial schematic illustration of an embodiment of 13 a charge transfer circuit including a time-shared capacitor for charge 14 differencing.
FIG. 2 is a schematic diagram of an equivalent circuit of the 16 device shown in FIG. 1.
, 18 -In charge transfer device technology involving charge coupled 19 devices and bucket brigade devices, an often required function is the determination of the difference between two charge quantities. Since 21 there is no effective way of directly subtracting one charge packet from 22 another, a simple approach is to convert the charge packets to voltages 23 and then subtract. Heretofore, the conventional approach was to introduce 24 the two charge packets to two capacitors and then determine the difference between the resulting voltages. Since the characteristics of the two 26 capacitors are never identical, an inherent capacitor tracking error and 27 non-linearity error will be present in the difference voltage.
Y0976-081 - }
~ sss;l~s 1 FIG. 1 illustrates an embodiment of an n-channel charge 2 traasfer device wherein a single capacitor function of a floating gate 3 electrode is time-shared by the two charge packets and a difference 4 voltage is produced which avoids the aforementioned errors. Charge coupled devices are well known in the art as are the techniques for 6 charge retentlon and transfer used in the description of the embodiment 7 of FIG. 1, and need not be described in detail.
8 More particularly, FIG. 1 shows a schematic view of a charge g coupled device embodiment on the invention including semiconductor substrate 10. A plate 12 of capacitor 14 i9 disposed over semiconductor 11 substrate 10 and insulated from semiconductor substrate 10 by an insulating 12 layer, for example silicon dioxide or a silicon nitride. Plate 12 is -13 referred to as a floating gate Connected to it is a total loading capaci-14 tance CL. Plate 12 is connected to a bias voltage source 13 through switch 15. With appropriate bias voltage on plate 12, the region sub-16 jacent plate 12 in the silicon surface becomes what is referred to in 17 the art as a potential well in which mobil minority charge carriers can 18 be stored, entered, or removed by charge transfer techniques. The 19 mobile charge carriers in the potential well plus the immobile charge in the depletion region of the potential well form the second plate of 21 capacitor 14. The potential well is represented in FIG. 1 as region 16.
Z2 Two charge transfer electrodes 18 and 20 are disposed over 23 semiconductor substrate 10 on either side of plate 12. Transfer electrodes 24 18 and 20 are connected to pulse sources such that quantities of charge may be transferred into and out of potential well 16 in response to 26 transfer pulses applied to electrodes 18 and 20.
Y0976-081 -4~
-~(i. 94~9 1 Additional electrodes 22 and 24 are disposed over semiconductor 2 substrate 10 on the opposite sides of transfer electrodes 18 and 20 and 3 are connected to voltage sources to create respectively potential wells 4 26 and 28 which serve to store quantities of charge carriers which may be transferred into or out of potential well 16.
6 In operation, assume that the difference is to be determined 7 between a charge quantity deslgnated as charge packet Q and a different 8 charge quantity designated as charge packet Qb. Initially, one charge 9 packet, for example Q , is stored in potential well 16, having been transferret therein at a previous time to. In order to effect the 11 transfer of charge packet Qa i~to potential well 16, switch 15 is temporarl-12 ly closed to establish the patential well 16 under plate 12. At the 13 completion o the transfer of charge packet Qa into potential well 16 14 plate 12 and output terminal 30 have an initial voltage condition, and switch 15 is open, allowing plate 12 to float.
16 The second charge packet Qb is initially stored in potential lJ well 28, having been inserted therein by conventional charge coupled 18 device charge transfer techniques well known to those skilled in the 19 art.
At a time tl a clocking pulse is applied to transfer electrode 21 18 causing charge packet Qa to be transferred from potential well 16 and 22 into potential well 26. After a sufficient time to allow the clocking 23 transients to decay, the transferring of Qa out from under plate 12 24 produces a proportional increase in the floating gate voltage at terminal 30 as follows:
Q C
26 V , a ox [ t ( COX + C )] (COX + CL) (1) Y097~-081 -5-". . .
.
~a~s~s 1 where CL is the previously mentioned loading capacitance, 2 COX is the oxide capacitance of capacitor 14, 3 Cd is the non-linear depletion capacitance of capacitor 14.
4 At a time t2 a second clocking pulse is applied to transfer electrode 20 and charge packet Qb is transferred into potential well 16, 6 which,after transient decay, produces a proportional decrease in the 7 floating gate voltage as follows:
b C C
[ ( C~x + CL ) ] L (2) 9 Thus, a net change in the floating gate voltage ~V results that is related to Qa ~ Qb; to the extent that non-linearities are 11 small, 12 ~V a (Qa ~ Qb) (3) 13 Any error in the difference voltage as a result of the non-14 linearity of Cd can be minimized by using a lightly doped substrate and i~ particularly minimized when ~V is small. Since the capacitance 14 -16 between the floating gate and the substrate 10 is time-shared by both Qa 17 and Qb' the tracking error which would exist between two unmatched 18 capacitors is non-existent. In the specific case where it is only l9 - desired to determine which of the quantities Qa and Qb is larger, any non-linearities will not effect such a determination.
21 Another import-ant feature of the present invention as embodied 22 in FIG. 1 is that the difference voltage QV is independent of the relative 23 amplitudes of the clocking pulses applied to transfer electrode 18 at t 24 and transfer electrode 20 at t2. The two clocking pulses may have different amplitudes, which is the usual situation in~practice, but as ~ .
~q9g~g 1 long as each pulse returns to its o~iginal level the difference voltage 2 ~V will not be affected. Although the charge transfer functions were 3 described using clock pulses applied to electrodes 18 and 20, alternative 4 techniques known in the art, such as varying the potential on electrodes 22 and 24, may also be used.
6 FIG. 2 is a schematic illustration of the equivalent circuit 7 of the structure of FIG. 1 showing the relative arrangement of the C x' 8 Cd and-CL parameters.
9 The present invention can have wide application as a differencing circuit in many charge transfer device systems such as analog-to-digital 11 and digital-to-analog converters. Also, if only an indication of the 12 greater of Qa and Qb is desired, as in comparator circults and many 13 analog-to-digital converters, the polarity of ~V can be detected accurate-14 ly by a non-precision high gain amplifier and latch.
Although the embodiment of FIG. 1 employs an n-channel charge 16 coupled device structure a p-channel device structure may also be employed.
17 Also, one skilled in the art will appreciate that an equivalent bucket 18 brigade device structure can be used rather than a charge coupled device.
19 While the invention has been particularly shown and described 2~ with reference to preferred embodiments thereof, it will be understood 21 by those skilled in the art that the foregoing and other changes in form 22 and details may be made therein without departing from the spirit and 23 scope of the invention.
Claims (5)
1. A circuit for determining the difference in magnitude between first and second quantities of electrical charge comprising:
means for locally retaining quantities of electrical charge carriers, said retaining means including a first electrode plate connected to an output terminal for manifesting an output voltage pro-portional to quantities of electrical charge retained in said means, first charge transfer means for transferring a first discrete quantity of charge out of said charge retaining means, thereby producing a first change in said voltage on said output terminal proportional to said first quantity of electrical charge, and second charge transfer means for transferring a second discrete quantity of electrical charge into said charge retaining means thereby producing a second change in said output voltage on said output terminal proportional to said second quantity of electrical charge, said net change produced in sald output voltage being proportional to the difference in magnitude between said first and second quantities of charge.
means for locally retaining quantities of electrical charge carriers, said retaining means including a first electrode plate connected to an output terminal for manifesting an output voltage pro-portional to quantities of electrical charge retained in said means, first charge transfer means for transferring a first discrete quantity of charge out of said charge retaining means, thereby producing a first change in said voltage on said output terminal proportional to said first quantity of electrical charge, and second charge transfer means for transferring a second discrete quantity of electrical charge into said charge retaining means thereby producing a second change in said output voltage on said output terminal proportional to said second quantity of electrical charge, said net change produced in sald output voltage being proportional to the difference in magnitude between said first and second quantities of charge.
2. A circuit according to claim 1 wherein said charge retainlng means includes a semiconductor substrate subjacent said first electrode plate and bias means selectively connected to said first electrode plate for selectively creating a first potential well in said semiconductor substrate for storing electrical charge carriers.
3. A circuit according to claim 2 wherein said first electrode plate and said substrate form a single electrical capacitor and wherein said output voltage on said output terminal is a function of the capacitance between said first electrode plate and said substrate and the magnitude of the quantity of charge carriers in said first potential well.
4. A circuit according to claim 2 wherein said first charge transfer means includes a first transfer electrode disposed over said semiconductor substrate adjacent to said first electrode plate and a second electrode plate disposed over said semiconductor substrate adjacent to said first transfer electrode for producing a second potential well in said substrate, said first transfer electrode and said second electrode plate functioning to transfer charge carriers out of said first potential well and into said second potential well.
5. A circuit according to claim 4 wherein said second charge transfer means includes a second transfer electrode disposed over said semiconductor substrate adjacent to said first electrode plate and a third electrode plate disposed over said semiconductor substrate adjacent to said second transfer electrode for producing a third potential well in said substrate, said second transfer electrode and said third electrode plate functioning to transfer charge carriers out of said third potential well and into said first potential well.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US78572377A | 1977-04-07 | 1977-04-07 | |
| US785,723 | 1977-04-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1099409A true CA1099409A (en) | 1981-04-14 |
Family
ID=25136433
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA293,097A Expired CA1099409A (en) | 1977-04-07 | 1977-12-14 | Charge transfer device differencing circuit |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS53125872A (en) |
| CA (1) | CA1099409A (en) |
| DE (1) | DE2811146A1 (en) |
| FR (1) | FR2386942A1 (en) |
| IT (1) | IT1113115B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4239983A (en) * | 1979-03-09 | 1980-12-16 | International Business Machines Corporation | Non-destructive charge transfer device differencing circuit |
| FR2455772B1 (en) * | 1979-05-04 | 1986-01-17 | Thomson Csf | DEVICE FOR TRANSFERRING SUBTRACTION LOADS AND GENERATING QUANTITIES OF LOADS AND SYSTEM PROVIDED WITH SUCH A DEVICE |
| DE2936704A1 (en) * | 1979-09-11 | 1981-03-26 | Siemens AG, 1000 Berlin und 8000 München | MONOLITHICALLY INTEGRATED CIRCUIT WITH A TWO-DIMENSIONAL IMAGE SENSOR |
| DE2939490A1 (en) * | 1979-09-28 | 1981-04-16 | Siemens AG, 1000 Berlin und 8000 München | MONOLITHICALLY INTEGRATED TWO-DIMENSIONAL IMAGE SENSOR WITH A DIFFERENTIAL LEVEL |
| US4639678A (en) * | 1983-12-30 | 1987-01-27 | International Business Machines Corporation | Absolute charge difference detection method and structure for a charge coupled device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3623132A (en) * | 1970-12-14 | 1971-11-23 | North American Rockwell | Charge sensing circuit |
| IL52589A (en) * | 1976-09-15 | 1979-09-30 | Hughes Aircraft Co | Charge coupled device subtractor |
-
1977
- 1977-12-14 CA CA293,097A patent/CA1099409A/en not_active Expired
-
1978
- 1978-03-07 FR FR7807534A patent/FR2386942A1/en active Granted
- 1978-03-07 JP JP2508578A patent/JPS53125872A/en active Pending
- 1978-03-15 DE DE19782811146 patent/DE2811146A1/en not_active Withdrawn
- 1978-03-21 IT IT21405/78A patent/IT1113115B/en active
Also Published As
| Publication number | Publication date |
|---|---|
| IT1113115B (en) | 1986-01-20 |
| FR2386942A1 (en) | 1978-11-03 |
| JPS53125872A (en) | 1978-11-02 |
| IT7821405A0 (en) | 1978-03-21 |
| FR2386942B1 (en) | 1982-07-23 |
| DE2811146A1 (en) | 1978-10-19 |
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