CA1097743A - Modem for the high speed transmission of binary data over an fm communications system - Google Patents
Modem for the high speed transmission of binary data over an fm communications systemInfo
- Publication number
- CA1097743A CA1097743A CA304,794A CA304794A CA1097743A CA 1097743 A CA1097743 A CA 1097743A CA 304794 A CA304794 A CA 304794A CA 1097743 A CA1097743 A CA 1097743A
- Authority
- CA
- Canada
- Prior art keywords
- modem
- coupled
- signal
- binary
- receiver
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Dc Digital Transmission (AREA)
Abstract
TITLE
MODEM FOR THE HIGH SPEED TRANSMISSION OF
BINARY DATA OVER AN FM COMMUNICATIONS SYSTEM
INVENTORS
Daniel Gelbart Thomas W. Purdy ABSTRACT OF THE DISCLOSURE
A modem for the high speed transmission of binary data over an FM communications system in which the transmitter section of the modem integrates the first bit of each sequence of similar polarity bits IN the input binary data to form a three level signal. The receiver section of the modem filters out the DC and the high frequency components in the received signals, converts the received signal to a two level binary signal, generates a clocking signal and synchronizes the two level binary signal to the clocking signal to reconstruct the original binary data.
MODEM FOR THE HIGH SPEED TRANSMISSION OF
BINARY DATA OVER AN FM COMMUNICATIONS SYSTEM
INVENTORS
Daniel Gelbart Thomas W. Purdy ABSTRACT OF THE DISCLOSURE
A modem for the high speed transmission of binary data over an FM communications system in which the transmitter section of the modem integrates the first bit of each sequence of similar polarity bits IN the input binary data to form a three level signal. The receiver section of the modem filters out the DC and the high frequency components in the received signals, converts the received signal to a two level binary signal, generates a clocking signal and synchronizes the two level binary signal to the clocking signal to reconstruct the original binary data.
Description
1~Ca7i~3 BACXGROUND OF THE INVENTION
The present invention relates generally to transmission of digital data over an FM radio link and more particularly to a novel modem for data transmission over an FM radio link.
Those concerned with data transmission over fixed or mobile FM radios, such as, for example, law enforcement and public safety agencies, and transportation industries, have been confronted with the necessity of providing high speed digital data transmission over FM radio links. The FM
radio link may be, for example, of the voice communication type having to be modified for digital data transmission.
Most of these FM links do not provide DC coupling as it is not required for voice and slower methods of data communications.
Certain data transmission devices not requiring ~C coupling in the radio link employ modula~ion methods such as ~requency Shift Keying (FSK) and Phase Shift Keying IPSK). Generally, the data transmission speed for a given 2G com~unication channel is twice as fast when using conventionally encoded or serial Non Return to Zero data (NRZ) as when using two level FSK or PSK. The problems in using NRZ are the D~ coupling required and the clock recovery, as NR~ has few or no transitions in the data stream. As a consequence, NRZ has seen little use in FM
radio data transmission systems despite its high~r speed capability.
United States Patent 3,197,705 which issued on I July 25, 1965 to H.H. Da lon~ describes a method o~
3~ genera';i!lg a three level signal fro~ binary d~ta for data --1 ~
1C!!~77~3 transmission. Ho~ever, the circuitry is complex and does not provide for synchronize~ output data from the receiver.
SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide a modem for high speed data transmission over an FM link.
It is a further object of this invention to provide a modem for the transmission of serial NRZ data over an FM link.
It is another object of this invention to provide a low cost modem for high speed data transmission over an FM link.
It is a further object of this invention to ,, provide inherently stahle and maintenance free data ; transmission apparatus.
It is another object of this invention to provide a modem which provides output data synchronized to - a self-generated clock signal.
These and other objects are achieved in a modem in accordance with the present invention for a communications system having an FM transmitter and receiver. The transmitter section of the modem includes an integrator for integrating the input binary data having a binary rate f and the integrat~r is limited to integrating only the first binary bit in any sequence of bits having the same polarity. The output of the integrator is coupled to the F~ ~ransmitter.
The receiver section of the modem includes a DC filter coupled to the receiver for hlocking DC in the receiver signal, a comparator with hysteresis coupled to the filter for converting the receiver signal to a binary data signal, a clock circuit coupled to the comparator output for generating a bina~y clock signal of frequency f, and a logic 1~7743 element having an input coupled to the co`nparator and controlled by the binary clock signal to provide an output binary data signal synchronized to the clock signal.
The integrator may consist of an operational amplifier having an input terminal and an output terminal, a resistor R serially connected to the input of the operational amplifier, a capacitor connected between the input terminal and the output terminal of the operational ~nplifier, and two zener diodes of limiting voltage + Vz connected in series across the capacitor. The component values can be determined by the equation l/f = RCVz/ VH
where VH is the positive or negative amplitude of the data bits.
The clocking circuit may consist of a delay element coupled to the comparator, the delay elemen. having a delay period smaller than l/f and preferrably 1/2f, an exclusive-or gate having one input coupled to the delay element and a second input coupled to the comparator, a band-pass filter coupled to the exclusive-or gate means and waveform shaping
The present invention relates generally to transmission of digital data over an FM radio link and more particularly to a novel modem for data transmission over an FM radio link.
Those concerned with data transmission over fixed or mobile FM radios, such as, for example, law enforcement and public safety agencies, and transportation industries, have been confronted with the necessity of providing high speed digital data transmission over FM radio links. The FM
radio link may be, for example, of the voice communication type having to be modified for digital data transmission.
Most of these FM links do not provide DC coupling as it is not required for voice and slower methods of data communications.
Certain data transmission devices not requiring ~C coupling in the radio link employ modula~ion methods such as ~requency Shift Keying (FSK) and Phase Shift Keying IPSK). Generally, the data transmission speed for a given 2G com~unication channel is twice as fast when using conventionally encoded or serial Non Return to Zero data (NRZ) as when using two level FSK or PSK. The problems in using NRZ are the D~ coupling required and the clock recovery, as NR~ has few or no transitions in the data stream. As a consequence, NRZ has seen little use in FM
radio data transmission systems despite its high~r speed capability.
United States Patent 3,197,705 which issued on I July 25, 1965 to H.H. Da lon~ describes a method o~
3~ genera';i!lg a three level signal fro~ binary d~ta for data --1 ~
1C!!~77~3 transmission. Ho~ever, the circuitry is complex and does not provide for synchronize~ output data from the receiver.
SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide a modem for high speed data transmission over an FM link.
It is a further object of this invention to provide a modem for the transmission of serial NRZ data over an FM link.
It is another object of this invention to provide a low cost modem for high speed data transmission over an FM link.
It is a further object of this invention to ,, provide inherently stahle and maintenance free data ; transmission apparatus.
It is another object of this invention to provide a modem which provides output data synchronized to - a self-generated clock signal.
These and other objects are achieved in a modem in accordance with the present invention for a communications system having an FM transmitter and receiver. The transmitter section of the modem includes an integrator for integrating the input binary data having a binary rate f and the integrat~r is limited to integrating only the first binary bit in any sequence of bits having the same polarity. The output of the integrator is coupled to the F~ ~ransmitter.
The receiver section of the modem includes a DC filter coupled to the receiver for hlocking DC in the receiver signal, a comparator with hysteresis coupled to the filter for converting the receiver signal to a binary data signal, a clock circuit coupled to the comparator output for generating a bina~y clock signal of frequency f, and a logic 1~7743 element having an input coupled to the co`nparator and controlled by the binary clock signal to provide an output binary data signal synchronized to the clock signal.
The integrator may consist of an operational amplifier having an input terminal and an output terminal, a resistor R serially connected to the input of the operational amplifier, a capacitor connected between the input terminal and the output terminal of the operational ~nplifier, and two zener diodes of limiting voltage + Vz connected in series across the capacitor. The component values can be determined by the equation l/f = RCVz/ VH
where VH is the positive or negative amplitude of the data bits.
The clocking circuit may consist of a delay element coupled to the comparator, the delay elemen. having a delay period smaller than l/f and preferrably 1/2f, an exclusive-or gate having one input coupled to the delay element and a second input coupled to the comparator, a band-pass filter coupled to the exclusive-or gate means and waveform shaping
2~ means coupled to the band-pass filter to provide the binary clock signal.
Finally the receiver modem section may further include a low pass filter coupled betwe~n the DC filter and the comparator, the low pass filter having a time constant equal or smaller than l/f.
BRIEF DESCRIPTION OF THE DRAWINGS:
In the drawings:
Figure 1 schematically illustrates an F~
con~unica ions system including the modem in accordance with this invention; and
Finally the receiver modem section may further include a low pass filter coupled betwe~n the DC filter and the comparator, the low pass filter having a time constant equal or smaller than l/f.
BRIEF DESCRIPTION OF THE DRAWINGS:
In the drawings:
Figure 1 schematically illustrates an F~
con~unica ions system including the modem in accordance with this invention; and
3--10~77~3 Figure 2 illustrates typical waveforms o~ the signal at various points A to K of the circuit shown in figure 1.
DESCRIPTION OF 'rHE PREFERRED EMBODIMæNT
~- Referring to the drawings, figure 1 illustrates an FM communications system which consists of a transmitting , . .,;
~,~ section 1 and a receiving section 2. The transmitting section 1 includes a conventional FM transmitter 3 with . ~.,,.~ .
modulator and pre-emphasis network and a transmitter section
DESCRIPTION OF 'rHE PREFERRED EMBODIMæNT
~- Referring to the drawings, figure 1 illustrates an FM communications system which consists of a transmitting , . .,;
~,~ section 1 and a receiving section 2. The transmitting section 1 includes a conventional FM transmitter 3 with . ~.,,.~ .
modulator and pre-emphasis network and a transmitter section
4 of the modem in accordance with the present invention. The -, receiving section 2 includes a conventional FM receiver 5 '~ and a receiver section 6 of the modem in accordance with this invention.
The transmitter sec~ion 4 of the modem to which standard serial NRZ data is applied at terminal 7 consists of an integrator 8 having an operational amplifier 9, resistor 10, and capacitor 11. The output of integrator 8 is limited from reaching the maximum voltage by zener diodes 12 and 13. ~ariable resistor 14 at the output of ; 20 integrator 8 determines the portion of the integrator's -output to be fed to the F~ transmitter 3. Conven-tional FM transmitters include a pre-emphasis network which increases or boosts the high frequencies of the input signal, followed by a modulator. One type of FM transmitter includes a modulator, commonly known as a phase modulator, B in which the pre-emphasis network function is carried out as an inseparable part of the FM modulator. The value of ~o ~\
resistor ~ and capacitor ~ is chosen to allow the integrator ~output to reach the voltage of the zener diodes 12, 13 within the period of one tran~mitted bit. For example, if the data rate is f, the period of one bit is 1/f; resistor ~9~ ~ ~3 has a value of R, capacitor ~ a value of C, the limiting 1~ point of zener diodes 12 and 13 is + Vz and the input data will have a value of f VH when positive and - VH when negative; then the values are chosen so that l/f = R-C-Vz/VH. The data rate f which may be transmitted will depend on the channel bandwidth fb and may be as high as twice the bandwidth fb.
The transmitted data is received by the FM
reseiver 5 which conventionally includes a demodulator or ,0 frequency discriminator circuit followed by a de-emphasis network for voice communication. For data communication in accordance with this invention, the input to the receiver - section 6 of the modem is coupled directly to the frequency discriminator circuit in the receiver 5. The receiver section 6 of the modem first includes two filters, the first having a capacitor 15 and resistor 16 which block any DC
component that may have been superimposed on the signal due to imperfections in the operation of the FM radio link, an~
the second having resistors 17, 18 and capacitor 19 which form a low-pass filter to remove sharp noise pulses that may have been superimposed on the signal due to other imperfections in the operation of the FM radio link. The 15 l6 time constant of capacitor ~ and resistor ~ is chosen to be much 3arger than the duration of one bit. The time constant of resistors 17, 18 and capacitor 19 is chosen to be equal or smaller to the period of one bit. Small variations in the values of ~hese components will h~ve no adverse ef'ects on the operation of this invention. A
cGmparator 21 is coupled to resistor 18 and has an amount of hysteresis determined by t~e ratio of resistor 18 to resisto'^ 20j. This ratio should be s~t to equal about one-half of the total voltage swing of the signal across capacitor 19.
_.5 lQ97 ~ 43 The comparator 21 recovers the ra~ digital data from the signal.
The receiver modem 6 further includes a clocking circuit 22 which derives a clock signal from the transition ;; points of the received data. The clocking circuit 22 includes a logic exclusive-or gate 23 having a first input coupled to comparator 21 and a second input coupled to the comparator 21 through a delay element 24. The signal - delay ~ through delay element 24 should approximately be equal to one-half of a bit period. A common means of achieving such delays is by using a digital shift register clocked ~y a fast external clock. The output of the exclusive-or gate 23 is filtered by a narrow-band band pass filter 25. The center frequency of filter 25 is equal to the data rate f, and the figure of merit, Q, of this filter should be - between 20 and 1000. A lower Q is chosen when faster acquistion of the clock is desired. A higher value of Q
is chosen when less jitter in the output clock is desired.
Common means of achieving such filters are the use of crystal filters, LC filters, phase lock loops, or commutating digital filters. The filtered waveform is shaped by comparator 26 to provide a clock signal at terminal 27.
In order to synchronize the clock signal and the received data, the input of a D-type bi-stable multivibrator 28 is coupled to comparator 21 and the clock input of multivibrator is coupled to clock circuit terminal 27. The multivibrator 28 thus provides the synchronized data and the logic complement of the data at output terminals 29 and 30.
In operation, referring now to figure 1 and the example waveforms in figure 2 jointly, the serial NRZ data to be - ~@97743 transmitted is shown by waveform A. When waveform A is integrated by integrator ~, the waveform B in figure 2 results. This waveform will have either a positive slope or a negative slope as long as the integration period is one bit. When the input data includes two or more bits of the same polarity, the integrator limits the output signal after one bit and a signal of zero slope results, as shown by waveform B in figure 2.
The pre-emphasis network in the FM transmitter 3 has the effect of differentiating the integrated waveform thus, the FM signal transmitted is similar to waveform C
of figure 2. The frequency deviation of this signal can be represented by waveform D. The three possible slopes of the input signal B turn into three possible fre~uency deviations:
positive frequency deviation, no frequency deviation, and negative frequency deviation. ~Ihen an FM transmitter 3 has no pre-emphasis network, these waveforms can be produced by inserting an RC differentiating network between the modem section 4 and the transmitter 3.
The output of the FM receiver S at the discriminator equals the instantaneous frequency deviation, thus a three level waveform as shown in figure 2, waveform D, results.
This waveform might have a DC offset voltage which is removed by capacitor 15 and resistor 16. Comparator 21 which has hysteresis converts the three levels of this waveform F into two level binary data waveform G. When the input returns to zero, the comparator 21 does not change state as the hysteresis resistor 20 holds the comparator in its last state. When the input to the comparator 21 turns negative, the comparator 21 changes sta;te. The exact switching points depend on the amount of hysteresis. One possible setting ~7 ~ ~3 i'` .
,~ for the comparator 21 may be that it will switch to a positive output when the signal reaches one-half of its maximum positive amplitude, and ~ha-t the cor,lparator 21 ~- will switch to a negative output when the signal reaches one-half of the maximum negative amplitude.
Each change in the comparator 21 output produces a pulse at the output of the exclusive-or gate 23. The width of this pulse equals the delay o~ delay element 24.
These pulses contain frequency components at, among others, the frequency of the data rate. This frequency component is isolated by band-pass filter 25 and shapea by comparator 26 into a square wave data clock signal. The data clock is used to synchronize the data via a clocked D-type multivibrator 28, thus small variations in the width of the bits are removed by the action of sync~ronizing the data.
The data and the clock are the desired outputs. The data waveform K is a delayed copy of the input data wave~orm A.
The delays are due to the propagation delays of the circuit elements and the FM radio link.
Since the integrator ~ generates a negative slope for a positive input, the data transmitted is the logic complement of waveform A, and the data has to be inverted by the D-type multivibrator 28 in order ~or the output data to be identical with the input data. This in~rersion is achieved by using the invert~d output, Q, cf this logic element 28.
The transmitter sec~ion 4 of the modem to which standard serial NRZ data is applied at terminal 7 consists of an integrator 8 having an operational amplifier 9, resistor 10, and capacitor 11. The output of integrator 8 is limited from reaching the maximum voltage by zener diodes 12 and 13. ~ariable resistor 14 at the output of ; 20 integrator 8 determines the portion of the integrator's -output to be fed to the F~ transmitter 3. Conven-tional FM transmitters include a pre-emphasis network which increases or boosts the high frequencies of the input signal, followed by a modulator. One type of FM transmitter includes a modulator, commonly known as a phase modulator, B in which the pre-emphasis network function is carried out as an inseparable part of the FM modulator. The value of ~o ~\
resistor ~ and capacitor ~ is chosen to allow the integrator ~output to reach the voltage of the zener diodes 12, 13 within the period of one tran~mitted bit. For example, if the data rate is f, the period of one bit is 1/f; resistor ~9~ ~ ~3 has a value of R, capacitor ~ a value of C, the limiting 1~ point of zener diodes 12 and 13 is + Vz and the input data will have a value of f VH when positive and - VH when negative; then the values are chosen so that l/f = R-C-Vz/VH. The data rate f which may be transmitted will depend on the channel bandwidth fb and may be as high as twice the bandwidth fb.
The transmitted data is received by the FM
reseiver 5 which conventionally includes a demodulator or ,0 frequency discriminator circuit followed by a de-emphasis network for voice communication. For data communication in accordance with this invention, the input to the receiver - section 6 of the modem is coupled directly to the frequency discriminator circuit in the receiver 5. The receiver section 6 of the modem first includes two filters, the first having a capacitor 15 and resistor 16 which block any DC
component that may have been superimposed on the signal due to imperfections in the operation of the FM radio link, an~
the second having resistors 17, 18 and capacitor 19 which form a low-pass filter to remove sharp noise pulses that may have been superimposed on the signal due to other imperfections in the operation of the FM radio link. The 15 l6 time constant of capacitor ~ and resistor ~ is chosen to be much 3arger than the duration of one bit. The time constant of resistors 17, 18 and capacitor 19 is chosen to be equal or smaller to the period of one bit. Small variations in the values of ~hese components will h~ve no adverse ef'ects on the operation of this invention. A
cGmparator 21 is coupled to resistor 18 and has an amount of hysteresis determined by t~e ratio of resistor 18 to resisto'^ 20j. This ratio should be s~t to equal about one-half of the total voltage swing of the signal across capacitor 19.
_.5 lQ97 ~ 43 The comparator 21 recovers the ra~ digital data from the signal.
The receiver modem 6 further includes a clocking circuit 22 which derives a clock signal from the transition ;; points of the received data. The clocking circuit 22 includes a logic exclusive-or gate 23 having a first input coupled to comparator 21 and a second input coupled to the comparator 21 through a delay element 24. The signal - delay ~ through delay element 24 should approximately be equal to one-half of a bit period. A common means of achieving such delays is by using a digital shift register clocked ~y a fast external clock. The output of the exclusive-or gate 23 is filtered by a narrow-band band pass filter 25. The center frequency of filter 25 is equal to the data rate f, and the figure of merit, Q, of this filter should be - between 20 and 1000. A lower Q is chosen when faster acquistion of the clock is desired. A higher value of Q
is chosen when less jitter in the output clock is desired.
Common means of achieving such filters are the use of crystal filters, LC filters, phase lock loops, or commutating digital filters. The filtered waveform is shaped by comparator 26 to provide a clock signal at terminal 27.
In order to synchronize the clock signal and the received data, the input of a D-type bi-stable multivibrator 28 is coupled to comparator 21 and the clock input of multivibrator is coupled to clock circuit terminal 27. The multivibrator 28 thus provides the synchronized data and the logic complement of the data at output terminals 29 and 30.
In operation, referring now to figure 1 and the example waveforms in figure 2 jointly, the serial NRZ data to be - ~@97743 transmitted is shown by waveform A. When waveform A is integrated by integrator ~, the waveform B in figure 2 results. This waveform will have either a positive slope or a negative slope as long as the integration period is one bit. When the input data includes two or more bits of the same polarity, the integrator limits the output signal after one bit and a signal of zero slope results, as shown by waveform B in figure 2.
The pre-emphasis network in the FM transmitter 3 has the effect of differentiating the integrated waveform thus, the FM signal transmitted is similar to waveform C
of figure 2. The frequency deviation of this signal can be represented by waveform D. The three possible slopes of the input signal B turn into three possible fre~uency deviations:
positive frequency deviation, no frequency deviation, and negative frequency deviation. ~Ihen an FM transmitter 3 has no pre-emphasis network, these waveforms can be produced by inserting an RC differentiating network between the modem section 4 and the transmitter 3.
The output of the FM receiver S at the discriminator equals the instantaneous frequency deviation, thus a three level waveform as shown in figure 2, waveform D, results.
This waveform might have a DC offset voltage which is removed by capacitor 15 and resistor 16. Comparator 21 which has hysteresis converts the three levels of this waveform F into two level binary data waveform G. When the input returns to zero, the comparator 21 does not change state as the hysteresis resistor 20 holds the comparator in its last state. When the input to the comparator 21 turns negative, the comparator 21 changes sta;te. The exact switching points depend on the amount of hysteresis. One possible setting ~7 ~ ~3 i'` .
,~ for the comparator 21 may be that it will switch to a positive output when the signal reaches one-half of its maximum positive amplitude, and ~ha-t the cor,lparator 21 ~- will switch to a negative output when the signal reaches one-half of the maximum negative amplitude.
Each change in the comparator 21 output produces a pulse at the output of the exclusive-or gate 23. The width of this pulse equals the delay o~ delay element 24.
These pulses contain frequency components at, among others, the frequency of the data rate. This frequency component is isolated by band-pass filter 25 and shapea by comparator 26 into a square wave data clock signal. The data clock is used to synchronize the data via a clocked D-type multivibrator 28, thus small variations in the width of the bits are removed by the action of sync~ronizing the data.
The data and the clock are the desired outputs. The data waveform K is a delayed copy of the input data wave~orm A.
The delays are due to the propagation delays of the circuit elements and the FM radio link.
Since the integrator ~ generates a negative slope for a positive input, the data transmitted is the logic complement of waveform A, and the data has to be inverted by the D-type multivibrator 28 in order ~or the output data to be identical with the input data. This in~rersion is achieved by using the invert~d output, Q, cf this logic element 28.
Claims (7)
1. In a communications system having an FM transmitter and receiver, a modem for the transmitter and receiver comprising:
- a transmitter modem section including integrator means for integrating input binary data having a binary rate F, the integrator means having limiting means for integrating the first binary bit in any sequence of bits having the same polarity and, the integrator means further having an output terminal coupled to the transmitter; and - a receiver modem section including DC filter-means coupled to the receiver for blocking DC in the received receiver signal, comparator means with hysteresis coupled to the filter means for converting the receiver signal to a binary data signal, clock means coupled to the comparator means output for generating à binary clock signal of frequency f, and logic element means having an input coupled to the comparator means and controlled by said binary clock signal to provide an output binary data signal synchronized to the clock signal.
- a transmitter modem section including integrator means for integrating input binary data having a binary rate F, the integrator means having limiting means for integrating the first binary bit in any sequence of bits having the same polarity and, the integrator means further having an output terminal coupled to the transmitter; and - a receiver modem section including DC filter-means coupled to the receiver for blocking DC in the received receiver signal, comparator means with hysteresis coupled to the filter means for converting the receiver signal to a binary data signal, clock means coupled to the comparator means output for generating à binary clock signal of frequency f, and logic element means having an input coupled to the comparator means and controlled by said binary clock signal to provide an output binary data signal synchronized to the clock signal.
2. A modem as claimed in claim 1 wherein the integrator means includes an operational amplifier having an input terminal and an output terminal, a resistor R
serially connected to the input of the operational amplifier, a capacitor C connected between the input terminal and the output terminal of the operational amplifier, and two zener diodes of limiting voltage ? VZ connected in series across the capacitor.
serially connected to the input of the operational amplifier, a capacitor C connected between the input terminal and the output terminal of the operational amplifier, and two zener diodes of limiting voltage ? VZ connected in series across the capacitor.
3. A modem as claimed in claim 2 wherein the bit data rate period l/f = RCVZ/ VH, where VH is the positive or negative amplitude of the data bit.
4. A modem as claimed in claim 1 wherein the clock means includes a delay element coupled to the comparator means, the delay element having a delay period smaller than l/f, exclusive-or gate means having one input coupled to the delay element and a second input coupled to the comparator means, band-pass filter means coupled to the exclusive-or gate means and waveform shaping means coupled to the filter means to provide the binary clock signal.
5. A modem as claimed in claim 4 wherein the delay period of the delay element is approximately l/2f.
6. A modem as claimed in claim 1 wherein the logic element means consists of a bi-stable multivibrator.
7. A modem as claimed in claim 1 wherein the receiver modem section further includes a low pass filter coupled between the DC filter means and the comparator means, the low pass filter having a time constant equal or smaller than l/f.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US82697077A | 1977-08-22 | 1977-08-22 | |
| US826,970 | 1977-08-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1097743A true CA1097743A (en) | 1981-03-17 |
Family
ID=25247976
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA304,794A Expired CA1097743A (en) | 1977-08-22 | 1978-06-05 | Modem for the high speed transmission of binary data over an fm communications system |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS5435608A (en) |
| AU (1) | AU518023B2 (en) |
| CA (1) | CA1097743A (en) |
| DE (1) | DE2833897A1 (en) |
| GB (1) | GB2003367A (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3120761C2 (en) * | 1981-05-25 | 1986-02-13 | Siemens AG, 1000 Berlin und 8000 München | Circuit for the quick detection of FSK signals in a radio channel |
| JPS59123623U (en) * | 1983-02-08 | 1984-08-20 | 株式会社小松製作所 | Charge air cooler control device for supercharged engines |
| DE3313035A1 (en) * | 1983-04-12 | 1984-10-18 | Deutsche Fernsprecher Gesellschaft Mbh Marburg, 3550 Marburg | Method and circuit for transmitting digital information |
| JPS6128712A (en) * | 1984-07-17 | 1986-02-08 | Niigata Eng Co Ltd | Temperature regulating device of supercharged air |
| US4613973A (en) * | 1985-06-20 | 1986-09-23 | Eaton-Kenway, Inc. | Digital data decoder and method |
| US5216605A (en) * | 1990-06-28 | 1993-06-01 | Eaton-Kenway, Inc. | Update marker system for navigation of an automatic guided vehicle |
| US5187664A (en) * | 1990-11-27 | 1993-02-16 | Eaton-Kenway, Inc. | Proportional position-sensing system for an automatic guided vehicle |
| US5281901A (en) | 1990-12-03 | 1994-01-25 | Eaton-Kenway, Inc. | Downward compatible AGV system and methods |
| US5127486A (en) * | 1990-11-23 | 1992-07-07 | Eaton-Kenway, Inc. | System for sensing arrival of an automatic guided vehicle at a wire |
| US5175415A (en) * | 1990-11-27 | 1992-12-29 | Eaton-Kenway, Inc. | Combination drive-wheel mechanism and travel-sensor mechanism |
| US5539646A (en) * | 1993-10-26 | 1996-07-23 | Hk Systems Inc. | Method and apparatus for an AGV inertial table having an angular rate sensor and a voltage controlled oscillator |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3197705A (en) * | 1962-04-25 | 1965-07-27 | Moude Homer H Da | Modulator shaper for frequency shift transmitter |
| US3377560A (en) * | 1964-01-13 | 1968-04-09 | Collins Radio Co | Direct data sample single tone receiver |
| JPS5214124B2 (en) * | 1973-07-05 | 1977-04-19 | ||
| JPS5242310A (en) * | 1975-09-30 | 1977-04-01 | Mitsubishi Electric Corp | Code transmission wireless unit |
-
1978
- 1978-06-05 CA CA304,794A patent/CA1097743A/en not_active Expired
- 1978-08-02 DE DE19782833897 patent/DE2833897A1/en not_active Ceased
- 1978-08-03 JP JP9417378A patent/JPS5435608A/en active Pending
- 1978-08-10 GB GB7832934A patent/GB2003367A/en not_active Withdrawn
- 1978-08-11 AU AU38847/78A patent/AU518023B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| GB2003367A (en) | 1979-03-07 |
| AU3884778A (en) | 1980-02-14 |
| DE2833897A1 (en) | 1979-03-08 |
| AU518023B2 (en) | 1981-09-10 |
| JPS5435608A (en) | 1979-03-15 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |