CA1096034A - Solid state imaging device - Google Patents

Abstract

SOLID STATE IMAGING DEVICE

ABSTRACT OF THE DISCLOSURE
A solid state imaging device capable of converting a one-dimensional or two-dimensional optical information to an electrical signal is disclosed. A
signal charge stored in each photo-electric converter element, which signal charge is in proportion to the amount of incident light, is read into a corresponding stage of a charge transfer device through a switching transistor under the control of a control pulse. The read control pulse is applied through a clock line of the charge transfer device so that the clock line is used both for read-in and for transfer. In this manner, one picture element of a sensor is consisted of one photo-cell and two transistors whereby a high integration density of the solid state imaging device is attained.

Description

~96~391 1 The present invention relates to a solid state imaging device capable oI converting a one-dimensional or two-dimensional optical information to an electrical signal through a semiconductor device.
As a device capable of converting an optical information to an electrical signal and having a self-scan feature, a device has been known which uses a combination of a photo-sensor and a charge transfer device, e.g. BBD, as described, for example, in an article ]0 "Self-Scanned Image Sensor", IE~E ED-18, No. 11 (1971), by Paulk Weimer. As the photo-sensor, a photo-diode or a photo-transistor are used therein. Another device has been known, in which light is directly radia-ted onto a charge transfer array such as CCD array -to per-Eorm -the photo-elec-tric conversion and -the readout in the same array.
In this array, however, since the llght is directed to the charge trarlsfer array eve~ uring the cha~ge trans:Eer, ano-ther charge trans-fer array that is a temporally storage array consisting of as rnany storing charge transfer array as the number of sensing charge transfer array mu3t be separately provided in order to avoid optical distortion in an output signal. Fur-thermore, the number of times of transfer of signal charge required to produce the photo-electric converted output is twice as many as that required in the former device. Therefore, this device has a drawback in that the influence by the transfer efficiency of the charge transfer device to the output i signal is large.
The present invention relates to the former device which requires fewer number of times oE transfer ' ~g6~3~ .

1 of signal charge.
The invertors of the present invention have noted a BBD type solid state imaging device which is easy to manufacture, can be two-phase driven, and can be self-scanned without requiring matrix scan, and have made investigation on this type of device. As an imaging device having a self-scanning feature, a CCD sensor has been proposed, and a frame transfer system in which a transfer device also functions as a sensor has been frequently adopted. The inventors have noted that a plane sensor could be driven at a low clock frequency, e.g., several tens K~Iz and hence the plane sensor could be constituted by a BBD with a PN junct:ion diode which could be manufactured by a simpler process -than and could be driven by a simpler drive circuit than the CCD.
In construct:ing an image sensor o:~` the interl:ine type using a combination of a photo-dlode and ~ a BBD, two lines, that is, a vertical transfer clock ; line and a transversing control line, would be normally required for each bit to perform the read-in of the optical information and the interlace function.
Bearing the above in minds and using -the experience of having developed an audio frequency MOS
BBD driven by a low voltage, the inventors have adopted a unique circuit as a basic element in developing the interline type image sensor and developed a high performance image sensor which requires a reduced number of inter-connections and elements.
The present lnvention will become more apparen-t ~0 in the following detailed descriptlon taken togehter with 3~

1 the accompanying drawings, in which:
Fig. 1 shows a basic arrangement of a solid sta-te imaging device constructed by a photo-sensor and a charge transfer device.
Fig. 2 shows a specific circuit diagram of the basic solid state imaging device constructed by the photo-sensor and the charge transfer device.
Fig. 3 shows a unique control clock pulse pattern for driving the solid state imaging device shown in Fig. 2.
Fig. 4 shows a structure of a solid state imaging d~vice in accordance with one embodiment of the present invention.
~ ig. 5 shows a first embodiment of a major section o~ the solid state imaging device of the present lnvent:ion and illustrates a comblnation circuit of a photo-sensor and a charge -trans~`er device.
Fig. 6 shows a control clock pulse pattern for driving the first embodiment of the present invention.
Fig. 7 shows an embodiment of an output and support circuit o-f the solid state imaging device of the present invention.
~ Fig. 8 shows a plan structure of the first ; embodiment when formed on a semiconductor substrate.
Fig. 9 shows a sectional structure of the first embodiment when formed on the semiconductor substrate.
` Fig. lO(a) shows a pattern of a portion of a sem.iconductor chip of the device shown in Fig. 2.
0 Fig. lO(b) shows a pattern of a portion of . .

1 a semiconductor chip of the device shown in Fig. 5.
Figs. 1 and 2 show the structures of the solid state imaging device which was proposed by the inventors of the present application in DIGEST OF TECH~ICA~ PAPERS, pages 40 and 41, IEEE International Solid-State Conference, February 18, 1976. In the propsed image sensor device, the read-in and the transfer of a signal charge have been improved to construct each cell by three transistors.
In Fig. 1, Dl ~ D4 denote photo-sensors, and (n - 1) ~
(n - 2) denote transfer stages forming a series o~ charge transfer devices. A photo-electric converted signal from the photo-sensor Dl is read in-to the corresponding charge transler stage n-l and sequentially transferred -through the series of charge transfer devices n-l, n, n~l, n~2. Circles in the drawing show gates, in which 101 denot~s a gate for charging the photo-sensor, 102 denotes El gate for reading -the photo-electric conver-ted signal from the photo-sensor into the charge transfer device, and 103 denotes a gate ~or transferring a signal from one charge transfer stage to a suceeding stage.
A feature of the above device lies in that the devices are simultaneously recharged by a power supply through the charge gates which are controlled by clock lines of the respective charge transfer stages ` 25 whereby the numbers of the elements and the interconnections are reduced. The device will now be explained in more detail with reference to Figs. 2 and 3.
Symbols ~1 and ~2 denote transfer clock pulses for controlling the actuation and deactuation of the gates. ~ig. 2 shows a specific circuit embodiment therefor.

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l The operation is su~merized as follows: As shown in Fig. 2, the control lines for the charge gates Ql and Q3 and the control lines for the read gates Q2 and Q4 are common to the trans-fer clock pulses ~l and ~2 for the charge transfer stages, and they are pulsed in a unique drive pulse pattern shown in Fig. 3. In this manner, no separa-te control line -for the charge gates Ql and Q3 and the read gates Q2 and Q4 is required but only two control lines in total are required. Thus, a high integration density is attained in a two-dimensional arrangement of the photo-sensor.
In the above construction o~ the device, however, one photo-diode and three transistors are required per picture element, and the number o~` transistors required has still been a barrier to attain a high integration dens:ity. ~he inventors have constructed a -two-dimensional image sensor oI` 12~ x 12~ picture elements, but a demand for higher integration density has been increasing. Fur-thermore, in the construction o-f Fig. 2, since the devices are charged at the charge clock (transfer clock) ~l and the charge signal is read out at the read clock (transfer clock) ~2~ the s-torage time of the optical image (which corresponds to one field period in a television system) is restricted to a time interval between the charge clock and the read clock.
One of the reasons why a high integration density of the solid state imaging device of this type is that the dimension of an image area depends primarily on a res-triction to a manufacturing and processing '.3LC3~34 1 technique ~or a semiconductor device and a restriction to an aper-ture of a lens used and hence it is a significent factor in improving the quality of an image reproduced by the device to arrange as a number of picture elements within the restricted area.
The present invention provides a highly sensitive and high performance self-scanning sold state imaging device using a basic arrangement which allows the reduc-tion of the number of transistors required per picture element of the device to attain a high integration density of the photo-sensor.
According to the present invention, the number of -transistors per picture element can be reduced by a novel circuit arragement and the photosensors arranged in a two-dimensional matrix can be integrated at a high density. As a resu]t, the opt:ical informat:ion can be stored over a frame period, the optical sensitivity o~
the device can be increased by the factor of two, and the circuit forming the picture element can be simplified, resulting in the enhancement in yield and an overall performance of the device.
Fig. 4 shows one embodiment of a solid state imaging device of the present invention and shows a structure of the device.
A photo-sensor 11 has a photo-electric conversion function and shown as a reverse biased photo-diode. The photo-diode is exposed to an incident light for a given integration (storage) time period and then discharges stored charge in accordance with the arnount of incident light. When it is desired to produce output signals 3~

1 from the device at a standard television rate, the integration time period corresponds to one field or frame scan period of a standard television scan. Herein-after, one frame scan period is referred to as the integration time period. A vertical signal transferring BBD (Bucket Brigade Device) 12 reads in signal charges which have been photo-electric converted by the photo-sensors 11 as shown by solid lines into corresponding positions of the BBD stages during a first field period and then sequentially transfers them to a parallel-to-serial conversion output circuit 13 a line at a time.
The parallel-to-serial conversion output circult 13 for produclng time-serial video output signals may be an analog shift register using BBD or CCD, or a combination circuit of a conventional digi-tal shl:Et register and ~witching gite~,.
In the following second field period, signal charges in photo-sensors llb shown by dotted lines are read into corresponding positions of the BBD stages and then they are sequentially transferred to the parallel-to-serial-conversion output circuit 1~ a line at a time.
In this manner, an interlace scan is carried out for each field period.
~ block 14 sorrounded by a solid rectangle in ~ig. 4 is a principal portion of the present invention and a specific configuration of that portion is explained below.
Fig. 5 shows an equivalent circuit of photo-diodes and BBD constructed by MOS transistors in accordance with a speci~Eic arrangement of the present invention.

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1 In Fig. 5, Tr(n) and ~r(n-~-l) denote transistors forming a vertical signal transferring BBD, and CB(n) and CB(n~l) denote bucket capacitances forming charge transfer stages.
Di and D4 denote photo-diodes for photo-electric conversion, and Q2 and Q4 denote transistors for reading the photo-electric converted signals of the photo-diodes into the eharge transfer stages. ~o drive the line of charge `;
transfer deviees, two-phase clock pulses ~1 and ~2 are supplied to clock lines 20 and 21 of the transistors Tr(n) and Tr(n+l) forming the line of charge transfer devices. Control lines 22 and 23 of the transistors ~2 and Q4 for reading in the photo-electric converted signals from the photo-diodes Dl and D2 are connected in common wi-th -the charge transferring cloek lines 20 and 21, ; 15 respeetively.
~ he operation o:E the photo-sensors and -the vertieal si~nal tran~:Eerr:ing B~D shown in the e~lu:ivalent eireuit O.e Fig. 5 is explained with re:Eerenee to Fig. 6.
Fig. 6 shows an example of pulse pattern for the clock pulses ~1 and ~2 Eor driving the circuit shown in Fig. 5. In the illustrated example of the clock pulse pattern, a sequenee of elock pulses ~p (which occur at 15.75 KHz in a standard television scar~) for driving the vertical signal transferring BBD at a clock pulse voltage Vl is combined with a sequence of control pulses ~R for reading the photo-electric converted signals from the photo-diodes into the vertical signal -transferring BBD at a clock pulse voltage V2. It is normally necessary to meet a relation of V2> Vl. It has been proved by an experiment tha-t a proper operatlon is attained by the ;~ ' , ', ~g~33~

1 combination of D2 = 12V and Vl = 6V, or V2 = 15V and Vl = 8V-When the control pulse ~2 (of the voltage V2)is applied to a gate terminal of the transistor Q2 in ~ig. 5, the transistor Q2 for reading in the photo-electric converted signal is turned on, and the pho-to-diode Dl is reset to a given voltage VR2 which corresponds to the voltage V2 of the control pulse ~R. (Normally, VR2 is equal to V2 - VT, where VT is a threshold voltage of the MOS transistor Q2-) After the control pulse ~R
terminates, the photo-diode Dl remains to be reset at VR2 while the transistor Q2 is turned o-ff and floats.
Under this condition, the photo-diode Dl is exposed -to light for a given time period so that a photo-electric leak current flows from the photo-diode Dl toward a sem:iconductor substrate (GND) resulting in a voltage drop of AV in the photo-cliocle. The magnitude ~V is proportional to the amount o-f incident light to the photo-diode.
When the control pulse ~R is again applied to the gate terminal of the transistor Q2 while the diode voltage is being reduced by ~V~ the circuit operates as follows: A drain terminal 24 of the read transistor Q2 is connected in common with a drain ter~inal of the transistor Tr(n) of the charge transfer stage and it is capacitively coupled to a gate terminal of -the transistor ; Tr(n). As a result, the drain -terminal 24 is pulled up to a high positive potential. Since the charge -transfer is normally carried out during the light exposure period SO by the signal charge transfer clock pulse ~p while a ~:

- .: - :: : . .:
,: . .

~l~99~i~34 1 voltage near Vl is being applied to an input terminal 25 of the ver-tical signal transferring ~BD, the drain terminal 24 has been reset to the given voltage VRl corresponding ..
to the voltage Vl (usually, VRl is equal to Vl-VT, where VT is a threshold voltage of the MOS transistor Tr(n+l) before the control pul.se ~R is applied. Accordingly, when the control pulse ~R is applied to the ga-te terminal of the transistor Q2' the voltage at the drain terminal 24 is pulled up to (VRl + V2) and the charges are exchanged between the drain terminal 24 and the photo-diode Dl.
Namely, because the potential of the photo-diode has been decreased to (VR2 - ~V) by the light exposure, a current flows from the drain te~ninal to the photo-diode. ~s a result, the potent:ial at the drain terminal decreases by approximately ~V ass~ing that the bucket capacitance .is substantially equal to a capacitance O:r the photo-diode Dl to the semiconductor substrate. The ~nount of charge corresponding to the vol-tage ~V is proportional -to the total amount of charge -~lo~n into the semiconductor substrate by the photo-diode Dl through the light exposure .for the given time period.
:When the control pulse ~R terminates, the potential at the drain terminal 24 of the charge transfer stage, that is, the voltage across the bucket capacitance CB, assumes (VRl-~V) so that the photo-electric converted signal can be read into the vertical signal transferring .
BBD by the application of -the control pulse ~R. ~t the same time, by the application of -the control pulse ~R~ the voltage of the photo-diode D~ is again reset to the gi.ven vol-tage VR2 and thus it i.s ready for sensingr - 10 - .

,. - . . ~, . .

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1 next optical information. In this manner, precharging of the diode from the transferring ~BD can be carried out by the application of the control pulse ~R~ A transfer efficiency of the B~D was 99.95% and precharging was carried out without causing a disturbing voltage variation.
The photo-electric converted signals read into the vertical signal transferring ~BD are sequentially transferred to the parallel-to-serial conversion output circuit 13 by a sequence of clock pulses ~p of the pulse voltage Vl which drive the BBD.
In the illustrated embodiment of the present invention, a maximum al]owable photo-elec-tric converted signal ~V max is equal to V2 - Vl. Within -the above range ! the voltage of the photo--diode is always higher than Vl so -that the vol-tage of the photo-diode does not affect, the transfer signa].
While the previous explanation referred only to the case where the control pulse ~R is applied to the gate terminal of the transistor Q2' both clock pulses ~1 and ~2 may be used as shown in Fig. 6, in which case : the c]ock pulse ~R is applied to the gate terminal of the transistor Q4 to enable the interlaced scan of the photo-electric converted signals of the photo-diodes arranged in a matrix.
In Fig. 6~ Tw represents an integration time period during which the optical information is stored in the photo-diodes. In the illustrated e~lbodiment, - it corresponds to one frame period in a standard television scan and it may be 1/~0 seconds, fcr examplc.

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1 The series of operations described above are carried out simultaneously on a plurality of photo-diodes and a plurality of vertical signal transferring ~BD's forming the solid state imaging device.
An embodimellt of the parallel-to-serial conversion output circuit 1~ is now explained. Fig. 7 shows a confi.guration of the parallel-to-serial conversion output signal. Numerals 41 and 42 denote final stages of the vertical signal transferring BBD. The photo-diode 10 circuit of the final stage is omitted in the drawing .
for the purpose of simplification. The photo-electric converted signal at a terminal 46 of the final s-tage of the vertical signa] -transferring B~D i.s transferred to a node 45 by a timin~ gate comprising a transis-tor 4~
; 15 and the control line ~p. The node 45 is coupled to a gate terminal of a parallel output transistor 47, a conductance ol which :is mo(lul.lt~d by the photo-electric converted signal. ~ transistor 44 serves to recharge the voltage at the node 45 to a given voltage by a power supply line ~DD and a control line ~set before the photo-electric converted signal is fed to the node 45 by the timing gate.
The power supply line VDD also functions as a power supply line to the parallel output transistor 47. The photo-electric converted signal at an output node 4~ of the parallel output transistor 47 is transferred to a video output line 52 by an output line 51 of a conventional digital shi:Et registrr 50 and a parallel-to-serial conversion transistor 49. The digital shift ~0 register 50 prod.u.ces a video output at, for e~ample, 9~03~

1 7.3 MHz. The explanation of the circuit of the digital shift register is omitted for the purpose of simplification.
~n output signal from the digital shift register 50 is applied to one of the gate terminals of a plurality of parallel-to-serial conversion transistors as represented by the gate terminal of the parallel-to-serial conversion transistor 49. The output signal from -the digital shift register 50 should be large enough to sequentially turn on the parallel-to-serial conversion transistors. With the arrangements described above, the photo-electric converted signals of the plurality of vertical signal trans:~erring B~D's can be converted into -the time-serial signal on the video outpu-t line 52.
Fig. 8 shows a plain structure of -the circuit arrangement of Fig. 5 when formed on a semiconductor substrate. In Fig. 8, numerals 61, 62 and 63 denote diffusion regions of opposite conductivity type to the semiconductor substrate, which form the transistors Tr(n) and Tr(n~l), and nuMerals 64 and 65 denote diffusion regions of opposit,e conductivity type to the semiconductor substrate, which act as photo-diodes to sense a light.
Numerals 66 and 6'7 denote gate electrodes to which the clock control signals ~1 and ~2 are supplied. The transistors Tr~n) and Tr(n+l) and the transistors Q2 and Q~ shown ` 25 in Fig. 5 are formed in Fig. 8 at the respectively indicated locations between the diffused regions.
Fig. 9 shows a sectional view taken along a chain line V-V' in the plain structure shown in ~ig. 8.
In Fig. 9, numeral 70 denotes a P-type semiconducto-r substrate, and nuMeral 62 denotes an N type diffusion ~603~

1 region which forms a souree or drain region of the charge transfer stage. An N-type diffusion region 64 represents a photo-diode, and numeral 66 denotes a gate electrode to which the control cloek pulses ~1 and ~2 shown in ;~ 5 ~ig. 6 are applied. ~umeral 71 denotes a gate oxide layer of the MOS transistor. A eonduetion ehannel Q2 in Fig. 9 eorresponds to the transistor Q2 in Fig. 5 by whieh the photo-eleetrie eonverted signal from the photo-diode is read into the drain region 62.
In an aetual operating eondition of the structure shown in Figs. 8 and 9, a light shielding mask is disposed sueh that only the photo-diodes are exposed to the light, but sueh mask is omitteA in the drawings for the purpose o-f simpli~ication.
As seen from Figs. 5, 6, 7, 8 and 9, aecording to the preferred embodiments of the present invention, the eontrol lines for the MOS t:rarlslstors Q2 and Q4 for reading the photo-electrie converted signal from the photo-diode into the charge transfer deviee are shared with the clock lines for the charge transfer device and ; a eontrol pulse is additionally provided -for the cloek lines. In this manner, the reeharging of the diode ; ean be aceomplished simultaneously with the read-in of the photo-electric converted signal by the switching MOS
transistor. Accordingly, the device shown in ~ig. 5 can be operated with two clock control lines and one pieture element (sensor) ean be constructed by one diode and two transistors. Thus, the structure is very simplified and a high integration density of the photo-sensors arranged in a matrix is attained. The inventors -- lLI. _ .

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1 have constructed a two-dimensional image sensor of 400 x 320 picture elements using the structure of the present invention.
Fig. lO(a) shows a photograph of a portion of a surface pattern of an image sensor (of 128 x 128 picture elements) constructed in accordance with the basic arrange-ment shown in Fig. 2, and Fig. lO(b) shows a similar picture of an image sensor (having image area o-E 7.2 mm x 14 mm and one pic-ture element area of 22.5 ~m x 35 ~m) of 400 x 320 picture elements constructed in accordance with the present invention. The photograph of Fig. lO(b) was taken for the same area as Fig. lO(a) at the same magnification scale (250 magnifications). It is seen from the comparison of Figs. lO~a) and lO(b) that the present invention allows a higher in-tegration density and reduces the area per picture element to one half ; or less.
Furthermore, according to the present inven-tion, the storage time of the photo-electric conversion can be extended from one field period shown in Fig. 2 (e.g.
1/60 seconds in a standard television scan) to Tw or one frame peri.od shown in Fig. 6 (e.g. 1/30 seconds) and hence the sensitivity of the device can be improved :
by the factor of two.
As described hereinabove, the present invention -provides a two-dimensional image sensor which has a high sensitivity, can be manufactured at a high integration density and can be readily driven. Thus, the present invention has a great contribution to a color solid state imaging device.

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Claims (9)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN
EXCLUSIVE PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED
AS FOLLOWS:

1. A solid state imaging device for converting an optical image to an electrical signal comprising:
photo-electric conversion means including a plurality of photo-sensors for accumulating charge signals corresponding to the optical image for a given time period;
charge transfer means including a plurality of charge transfer devices driven by multi-phase transfer clock signals; and read means connected between said photo-sensors and said charge transfer devices and further connected to at least one of clock lines supplying said multi-phase clock signals for maintaining said photo-sensors at a constant voltage for a predetermined time period by a control pulse supplied from said at least one clock line and simultaneously reading said charge signals into corresponding positions of said charge transfer means, whereby said charge signals read out by said control pulse are transferred by clock signals applied to said clock lines to produce said electrical signal corresponding to the optical image.

2. A solid state imaging device according to Claim 1 wherein said read means are alternately connected to said multi-phase clock lines.

3. A solid state imaging device according to Claim 1 wherein an amplitude of said control pulse is larger than an amplitude of said transfer clock signal.

4. A solid state imaging device according to Claim 2 wherein said charge transfer means comprises BBD's.

5. A solid state imaging device according to Claim 1 wherein said photo-sensors comprise photo-diodes built in a semiconductor substrate, and said read means comprise switching transistors built in said semiconductor substrate and having gate electrodes thereof connected to said clock line.

6. A solid state imaging device according to Claim 5 wherein said transistors are MOS transistors.

7. A solid state imaging device for converting a two-dimensional optical image to a sequential electrical signal to provide a video signal comprising:
photo-electric conversion means including photo-sensors for accumulating charge signals corresponding to said optical image for a given time period;
multi-line vertical transfer means for transferring said charge signals a line at a time at a first phase of a multi-phase transfer clock signal;
switching means connected between said photo-sensors and charge transfer devices forming said vertical transfer means and having gate electrodes thereof connected to at least one of clock lines supplying said first phase transfer clock signal, for maintaining said photo-sensors at a constant voltage for a predetermined time period by a control pulse applied to said clock line at a given interval, said control pulse having a larger amplitude than that of said first phase transfer clock signal, and simultaneously reading said charge signals into corresponding positions of said vertical transfer means; and parallel-to-serial conversion means for transferring the charge signal transferred from said vertical transfer means at a second phase of said transfer clock during an output period to produce said video signal.

8. A solid state imaging device according to Claim 7 wherein said vertical transfer means comprises two-phase driven BBD's and the gate electrodes of said switching means are alternately connected to two-phase clock lines.

9. A solid state imaging device according to Claim 7 wherein said control pulses are applied to respective one of said clock lines for each frame period with the control pulses being offset by one field to each other.