CA1091809A - Combinatorial logic circuit - Google Patents
Combinatorial logic circuitInfo
- Publication number
- CA1091809A CA1091809A CA295,797A CA295797A CA1091809A CA 1091809 A CA1091809 A CA 1091809A CA 295797 A CA295797 A CA 295797A CA 1091809 A CA1091809 A CA 1091809A
- Authority
- CA
- Canada
- Prior art keywords
- circuit
- segments
- word
- words
- bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/607—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers number-of-ones counters, i.e. devices for counting the number of input lines set to ONE among a plurality of input lines, also called bit counters or parallel counters
Landscapes
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Mathematical Optimization (AREA)
- Mathematical Analysis (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- Pure & Applied Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Logic Circuits (AREA)
- Image Processing (AREA)
Abstract
COMBINATORIAL LOGIC CIRCUIT
Abstract of the Disclosure The numbers of gates necessary in an integrated combinatorial logic circuit is reduced by designing the circuit to accept an applied binary word of given length as a plurality of word segments having numbers of bits which add up to the number included in the applied word. A
preprocessor responds to the word segments to generate a word characterizing the segments and to apply those words to an arithmetic logic unit designed to add binary words and to generate words having lengths of the applied words.
Abstract of the Disclosure The numbers of gates necessary in an integrated combinatorial logic circuit is reduced by designing the circuit to accept an applied binary word of given length as a plurality of word segments having numbers of bits which add up to the number included in the applied word. A
preprocessor responds to the word segments to generate a word characterizing the segments and to apply those words to an arithmetic logic unit designed to add binary words and to generate words having lengths of the applied words.
Description
~091809 Field of the Invention -This invention relates to logic circuits and more particularly to such circuits intended for implementation by integrated circuit technology.
Ba~Lound of the Invention The implementation of even a noncomplex logic circuit in integrated circuit technology is made difficult - because the number of gates required for the implementation increases exponentially with the number of bits in a word which the circuit is designed to accept. Thus, for example, a four-bit word in a "count ones" operation includes six - ways in which two ones can occur, four ways to have three or one, and one way to have zero or four for a total of sixteen or 24 combinations requiring sixteen gates. For an eight-bit word, on the other hand, there are 28 or two hundred and fifty-six ~ombinations requiring an equal number of gates.
~,; It is well known that integrated circuit processing . i8 difficult and that the yield from such processing deter-mines the cost of the circuits. Certainly any expedient , q ~ 20 which allows the realization of any desired circuit function -~ with fewer elements would obviously permit the function to ~-~ be implementea with higher yields and thu~ lower costs.
. ;,........................................ .
: Brief Description of the Invention The present invention is based on the realization ,:
that a circuit designed for response to say eight-bit words ` may be made with relatively few elements by accepting those : .
words as, for example, two four-bit segments. The logic circuit to which each such segment is applied need have only a~bout thirty transistors or sixteen gates rather than four hundred and eighty transistors for the expected two hundred `!' and sixty-six gates.
~B
109~8~9 The word ~egments are applied to a preprocessing or preprocessor circuit, operative as a plurality of combinatorial counter circuits. In one embodiment, each counter generates say a three-bit word characterizing the number of binary ones in the associated word segment. Each counter circuit may be operative to add one zero to each three-bit word applying the resulting four-bit words to an - adder circuit conveniently included within an arithmetic logic unit tALU) identical to one to which each of the original eight-bit words is applied in a typical prior art system.
The preprocessing circuit for each word segment can be seen to require about thirty transistors in an illustrative count ones circuit. This leads to a total of ~ixty transistors, a 5avings of one hundred and ~inety-six ~ transistors. An obvious simplification in circuit complexity '' results.
In circuits for use with inputs having more than eight bits, the preprocessor circuit may be adapted to receive more than two word segments. Even portions of the ALU itself may be employed in the preprocessor operation.
In accordance with an aspect of the invention there is provided a circuit arrangement including first circuit means for adding binary words together and second circuit means responsive to external signals representative of an x-bit binary word for applying first and second binary words to said arrangement, said second circuit means comprising a ,. .
preprocessor circuit including means responsive to segments of each of said x-bit words for generating output words representative of a characteristic binary digit pattern in each of said segments, said output words having a number of :,, ,:-"' ,;- ~
bits equal to the number in the segment having the greatest number of bits, said preprocessor circuit being adapted to apply said output words to said adder.
_ief Description of the Drawing PIG. 1 is a schematic block diagram of a circuit arrangement for an illustrative count ones circuit in accordance with this invention; and FIG. 2 is a schematic circuit diagram of the logic gating circuit for a portion of the preprocessor circuit of the arrangement of FIG. 1.
Detailed Description FIG. 1 shows a block diagram of an illustrative count ones circuit 10 in accordance with one embodiment of this invention. The circuit comprises a preprocessor circuit 11 and an adder 12, defined in an integrated circuit chip IC. Circuit 12 is adapted conveniently for applying outputs to a memory represented by block 13.
Circuit 10 is operative under the control of control circuit 14 to count the number of ones in an eight-,: ., bit word. The eight bits of each such word are applied toinput leads 15A, to 15H by conventional apparatus (not shown) - well understood in the art. It is to be noted particularly - that the input leads are organized into two groups of four, 15A through 15D and 15E through 15H, which are connected to counter circuits 16A and 16B of preprocessor circuit 11, respectively.
Each of counter circuits 16A and 16B include thirty transistors organized as a standard logic block to provide binary weighted outputs indicative of the number of ones in the associated segment. Specifically, each word segment of four bits is applied to such a four-bit counter circuit which :; ~
~091809 responds to provide an output representative of the number of ones in the segment.
FIG. 2 is a diagram of a four-bit binary counter uqeful as counter circuit 16A or 16B of FIG. 1. The circuit includes thirty transistors responsive, for example, to four inputs applied to the gates of the thirty transistors. The transistors are organized to respond to the inputs to produce a binary output on leads 23, 24, and 25 of FIG.- 2 as shown.
These outputs are applied to adder 12 of FIG. 1.
The organization of the transistors of FIG. 2 reflects the various ways in which binary ones can occur at the input (gates) to transistors 15A, 15B, 15C, and 15D.
These input gates in FIG. 2 are also designated by the ; binary values 0, 1, 2, and 3 for convenience. The output leads 23, 24, and 25 of the counter are similarly designated bit 0, bit 1, and bit 2.
The source of each one of transistors 15A, 15B, 15C and 15D is connected to the drain of the next adjacent one of the txansistors as shown, the entirety being connected electrically in series between a reference potential, shown as ground, and the drain electrode of a P channel transistor 26. The source of transistor 26 also is connected to a power supply shown as Vs in the figure, the gate thereof being connected to ground. The drain of transistor 26 is connected by output lead 23.
; The drain of transistor 30 is similarly connected .~:
/ to output lçad 24 and to ground through an arrangement of ', transistor pairs connected to reflect the six ways in which ;, two ones can occur at the input gates thereto. Thus, eight ~; 30 transistors are connected between a reference potential and ` the source of transistor 30 in pairs. The transistors can be seen to be connected source to drain in pairs to define ''~
B
- ~09~809 four obvious parallel paths which can be seen actually to comprise six paths because of the inclusion of electrical short circuit 31. The transistors are designated by the logic value applied to the gates thereof and corresponding to thosè applied to the gates of transistors 15A, 15B, 15C, and 15D. Thus, the pairs can be seen to correspond to logic inputs 0-2, 1-3, 0-1, 2-3, expanded to 0-3 and 2-1 because of the inclusi~n of short circuit 31. The drai~s of the transistors of these pairs are connected to the drain of transistor 30 via a transistor 33. The gate of transistor 33 is connected to the drain of transistor 15A as shown at node 35.
A similar arrangement exists at the output corresponding to bit 0 as shown in the figure. The output lead 25, on which bit 0 occurs, is connected to the drain of a transistor 40. The drain of transistor 40 also is connected ~o the drains of four transistors which are shown in the figure connected electrically in parallel to ground. The four transistors are designated only by the representations 0, 1, 2, 3 corresponding to the logic input, the gates thereof being connected to the inputs of transistors 15A, 15B, 15C, and 15D, respectively. As can be seen from the figure the drains of the four transistors are connected to the drain of transistor 40 via a series arrangement of transistorq 41 and 42. The gates of transistors 41 and 42 are connected to the drain of transistors 33 and 15A, respectively.
A final arrangement of eight transistors comprises a parallel arrangement of four paths connected between the ; , drain of transistor 41 and ground. The transistors are again designated by the logic input thereto showing the relationship with transistors 15A, 15B, ~sC, and 15D.
In practice, all the transistors are N channel MOS
., ' ~
109~809 de~ices except for transistors 26, 30, and 40 which are P
channel MOS devices.
In operations, a four-bit word is applied to the ga1:es of the thirty transistors of FIG. 2. If four ones occur in the word, node 35 is grounded because transistors 15A, 15B, 15C, and 15D are made conducting. The grounding of node 35 causes the gates of transistors 33 and 42 to be grounded. Thus, nodes 45 and 46 are high. The adder to which these signals are applied interpret "high" as a 0 and "low" as a 1. This leads to 1-0-0 for bits 2, l, and 0, respectively.
If the inputs to the gates include only two ones in any of the six possible ways mentioned hereinbefore, the parallel arrangement of transistor pairs connected between transi~tor 30 and ground via transistor 33 provides a path to ground. The occurrence of only two ones insures that node 35 is high and transistors 33 and 42 are conducting.
The occurrence of two ones also ensures that the sources of transistors 33 and 41 are grounded. Thus, nodes 35, 45, and 46 are high, low and high, respectively, the last condition being due to the fact that the gate of transistor 41 is grounded because of the low voltage condition at node 45.
;; .
The outputs for bits 2, 1, and 0, are thus 0-l-0, respectively, due to the interpretation given these outputs by the adder.
; If three ones occur in the applied four-bit word, the sources of transistors 33, 41, and 42 are grounded. The t .
grounding of the sources of transistors 33 and 41 is due to the occurrence of two ones and one one, respectively, as ~; 30 described hereinbefore. The source of transistor 42 is :
grounded due to the low resistance path, defined by the :,: r ' '~ ' ,;' 109~809 occurence of three ones in the word, through the arrangement of eight transistors connecting that source to ground as already described.
The occurence of three ones results in node 35 be!ing high, thus activating transistors 33 and 42. But the sources of transistors 33 and 42 are grounded. Thus, a low voltage appears on the drains of transistor 33 and 42. As above, the resulting outputs are 0-1-1.
It should be clear at this juncture that a thirty 10 transistor arrangement is operative to count the number of ones in a four-bit word applied thereto and to apply a three-bit output representative of that number to adder 12 of FIG. 1. T~o such arrangements thus are capable of pro-cessing two four-bit words with only sixty transistors thus permitting the 3àvings of almost tw9 hundred transi8tors as stated hereinbe~ore.
, A dummy ~it 3 output lead 47 may be provided if it is desire~ to apply a four-bit word to adder 12. In this instance, adder 12 may comprise a four-bit adder. Three- or 20 four-bit adders are well known in the art and are not discussed further herein. The 1973 Texas Instrument TTL Data - Book for Design Engineers, on page 390, shows a block diagram of a circuit including a processor and an adder, the ~. ~
latter being useful in the embodiment of FIG. 1.
In the case where adder 12 is a three-bit adder, it is adapted to provide an additional five zeros so that an eight-bit output is provided at 40 in FIG. 1. In the case where preprocessor adds one zero to provide two four-bit Y words to adder 12, the adder is adapted to add four zeros to ~, .
. ., ;` 30 its output. The output of the adder thus comprises a word having the same number of bits as the word app}ied, in ~ B
segments, to preprocessor circuit 11.
Memory 13 is conveniently adapted for accepting eight-bit words for storage in conventional fashion.
In general then, it should be clear at this juncture that a count ones operation can be carried out on an x-bit word by applying the word in a plurality of segments of y ~ x and y - x bits to a plurality of combinatorial logic circuits designed to recéive words having lesser numbers of bits and by applying the outputs of those logic circuits to an adder which adds zeros to produce output words of desired ~ ;
length.
Although the illustrative example was described in terms of two segments with equal numbers of bits, more than ~
two segments can be employed and the numbers in the segments ;, can differ. Circuits 16A and 16B o preprocessor circuit 11, in such instances, may be adapted to supplement outputs therefrom by diferent numbers of zeros to apply words with ., ~'' like numbers of bits to adder 12.
;i, Circuit arrangements of the type illustrated are ~ ~"~ .
most convenient in system organizations already including ,~, arithmetic logic units useful for other types of operations.
i In such a case, the adder may be a portion of such a unit.
- In fact, the unit may be adapted to provide for example the . .
r- addition function of the preprocessor circuit itself as -; should be clear to one skilled in the art from the discussion .... .
of the figures hereinbefore. In a system operative to - provide any one of a number of operations of which a count . ,.
ones operation is one, transistors 50, 51, and 52 of FIG. 2 ~,~ are provided ~alternative to the ground connections shown) : :-..:.
, 30 under the control of control circuit 14 of FIG. 1 for ;,, .
selecting the count ones operation. The transistors and the ':
.~ .
,:. ~
~09~809 connections thereof are shown is phantom to indicate an alternative design. In a system where a separate adder is provided, the adder typically requires about thirty tran-sistors per bit. For a three bit system, still a savings of over one hundred transistors is achieved.
What has been described is considered merely illustrative of the principle of this invention. Therefore, various modifications thereof may be devised by those skilled in the art in accordance with those principles within the - 10 spirit and scope of the invention as encompassed by the following claims.
, , .
.
..'~
'','`; :
: .
: '''' ~' ':.
:-, _ 9 _ '~'
Ba~Lound of the Invention The implementation of even a noncomplex logic circuit in integrated circuit technology is made difficult - because the number of gates required for the implementation increases exponentially with the number of bits in a word which the circuit is designed to accept. Thus, for example, a four-bit word in a "count ones" operation includes six - ways in which two ones can occur, four ways to have three or one, and one way to have zero or four for a total of sixteen or 24 combinations requiring sixteen gates. For an eight-bit word, on the other hand, there are 28 or two hundred and fifty-six ~ombinations requiring an equal number of gates.
~,; It is well known that integrated circuit processing . i8 difficult and that the yield from such processing deter-mines the cost of the circuits. Certainly any expedient , q ~ 20 which allows the realization of any desired circuit function -~ with fewer elements would obviously permit the function to ~-~ be implementea with higher yields and thu~ lower costs.
. ;,........................................ .
: Brief Description of the Invention The present invention is based on the realization ,:
that a circuit designed for response to say eight-bit words ` may be made with relatively few elements by accepting those : .
words as, for example, two four-bit segments. The logic circuit to which each such segment is applied need have only a~bout thirty transistors or sixteen gates rather than four hundred and eighty transistors for the expected two hundred `!' and sixty-six gates.
~B
109~8~9 The word ~egments are applied to a preprocessing or preprocessor circuit, operative as a plurality of combinatorial counter circuits. In one embodiment, each counter generates say a three-bit word characterizing the number of binary ones in the associated word segment. Each counter circuit may be operative to add one zero to each three-bit word applying the resulting four-bit words to an - adder circuit conveniently included within an arithmetic logic unit tALU) identical to one to which each of the original eight-bit words is applied in a typical prior art system.
The preprocessing circuit for each word segment can be seen to require about thirty transistors in an illustrative count ones circuit. This leads to a total of ~ixty transistors, a 5avings of one hundred and ~inety-six ~ transistors. An obvious simplification in circuit complexity '' results.
In circuits for use with inputs having more than eight bits, the preprocessor circuit may be adapted to receive more than two word segments. Even portions of the ALU itself may be employed in the preprocessor operation.
In accordance with an aspect of the invention there is provided a circuit arrangement including first circuit means for adding binary words together and second circuit means responsive to external signals representative of an x-bit binary word for applying first and second binary words to said arrangement, said second circuit means comprising a ,. .
preprocessor circuit including means responsive to segments of each of said x-bit words for generating output words representative of a characteristic binary digit pattern in each of said segments, said output words having a number of :,, ,:-"' ,;- ~
bits equal to the number in the segment having the greatest number of bits, said preprocessor circuit being adapted to apply said output words to said adder.
_ief Description of the Drawing PIG. 1 is a schematic block diagram of a circuit arrangement for an illustrative count ones circuit in accordance with this invention; and FIG. 2 is a schematic circuit diagram of the logic gating circuit for a portion of the preprocessor circuit of the arrangement of FIG. 1.
Detailed Description FIG. 1 shows a block diagram of an illustrative count ones circuit 10 in accordance with one embodiment of this invention. The circuit comprises a preprocessor circuit 11 and an adder 12, defined in an integrated circuit chip IC. Circuit 12 is adapted conveniently for applying outputs to a memory represented by block 13.
Circuit 10 is operative under the control of control circuit 14 to count the number of ones in an eight-,: ., bit word. The eight bits of each such word are applied toinput leads 15A, to 15H by conventional apparatus (not shown) - well understood in the art. It is to be noted particularly - that the input leads are organized into two groups of four, 15A through 15D and 15E through 15H, which are connected to counter circuits 16A and 16B of preprocessor circuit 11, respectively.
Each of counter circuits 16A and 16B include thirty transistors organized as a standard logic block to provide binary weighted outputs indicative of the number of ones in the associated segment. Specifically, each word segment of four bits is applied to such a four-bit counter circuit which :; ~
~091809 responds to provide an output representative of the number of ones in the segment.
FIG. 2 is a diagram of a four-bit binary counter uqeful as counter circuit 16A or 16B of FIG. 1. The circuit includes thirty transistors responsive, for example, to four inputs applied to the gates of the thirty transistors. The transistors are organized to respond to the inputs to produce a binary output on leads 23, 24, and 25 of FIG.- 2 as shown.
These outputs are applied to adder 12 of FIG. 1.
The organization of the transistors of FIG. 2 reflects the various ways in which binary ones can occur at the input (gates) to transistors 15A, 15B, 15C, and 15D.
These input gates in FIG. 2 are also designated by the ; binary values 0, 1, 2, and 3 for convenience. The output leads 23, 24, and 25 of the counter are similarly designated bit 0, bit 1, and bit 2.
The source of each one of transistors 15A, 15B, 15C and 15D is connected to the drain of the next adjacent one of the txansistors as shown, the entirety being connected electrically in series between a reference potential, shown as ground, and the drain electrode of a P channel transistor 26. The source of transistor 26 also is connected to a power supply shown as Vs in the figure, the gate thereof being connected to ground. The drain of transistor 26 is connected by output lead 23.
; The drain of transistor 30 is similarly connected .~:
/ to output lçad 24 and to ground through an arrangement of ', transistor pairs connected to reflect the six ways in which ;, two ones can occur at the input gates thereto. Thus, eight ~; 30 transistors are connected between a reference potential and ` the source of transistor 30 in pairs. The transistors can be seen to be connected source to drain in pairs to define ''~
B
- ~09~809 four obvious parallel paths which can be seen actually to comprise six paths because of the inclusion of electrical short circuit 31. The transistors are designated by the logic value applied to the gates thereof and corresponding to thosè applied to the gates of transistors 15A, 15B, 15C, and 15D. Thus, the pairs can be seen to correspond to logic inputs 0-2, 1-3, 0-1, 2-3, expanded to 0-3 and 2-1 because of the inclusi~n of short circuit 31. The drai~s of the transistors of these pairs are connected to the drain of transistor 30 via a transistor 33. The gate of transistor 33 is connected to the drain of transistor 15A as shown at node 35.
A similar arrangement exists at the output corresponding to bit 0 as shown in the figure. The output lead 25, on which bit 0 occurs, is connected to the drain of a transistor 40. The drain of transistor 40 also is connected ~o the drains of four transistors which are shown in the figure connected electrically in parallel to ground. The four transistors are designated only by the representations 0, 1, 2, 3 corresponding to the logic input, the gates thereof being connected to the inputs of transistors 15A, 15B, 15C, and 15D, respectively. As can be seen from the figure the drains of the four transistors are connected to the drain of transistor 40 via a series arrangement of transistorq 41 and 42. The gates of transistors 41 and 42 are connected to the drain of transistors 33 and 15A, respectively.
A final arrangement of eight transistors comprises a parallel arrangement of four paths connected between the ; , drain of transistor 41 and ground. The transistors are again designated by the logic input thereto showing the relationship with transistors 15A, 15B, ~sC, and 15D.
In practice, all the transistors are N channel MOS
., ' ~
109~809 de~ices except for transistors 26, 30, and 40 which are P
channel MOS devices.
In operations, a four-bit word is applied to the ga1:es of the thirty transistors of FIG. 2. If four ones occur in the word, node 35 is grounded because transistors 15A, 15B, 15C, and 15D are made conducting. The grounding of node 35 causes the gates of transistors 33 and 42 to be grounded. Thus, nodes 45 and 46 are high. The adder to which these signals are applied interpret "high" as a 0 and "low" as a 1. This leads to 1-0-0 for bits 2, l, and 0, respectively.
If the inputs to the gates include only two ones in any of the six possible ways mentioned hereinbefore, the parallel arrangement of transistor pairs connected between transi~tor 30 and ground via transistor 33 provides a path to ground. The occurrence of only two ones insures that node 35 is high and transistors 33 and 42 are conducting.
The occurrence of two ones also ensures that the sources of transistors 33 and 41 are grounded. Thus, nodes 35, 45, and 46 are high, low and high, respectively, the last condition being due to the fact that the gate of transistor 41 is grounded because of the low voltage condition at node 45.
;; .
The outputs for bits 2, 1, and 0, are thus 0-l-0, respectively, due to the interpretation given these outputs by the adder.
; If three ones occur in the applied four-bit word, the sources of transistors 33, 41, and 42 are grounded. The t .
grounding of the sources of transistors 33 and 41 is due to the occurrence of two ones and one one, respectively, as ~; 30 described hereinbefore. The source of transistor 42 is :
grounded due to the low resistance path, defined by the :,: r ' '~ ' ,;' 109~809 occurence of three ones in the word, through the arrangement of eight transistors connecting that source to ground as already described.
The occurence of three ones results in node 35 be!ing high, thus activating transistors 33 and 42. But the sources of transistors 33 and 42 are grounded. Thus, a low voltage appears on the drains of transistor 33 and 42. As above, the resulting outputs are 0-1-1.
It should be clear at this juncture that a thirty 10 transistor arrangement is operative to count the number of ones in a four-bit word applied thereto and to apply a three-bit output representative of that number to adder 12 of FIG. 1. T~o such arrangements thus are capable of pro-cessing two four-bit words with only sixty transistors thus permitting the 3àvings of almost tw9 hundred transi8tors as stated hereinbe~ore.
, A dummy ~it 3 output lead 47 may be provided if it is desire~ to apply a four-bit word to adder 12. In this instance, adder 12 may comprise a four-bit adder. Three- or 20 four-bit adders are well known in the art and are not discussed further herein. The 1973 Texas Instrument TTL Data - Book for Design Engineers, on page 390, shows a block diagram of a circuit including a processor and an adder, the ~. ~
latter being useful in the embodiment of FIG. 1.
In the case where adder 12 is a three-bit adder, it is adapted to provide an additional five zeros so that an eight-bit output is provided at 40 in FIG. 1. In the case where preprocessor adds one zero to provide two four-bit Y words to adder 12, the adder is adapted to add four zeros to ~, .
. ., ;` 30 its output. The output of the adder thus comprises a word having the same number of bits as the word app}ied, in ~ B
segments, to preprocessor circuit 11.
Memory 13 is conveniently adapted for accepting eight-bit words for storage in conventional fashion.
In general then, it should be clear at this juncture that a count ones operation can be carried out on an x-bit word by applying the word in a plurality of segments of y ~ x and y - x bits to a plurality of combinatorial logic circuits designed to recéive words having lesser numbers of bits and by applying the outputs of those logic circuits to an adder which adds zeros to produce output words of desired ~ ;
length.
Although the illustrative example was described in terms of two segments with equal numbers of bits, more than ~
two segments can be employed and the numbers in the segments ;, can differ. Circuits 16A and 16B o preprocessor circuit 11, in such instances, may be adapted to supplement outputs therefrom by diferent numbers of zeros to apply words with ., ~'' like numbers of bits to adder 12.
;i, Circuit arrangements of the type illustrated are ~ ~"~ .
most convenient in system organizations already including ,~, arithmetic logic units useful for other types of operations.
i In such a case, the adder may be a portion of such a unit.
- In fact, the unit may be adapted to provide for example the . .
r- addition function of the preprocessor circuit itself as -; should be clear to one skilled in the art from the discussion .... .
of the figures hereinbefore. In a system operative to - provide any one of a number of operations of which a count . ,.
ones operation is one, transistors 50, 51, and 52 of FIG. 2 ~,~ are provided ~alternative to the ground connections shown) : :-..:.
, 30 under the control of control circuit 14 of FIG. 1 for ;,, .
selecting the count ones operation. The transistors and the ':
.~ .
,:. ~
~09~809 connections thereof are shown is phantom to indicate an alternative design. In a system where a separate adder is provided, the adder typically requires about thirty tran-sistors per bit. For a three bit system, still a savings of over one hundred transistors is achieved.
What has been described is considered merely illustrative of the principle of this invention. Therefore, various modifications thereof may be devised by those skilled in the art in accordance with those principles within the - 10 spirit and scope of the invention as encompassed by the following claims.
, , .
.
..'~
'','`; :
: .
: '''' ~' ':.
:-, _ 9 _ '~'
Claims (7)
1. A circuit arrangement including first circuit means for adding binary words together and second circuit means responsive to external signals representative of an x-bit binary word for applying first and second binary words to said arrangement, said second circuit means comprising a preprocessor circuit including means responsive to segments of each of said x-bit words for generating output words representative of a characteristic binary digit pattern in each of said segments, said output words having a number of bits equal to the number in the segment having the greatest number of bits, said preprocessor circuit being adapted to apply said output words to said adder.
2. A circuit arrangement in accordance with claim 1 defined in an integrated circuit chip wherein said preprocessor circuit includes first and second counter circuits adapted to receive y < x and x - y bit segments of said x-bit word, respectively.
3. A circuit arrangement in accordance with claim 2 wherein x = 2y.
4. A circuit arrangement in accordance with claim 3 wherein each of said counter circuits comprises means for adding a zero to the output thereof.
5. A circuit arrangement in accordance with claim 4 wherein said adder is adapted to add zeros to the output thereof in a manner to provide an x-bit output.
6. A circuit arrangement in accordance with claim 3 wherein said means responsive to segments is operative to generate output words representative of the number of binary ones in each of said segments.
7. A circuit arrangement including first circuit means for adding together binary word segments of greater than three bits and second circuit means responsive to a single set of external signals representative of a first x ? 8 bit binary word for applying to said arrangement said first and second binary word segments, said second circuit means comprising a preprocessor circuit including means responsive to said word segments for generating output words representative of a characteristic digit pattern in each of said segments, said output words having a number of bits at least equal to the number in the one of said word segments having the greatest number of bits, said preprocessor circuit being adapted to apply said output word segments, to said first circuit means.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US78097677A | 1977-03-24 | 1977-03-24 | |
| US780,976 | 1977-03-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1091809A true CA1091809A (en) | 1980-12-16 |
Family
ID=25121265
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA295,797A Expired CA1091809A (en) | 1977-03-24 | 1978-01-27 | Combinatorial logic circuit |
Country Status (10)
| Country | Link |
|---|---|
| JP (1) | JPS53118359A (en) |
| AU (1) | AU519782B2 (en) |
| BE (1) | BE865184A (en) |
| CA (1) | CA1091809A (en) |
| DE (1) | DE2811947A1 (en) |
| ES (1) | ES468136A1 (en) |
| FR (1) | FR2385146A1 (en) |
| GB (1) | GB1597089A (en) |
| IT (1) | IT1156932B (en) |
| NL (1) | NL7803055A (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3634658A (en) * | 1970-03-19 | 1972-01-11 | Sperry Rand Corp | Parallel bit counter |
| US3711692A (en) * | 1971-03-15 | 1973-01-16 | Goodyear Aerospace Corp | Determination of number of ones in a data field by addition |
-
1978
- 1978-01-27 CA CA295,797A patent/CA1091809A/en not_active Expired
- 1978-03-18 DE DE19782811947 patent/DE2811947A1/en not_active Ceased
- 1978-03-20 FR FR7807973A patent/FR2385146A1/en active Pending
- 1978-03-21 NL NL7803055A patent/NL7803055A/en not_active Application Discontinuation
- 1978-03-21 AU AU34361/78A patent/AU519782B2/en not_active Expired
- 1978-03-22 ES ES468136A patent/ES468136A1/en not_active Expired
- 1978-03-22 BE BE186175A patent/BE865184A/en not_active IP Right Cessation
- 1978-03-22 GB GB11481/78A patent/GB1597089A/en not_active Expired
- 1978-03-23 IT IT67652/78A patent/IT1156932B/en active
- 1978-03-24 JP JP3320278A patent/JPS53118359A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| FR2385146A1 (en) | 1978-10-20 |
| JPS53118359A (en) | 1978-10-16 |
| IT1156932B (en) | 1987-02-04 |
| IT7867652A0 (en) | 1978-03-23 |
| GB1597089A (en) | 1981-09-03 |
| NL7803055A (en) | 1978-09-26 |
| AU3436178A (en) | 1979-09-27 |
| AU519782B2 (en) | 1981-12-24 |
| ES468136A1 (en) | 1979-01-01 |
| BE865184A (en) | 1978-07-17 |
| DE2811947A1 (en) | 1978-10-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4189716A (en) | Circuit for determining the number of ones in a binary signal | |
| US5095523A (en) | Signal processor including programmable logic unit formed of individually controllable output bit producing sections | |
| US4694391A (en) | Compressed control decoder for microprocessor system | |
| EP0011374A1 (en) | Execution unit for data processor using segmented bus structure | |
| US4425623A (en) | Lookahead carry circuit apparatus | |
| US4369500A (en) | High speed NXM bit digital, repeated addition type multiplying circuit | |
| US4422143A (en) | Microprocessor ALU with absolute value function | |
| US4208728A (en) | Programable logic array | |
| JPS60157334A (en) | Logic circuit | |
| US4417314A (en) | Parallel operating mode arithmetic logic unit apparatus | |
| EP0227427B1 (en) | Method of and circuit for generating bit-order modified binary signals | |
| US3576984A (en) | Multifunction logic network | |
| EP0098692A2 (en) | Apparatus for adding first and second binary operands | |
| US4280190A (en) | Incrementer/decrementer circuit | |
| CA1229172A (en) | Logic adder circuit | |
| US4306163A (en) | Programmable single chip MOS computer | |
| CA1091809A (en) | Combinatorial logic circuit | |
| US7024445B2 (en) | Method and apparatus for use in booth-encoded multiplication | |
| GB1312791A (en) | Arithmetic and logical units | |
| US4231024A (en) | Device for a digital arithmetic processing apparatus | |
| EP0707261B1 (en) | High speed dynamic binary incrementer | |
| US20040172497A1 (en) | Address decoding method and related apparatus by comparing mutually exclusive bit-patterns of addresses | |
| US5146424A (en) | Digital adder having a high-speed low-capacitance carry bypass signal path | |
| EP0166523B1 (en) | Mask signal generator | |
| EP0302764B1 (en) | Circuit for comparing magnitudes of binary signals |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |