CA1079820A - Master slave flip-flop circuit - Google Patents
Master slave flip-flop circuitInfo
- Publication number
- CA1079820A CA1079820A CA270,682A CA270682A CA1079820A CA 1079820 A CA1079820 A CA 1079820A CA 270682 A CA270682 A CA 270682A CA 1079820 A CA1079820 A CA 1079820A
- Authority
- CA
- Canada
- Prior art keywords
- master
- flip
- circuit
- flop
- flop circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
- H03K3/0372—Bistable circuits of the master-slave type
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
- H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
- H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
- H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manipulation Of Pulses (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Processing Of Color Television Signals (AREA)
Abstract
MASTER-SLAVE FLIP-FLOP CIRCUIT
ABSTRACT OF THE DISCLOSURE
This invention is a phase inversion circuit of improved stability of operation for a master-slave flip-flop circuit.
An additional gating circuit is controlled by two signals, one from an output of the slave flip-flop circuit and the other from an externally applied phase inversion signal.
The output of the additional gating circuit is connected to the master flip-flop circuit through a circuit that also receives a signal from the slave flip-flop output circuit.
In the absence of inversion signals the circuit con-trols the master flip-flop circuit from the slave flip-flop circuit and the master flip-flop circuit controls the slave flip-flop circuit with the assistance of the timing pulses in the usual manner the phase inversion signal can be applied over a wide range of timing intervals of the timing circuit provided the inversion signal overlaps at least partly one of the timing pulses of the regular timing signal when the normal output signal of the slave flip-flop is a "O" and the normal output signal of the master flip-flop circuit is also a "O".
ABSTRACT OF THE DISCLOSURE
This invention is a phase inversion circuit of improved stability of operation for a master-slave flip-flop circuit.
An additional gating circuit is controlled by two signals, one from an output of the slave flip-flop circuit and the other from an externally applied phase inversion signal.
The output of the additional gating circuit is connected to the master flip-flop circuit through a circuit that also receives a signal from the slave flip-flop output circuit.
In the absence of inversion signals the circuit con-trols the master flip-flop circuit from the slave flip-flop circuit and the master flip-flop circuit controls the slave flip-flop circuit with the assistance of the timing pulses in the usual manner the phase inversion signal can be applied over a wide range of timing intervals of the timing circuit provided the inversion signal overlaps at least partly one of the timing pulses of the regular timing signal when the normal output signal of the slave flip-flop is a "O" and the normal output signal of the master flip-flop circuit is also a "O".
Description
SO~ t BACKGROUND OF THE I~ IENTION
Field of the Invention This invention relates generally to master-slave flip-flop circuits and more particularly is directed to a phase inverter for a master-slave flip-flop circuit to invert the phase of the output signals of the master and slave flip-flop circuits at any desired time by means of a phase in-verting signal wherein the tolerance for selecting the pulse width and phase of the phase inverting signal is relatively large, The Prior Art In PAL color television receivers master-slave flip-flop circuits are frequently u9ed a9 a circuit to generate switch-ing signals. At certain time9 the phase of the output signal of the flip-flop cir~ it must be inverted. A ~ypical master-slave flip-flop circuit includes an input terminal to which an input timing signal is applied. One of the two output terminals of the master flip-fl~ is connected to one of t~o input terminals of an AND gate and the other output terminal "
- of the master flip-flop is connected to one of two input terminals of another AND gate. The two output terminals of I the AND gates are connected to the SET and RESET te~minals of the slave flip-flop. The output terminals of the slave flip-flop are the output terminals of the master-slave flip-flop circuit, and each of these output terminals is connected to one Lnput terminal of each of a second pair of AND gates.
The master-slave flip-flop circ~it has a signaL receiving input terminal connected to the other input terminal of each .. . .. .. . . .
'~ ;' . '' ' - 3~
S03~.
oE the first pair of AND gates, and the same input terminal is connected through an inverter to the other input terminal of each AND gate of the second pair. The o~t put terminals of the second pair of AND gateC are connected to the RES2T
and SET terminals, respectively, of the master flip-flop.
Normally the input signal to control the operation o~
the master-slave flip-flop circuit is a square wave having a desired repetition rate. The output signal of the master flip-flop is also a square wave having one-half the repetition rate of the input signal, and the output signal of the slave flip-flop has the same repetition rate as the master flip-flop but is timed to be offset by one-fourth of a complete cycle relative to the master flip-flop output signal.
When it is desired to invert the phase of the master and slave flip-flop circuits one of the input pulses may be eliminated or an additional input pulse may be inserted However, the duration and the timing of the phase inverting signal must be such that its le~ing edge occurs when the regular input signal has a "0" value and the inverting sig-nal must terminate after one pulse of the regular input sig-nal has been eliminated and the signal level of the normal ~iming signal is again at its "0" value. Alternatively, to add an extra control pulse, the additional inverting signal must be quite narrow so that it can start and finish in the same half cycle of the regular timing signal when the regular timing signal has a "0" value. The~e timing limitations- make it difficult to provide a satisfactory inverting operation.
The circuit ~for forming the phase invertlng signal must be .
~ -3-.. .. .. . ..
' ` ~0798Z0 ~0384 very complicated, and it is susceptible to noise superimposed on the phase inverting signal.
OBJECTS AND SUM~JARY OF THE INVENTION `' -One of the principal objects of this invention is to provide an improved phase inverting circuit for a master-slave flip-flop circuit to generate a phase inverting signal that has a relatively wide leeway as to timing and duration.
A circuit to obtain improved operation of phase in-version in a master-slave flip-flop circuit includes a second input signal terminal connected to one input terminal of an additional AND gate. The circuit also includes an OR gate that has its output terminal connected to the SET input termi-nal of the master flip-flop and one of it9 input terminals connected to the output terminal of the AND gate that has one of its input terminals connected to the complementary output ter,minal of the slave flip-flop~ This complementary slave flip-flop output terminal is also connected to one of the input terminals of the AND ~ te in the inverting circuit and the output terminal of this latter AND gate is connected to another input terminal of the OR gate. The base input terminal of a transistor is also connected to the output of the additional AND gate, and the emitter-collector circuit of the transistor is connected between the phase inv~rsion signal input terminal of that AND gate and ground so that a "1" signal generated at the output of the additional AND gate creates,a short circuiting condition at the phase inversion input terminals of that AND gate and thus creates a "O" which turns the AND gate off to prevent the AND gate from remaining .. . . . . . . . .
.'~ ''' ' ' ' ~
-~` 10~98Z0 con~uctive for a long period.
More particularly, there is provided:
A master-slave flip-flop circuit for producing a rectangular wave output signal comprising:
a first input terminal to which a timing signal is applied;
a master flip-flop circuit having inpu~ terminals and output terminalsi a slave flip-flop circuit having input terminals and output terminals;
a master-slave output terminal connected to one of said slave flip-flop output terminals for delivering said rectangular wave output signal;
gating means for connecting said output terminals of said master flip-flop circuit to said input terminals of said slave flip-flop circuit and for connecting said output terminals of said slave flip-flop circuit to said input terminals of said master flip-flop circuit;
said first input terminal being connected to said gating .
means to control the operation thereof with the assistance of output signals from said output terminals of said master flip-flop circuit;
a gating circuit, separate from said gating means and having a connection to one of said output terminals of said slave flip-flop circuit, said gating circuit further being connected to one of said input terminals of said master flip-flop circuit ~:
to assist in controlling the operation of said master flip-flop : circuit; and a second input terminal to receive signals to produce phase inversion of the rectangular wave output signal of said mast~r-slave flip-flop circuit 9 said second input terminal being , ~ -5 .~
connected to said gating circuit to cooperate with said con-nection to said one output terminal of said slave flip-flop circuit in controlling the operation of said gating circuit to achieve controlled phase inversion of the signals at said output terminals of said slave flip-flop circuit.
BRIEF DESCRIPTION_OF THE DRAWINGS
The main and other objects of this invention which will become apparent hereinafter to those skilled in the art will be described in the following specification with reference to the drawings in which:
Fig. 1 is a block circuit diagram of a typical e~isting master-slave flip-flop that hac provisions for dropping out or addi-*g-a~timing pulse to achieve pha~e inversion, Fig. 2 shows the operating signals achieved in the cir-cuit in Fig. 1 in the absence of phase inversion.
Fig. 3 shows signals in the circuit ~f Fig. 1 when the circuit ic operating to invert the phase of the output ~ig-nals by dPIéting one of the regular timing pulses, Fig. 4 shows operating signals in the circuit in Fig. 1 when the circuit is arranged to invert the phase of the output signals by addin~ a short duration phase inversion pulse.
Fig. 5 shows a block circu~ diagram for obtaining im-proved phase inversion o~ the master-slave flip-flop output signals in accordance with the present invention.
Fig. 6 shows operating signals obtained in the use o~
the circuit in Fig. 5.
Fig. 7 is a schematic circuit diagram correqponding to the bloc~ circuit di~gram in Fig. 5.
DETAI~ED DESCRIPTION OF THE PREFERRED EMBOD~ENTS
The circuit in Fig. 1 ha~ an input ter~inal la to which ;~ the nor=al timiDg sigDal is applied. The circuit as showD, ~0798Z~ S0~3 includes an AND gate lb and an OR gate lc, each of which has an input terminal connected to the terminal la. The output terminals of the OR gate and the AND gate are con-nected to two terminals ld and le, respectively, of a three-position switch/that has a third terminal lf connected directly to the input terminal la. This input circuit is not normally used in a master-slave flip-flop circuit but is shown here only as a convenient way of providing means to apply an inversion signal in accordance with existing practice.
The master flip-flop is identified by reference numeral 1 and its normal output terminal Ql is connected to a first gating circuit 2. More specifically the Ql output terminal of the master flip-flop 1 is connected to one of two input terminals of an AND gate that is one of the components of the gating circuit 2. The output o~ the AND gate 3 i9 con-nected to the SET input terminal S4 of the sla~e flip-flop 4.
The complementary output terminal Ql of the master flip-flop 1 i9 connected to one of the in~ut terminals of an A~D gate 5 that is the other component of the gating circuit 2. The output of the AND gate 5 is connected to the RESET terminal R4 of the slave flip-flop circuit 4.
The normal output terminal Q4 of the slave flip-flop 4 is connected to one of the input terminals of a second gating circuit 6, specifically, the terminal Q4 is connected to one of two input terminals of an AND gate 7 that forms one of the components of the gating circuit 6. With the arm lg connect-ing tha input terminal la directly to the master-slave flip-flop circuit, a normal timing s~gnal is applied to the second . .
S o~ `7 -~0798Z0 input terminal of each of the A~ gates 3 and 5 and to the input of an inverter 8 that inverts the signal and connects it to the second input terminal of the AND gate 7. The complementary output terminal Q4 of the slave flip-flop 4 is connected to one of the terminals of an AND gate 9 that forms the second component of the gating circuit 6, and the output terminal of the inverter 8 is also connected to the second input terminal of the AND gate 9. The output termi-nal of the AND gate 9 is connected to the SET input terminal Sl of the master flip-flop 1 and the output terminal of the AND gate 7 is connected to the RESET input terminal Rl of the master flip-flop circuit.
The normal operation o the master-slave flip-flop cir-cuit in Fig. 1 will first be described without any phase inversion but with reference to the waveforms in Fig. 2.
The normal timing signal in Fig. 2A has a value of "11' for one unit of time tl followed by a value of "O" for an equal interval of time t2. This cyc/e~is repeated for the inter-vals t3 and t4 and then starts over again at tl. Assuming that the period tl in Fig. 2 begins when the input signal in Fig. 2A goes from 10ll to "1" and the normal output signal from the Ql terminal of the master flip-flop 1 is already at the value "1", and the normal output signal at the termi-nal Q4 of the slave flip-flop has been at ~a~, the effeet of applying a "1" signal to both input terminals of the AND gate 3 causes that AND gate to apply a "1" eignal to the SET input terminal S4 of the slave flip-flop and raise the normal vaLue of the output signal at the terminal Q4 from "O" to ~ , At , .
the same time the complementary output sig.lal a~ the terminal Ql of the master flip-flop is "0" so that the output of the AND gate 5 is also "0" and thus a "0" resetting signal is applied to the RESET input terminalR4 of the s7ave flip-flop.
At the end of the period tl, the input signal applied to the terminal la reverses to "0", which is inverted by the inverter 8 to a value "1" and applied to the AND gate 7.
Since the normal output signal at the terminal Q4 of the slave flip-10p i9 already "1", as shown in Fig. 2C, a "1"
signal is applied from the AND gate 7 to the RESET terminal Rl of the master flip-flop 1, thereby resetting the master flip-flop circuit and making its normal output signal at the terminal Ql "" and its complementary output signal at the terminal Ql ~1~. At the end of the interval t2, the timing signal applied to the terminal la goes to its "1" value and thereby makes the output of the A~D gate S "1" since both of its input terminals have a "l" signal applied to them. The "1" output signal o~/the AND gate 5 is applied to the RESET terminal R~ to reset the slave flip-flop 4 and cause its normal output voltage at the terminal Q4 to drop to "0" as shown in Fig. 2C while its complementary output terminal Q4 returns to a "1". These output signals disable the AND gate 7 and enable the AND gate 9. ~s a result~ when the input signal applled to the input terminal la drops to "0" at the end of the interval t3, the inverter 8 reverses this ~ælue from "0" to "11' and allows a "1" signal to be applied to the SET input terminal 51 of the ma9ter flip-10p 1.
This brings the condition of the circuit during the interval .
:.... : .: ., .: ..... . -~ 0798Z0 t4 back to t'ne came condition that it had prior to the initial interval tl and thus completes a cycle of operation.
A new cycle begi~s with a second interval tl and the be-ginning of each successive interval ~1 When the input signal is "1" only the ~irst gating cir-cuit 2 is operative, or enabled, and when the input signal at the terminal la is "0" only the second gating circuit 6 is operative. Therefore, when the input s~gnal i5 ~1", the state of the slave flip-flop 4 changes, and when the input signal is "Q", the state of the master 1ip-flop circuit 1 changes. This produces stable operation of the master-slave flip-flop in response to the ~ignal in Fig. 2A being applied to the input terminal la and the switch arm lg connected to ; the terminal lf. The signal shown in Fig. 2D appears at the normal output terminal Ql of the master flip-flop 1.
Sometimes the pha9e of the output ~ignaL of the master-slave flip-flop circuit must be in~erted at a certain tLme.
For example, such operation is required in P~L color tele-vision receivers for certain circuits that require such phase inversion at the end of each vertical scanning interval.
Fig. 1 shows two means of providing in~ersion. The first uses the AND gate lb and requires that the switch arm lg be shifted to engage the terminal la at the output of the AND
gate lb. The timing circuit applied to the input terminal la is shown in Fig. 3 and is the same as the timing signal shown in Fig. 2A. An inverting siOnal shown in Fig. 3B is applied to the sÆcond input terminal lh of the AND gate lb. Thie inverting signal in Fig. 3B has a value "1" except during a certain part of the interval t5,wh~ h extends ~rom the be-, ~ .
- .
,: :. . , ' 10~98Z0 s08~4 ginning of the "O" value of one of the timing intervals in the signal shown in Fig. 3A immediately preceding a timing signal pulse Pl that occupies the next timing inter-val and has the value "1". The interval t5 continues to some part of the timing interval i~mediately following the pulse Pl when the signal in Fig. 3A is again at its "O"
value. The effect of applying the phase inverting signal in Fig. 3B to the input terminal lh is to allow all of the regular timing pulses of the signal in Fig. 3A to pass through the AND gate lb except the pulse Pl that occurs when the signal in Fig. 3B has a "O" value. The pulse thus eliminated is the pulse Pl in Fig. 3A. Except or the elimination of thi~ pulse from the normal timing signal, . .
the operation of the master-slave flip-flop remains the same as described in connection with the non-inverting oper-ation. The effect of eliminatlng pulse Pl entirely is to cause the oircuit in Fig. 1 to maintain the status it achieved when the timing signal shown in Fig~ 3A dropped to its ,o-t value preceding the time of occurrence of the pulse Pl.
Since there is no pulse Pl to 2ffect the status of the master flip-flop 1 or the slave flip-flop 4 in Fig. 1, they maintain the voltage conditions in which the normal output signal at the term~nal Q4 of the slave flip flop 4 is at its "1" value and the normal output value at the tenminal Ql of the master flip-flop 1 rcmains at its "O" value. At t~e end of the phase inversion pulse shown în Fig. 3B, which must occur prior to the next positive pulse ollowing the pulse Pl in the timing signal in Fig. 3A, the circuit is free to make the changes .
. . . .
S038' 1 ~79 8 ~0 that it would normally make insofar as the states of con-ductivity of the master flip-flop 1 and the slave flip-flop 4 are concerned. That is, when the value of the timing signal in Fig. 3A goes positive from the "O" value to the "1" value following the missing pulse Pl, the voltage vaIue at the terminal Q4 drops to "O". Later after the passage o~ another unit of time equal to the width of the positive pulse following next after the pulse Pl, the master flip-flop would change its state of conductivity from llo-- to "1".
In effect what has happened is that the output voltage con-ditions of both the master and slave flip-flops remain un-changed for an additional two intervals of time of the timing signal in Fig. 3A. As measured in the chart in ~ig. 2A, these two intervals could be tl and t2 or t3 and t4 or any repetition of those pairs. This changeY the condition o conductivity of the master and slave flip-flops to the re-verse of what they would have been if the pulse Pl had been allowed to pass through to the gating circuits 2 and 6 in the normal manner.
The other form of phase inversion is accomplished by connecting the switch arm lg to the contact le at the output of the OR gate lc. The waveforms in Fig. 4 show the oper-ation. In this configuration of the circuit the phase in-verting pulse is shown in Fig. 4B and must be less than one unit of time indicated by the time interval t6 in Fig. 4A, the timing waveform. This phase inversion signal is applied to an input terminal li of the OR gate lc.
In accordance with the usual operation of an OR gate ' S 0~
107~8Z0 the timing signal in Fig. 4A, which is actually identical with the timing signal in Fig. 2.4, passes through to the switch arm lg without change, provided the inversion pulse in Fig. 4B does not partially overlap with the pulses P2 and P3 on either side of the time interval t6 in Fig. 4A.
Fig. 4C shows the signal at the complementary output termi-nal Q4 of the slave flip-flop-4 in Fig. 1, and Fig. 4D shows the regular output signal at the terminal Ql of the master flip-flop 1 in Fig. 1. The leading edge of the phase inversion pulse in Fig. 4B causes the AND gates 3 and 5 to be enabled.
At this time the complementary output at the terminal Ql has the value "1" and can therefore pass through to the RESET
terminal R4 of the slave flip-flop 4. The output of the AND
gate 3 is kept at a "O" value and it is this value that is applied to the SET terminal S4 of the slave flip-flop 4.
These conditions cause the slave flip-flop to be reset so that the output at the Q4 terminal drops to its "O" value and the output at the complementary terminal Q4 therefore rises to its "l;' value. The master flip-flop 1 does not change its condition of conductivity until the phase inver~îon signal in Fig. 4B is terminated and drops to its "O" value durin~ the interval t6. This enables the AND gates 7 and 9.
Since the complementary output-terminal Q4 is at its "1"
value, a "l" signal is available at the output terminal o~
the AND gate 9 but only a "O" value i9 available at the output terminal of the AND gate 7. The "1" value output signal fxom the AND gate 9 i~ applied t~ the SET terminal Sl o the master flip-flop 1 and switches-the state of con-- , ' , ' ' : ~
S~83 ductivity of that flip-flop so that the normal terminal Ql rises to a "1" value and, correspondingly, the complementary terminal Ql drops to "0" These conditions are shown in Figs. 4C and 4D. Thereafter, it will be observed that the operation of the master-slave flip-flop continues but with its phase inverted from what it was prior to the phase inversion pulse.
Both of these arrangements for applying phase inversion signals to a master-slave flip-flop circuit require very accurate generation of the phase inversion pulses both in terms of beginning and ending and in terms of duration of these pulqes. In terms of the switching signal generating circuit in PAL color television receivers, the phase in-version pulse must be accurately timed with respect to the pulse width of a single horizontal time interval, which means that the pulses must be very accurately timed. This is difficult to obtain and therefore it has been required in the past that the circuit for forming the phase inversion signal must be very complicated to operate with sufficient accuracy. Furthermore, if electrical noise is superimposed : ' on the phase inversion signal the noisy operation will be unstable, and misoperation will easily occur.
Fig. 5 shows one embodiment of the present invention The master-slave flip-flop section of Fig. 5 is identical with that of Fig. 1 except that Fig. 5 has a third gating circuit lZ and an additional 0~ gate 18. The gating circuit includes an input terminal lj to which a phase inversîon signal is applied. This terminal is connected to one of two . .
s08&~
1~798ZO
, input terminals of an AND gate 13 by way o~ an RC circuit comprising a resistor 14 and a capacitor 15 that slightly delay or integrate pulses applied to the terminal lj. The circuit 12 also includes a trancistor 16 that has its emitter-collector circuit connected directly in parallel with the capacitor 15. The output of the AND gate 13 is connected by means of a series resistor 17 to the base of the transistor 16 and is also connected to one of the input terminals of the OR gate 18. The other input terminal o~ the OR gate 18 is connected to the output terminal of the AN~ gate 9, and the output of the OR gate 18 is connected to the SET input termi-nal Sl of the master flip-flop 1. The complemcntary output terminal Q4 of the slave flip-flop 4 is connected to one of the input terminals of the AND gate as shown in the circuit in Fig. 1 and is also connected to the second input terminal of the AND gate 13.
The operation of the circuit in Fig. 5 will be described in relation to waveforms in Fig. 6. The wavefor~ in Fig. 6A
is the timing pulse signal similar to the timing pulse signals previously considered in Figs. 2-4. Fig. 6B shows the sig-nal at the regular output terminal Q4 of the slave flip-flop 4, and Fig. 6C shows the signal at the complementary output terminal Q~ of the slave flip-flop 4. Fig. 6D shows a phase inversion signal that happens to begin during the time inter-val t7 and Fig. 6E shows the normal output signal at the terminal Ql of the master flip-10p 1.
The operation of the circuit in Fig. 5 is identical with that of the circuit in Fig. 1 for the first five timing ' S088' 1~79820 intervals t2, t~, t4, tl and t2. Therefore it is unneeessary to describe again the way in which the signale in Figs. 6B, 6C and 6E are generated prior to the interval t7. The inter-val t7 i5 SO identified simply to set it apart from the regular intervals in which the phase inversion signal does not fall; actually it is an interval that includes a positive pulse P4 of the timing signal in Fig. 6A. Also at the be-ginning of the interval t7 the normal output at the terminal Q4 of the slave flip-flop drops to its "O" value as shown in Fig. 6B, and the complementary output terminal Q4 rises to its "1" value to enable the ANB gate 13. The phase inversion signal shown in Fig. 6D occurs shortly after the beginning of the time interval t7 and produces a "1" signal at the out-put of the AND gate 13. This signal passes through the OR
gate 18 to the SET input terminal Sl of the master flip-flop 1 and thereby changes the conditions of the conductivity at the normal and complementary output terminals Ql and Q
As a result, the voltage value at the output terminal Ql rises to "l". The signal at the normal output terminal Ql and the complementary signal at the output Ql of the master flip-flop are applied to the SET input terminal S4 and the RESET terminal R4, respectively, through the AND gate cir-cuits 3 and 5. The "1" value signal at the normal output terminal Ql thus sets the slave flip-flop 4 so that its sig-nal value at the nonmal output terminal Q4 becomes "1". As a result, the phase of the regular output terminals of the master and slave flip-flop circuits are inverted from that point on as shown in the right hand portion of the signals :
so~s/~
~ 0 7 9 8ZO
of Figs. 6B, 6C and 6~.
The pulse width of the phase inverting signal shown in Fig. 6D can be selected to have any value within the time region indicated by the broken line in Fig. 6D, provided at least part of the phase inversion signal overlaps with at least part of the time interval t7. Even if impulse noise is superimposed on the phase inversion signal, such noise can be eliminated by the integrating circuit formed by the resistor 14 and the capacitor 15.
When the output signal of the AND gate 13 is raised to -"1" by having a "1" signal applied to both of its input termi-nals, this "l" output signal fed to the base of the transistor 16 through the resistor 17 causes the transistor 16 to become conductive and thereby to drop the level -of the lower input terminal of the AND gate 13 to "0". This causes the output terminal of the AND gate 13 also to become lloll virtually simultaneously. Even if the pulse width of the phase inversion signal is relatively great, and the lower input terminal of the AND gate becomes "1" after the transistor 16 becomes non-conductive as the slave flip-flop 4 is set by the regular input terminal Ql of the master flip-flop l, causing the complementary outpllt terminal Q4 of the slave flip-flop to become "0", the output terminal of the AND gate 13 will be maintained at a 190ll value during the remainder of the period t7. Since both the SET and RESET input terminals of the master flip-10p are maintained at "0" under such conditions, the state of conductivity of the master flip-flop is un-changed during the remainder of the time interval t7.
.
.
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Fig~ 7 shows a schematic circuit diagram representing the block diagram in Fig, 5. The same reference numerals are applied to circuits in Fig. 7 that correspond to cir-cuits in Fig, 5, and the detailed explanation o~ those circuits is therefore abbreviated, An input signal from the input terminal la i~ supplied through a resistor 19 to the base of an NPN transistor 20, The same input signal is also supplied through a resistor 21, which is part of a voltage divider, to the base of a transistor 22, A resistor 23 connected between the base of the transistor 22 and ground constitutes the other part of the voltage-divider, The collector of the transistor 20 is connected to the emitters of two NPN transistors 24 and 25 in the ma9ter flip-flop 1, and the-emitter of the transistor 20 i9 grounded. The collector of the transistor 24 is connected to the ba9e of the tran9i9tor 25 and is also connected through a load resistor 26 to a power supply terminal B+, In like manner the collector of the transistor 25 is connected to the ba9e of the transistor 24 and is also connected to the power supply terminal B+ by way Pf a load resistor 27, The collector-emitter circuit of the transistor 22 is connected in series between the emitters of two NPN transis-tors 28 and 29 and ground. The ba9es of the transistors 28 and 29 is connected to the collectors of the transistor~ 25 .~
and 24, respectively, and the collector9 of the transistors 28 and 29 are connected to the bases of two transistors 30 and 31, which form the active element of the slave flip-flop 4.
.
- . - .
: . . . ~ : .
so~
1~79820 The collector of the transistor 28 is also connected to the collector of the transistor 31 and, through a load resistor 32 to the B+ terminal. Correspondingly, the collector of the transistor 29 is connected to the collector of the tran-sistor 30 and, thrDugh a load resistor 33, to the B+ terminal.
The collector of the transistor 30 is also connected directly to the base of an NPN transistor 34 which is connected as a grounded emitter circuit. The collector of the transistor 34 is connected to the B+ terminal by way of a load resistor 35. The transistor 34 inverts the output signal at the col-lector of the transistor 30.
The phase inversion signal applied to the te~rminal lj passes through the integrating circuit resistor 14 to the base of a transistor 36. The base of the transistor 36 is grounded through the capacitor 15 to achieve the 9 lightly integrating operation of the RC circuit. The collector of the transistor 36 is connected directly to the power supply terminal B+ and ~he emitter of the transistor 36 is connected to ground by way of a resistor 37. The emitter of the tran-sistor 36 is also connected to the emitter of another NPN
transistor 38, the collector of which is connected through a load resistor 39 to the power SUL~P1Y terminal B+. A biasing circuit comprising resistors 40 and 41 is connected to the ~ase of the transistor 38 to establish a reference voltage at that point.
The collector of the transistor 38 is connected to ths base of a PNP transistor 42, the emitter of which is directly connected to the power supply terminal B+. The collector of .~ , 1079~3Z0 the transistor 42 is connected to ground through a series circuit comprising two resistors 43 and 44. The junction between the latter resistors is connected to the base of a transistor 45, the emitter of which is grounded. A resis-tor 46 connects the collector of the transistor 34 to the collector of the transistor 45, and through a resistor 47 to the base of the transistor 16. As shown in Fig. 5, the emitter collector circuit of this NPN transistor is connected directly in parallel with the capacitor 15, The resistor 46 also connects the collector of the transi9tor 34 to the base of an NFN transistor 48 by way of another series connected resistor 49. The collector of the transistor 48 is connected back to the common circuit point of the collector of the transistor 24 and the load resistor 26, The operation of the circuit in Fig. 7 will be explained with reference to the waveforms in Fig. 6, since Fig. 7 is basically only a more detailed circuit drawing corresponding to the circuit diagram in Fig. 5. The input timing signal in Fig. 6A applied to the input terminal la although illustrated as being perfectly square actually has some slope to both the leading and lagging edge of each of the pulses such as the pulse P4, As a result9 the signal applied through the resistor 19 to the base of the transistor reaches the con-ductivity level of that transistor more quickly than the volt-age applied through the attenuation produced by the resistors 21 and 23. The attenuation causes the transistor 22 to become conductive just slightly after the transistor 20, The con-verse is true at the lagging edge of each of the pulses making . .
.
,.
.
.
S~9,84 ~07~8~0 up the timing signal in Fig. 6A; the transistor 22 reaches its cutoff level just slightly before the transistor 20 reaches its cu~off level. It is convenient to call the transition time between cutoff and non-cutoff as a transient condition and to refer to the condition in which the timing pulses are either at their "0" value or their "1" value for a relatively long time ac the steady state condition.
If the phase inversion signal applied to the input terminal 1~ is "0", the transistor 36 will be nonconductive.
By differential operation, the transistor 38 will be con-ductive and produce a voltage drop across the resistor 39 that causes the transistor 42 to be conductive. The current flowing through the base emitter circuit of the transistor 42 also flows through the resistors 43 and 44~ This raises the voltage at the base of the transistor 45 to a "1" value and causes the bases of the transistors 16 and 48 to be at the "0" value, no matter whether the collector of the transistor 34 is a "1" or a "0".
In the time period t2 in Fig. 6, the normal output termi- -nal Ql of the master flip-flop is "0" and the normal output of the slave flip-flop is "1" and both of the transistors 20 and 22 are nonconductive. At the beginning Qf the time period t3 when the input signal in Fig. 6A is rising, the transistor 20 becomes conductive first while the transistor 22 is still nonconductive, thereby causing the transistors 28 and 29 to continue to be nonconductive. This is the transient condition during which the state of conductivity of the flip-flops 1 and 4 is changing, and in this condition as the complementary output
Field of the Invention This invention relates generally to master-slave flip-flop circuits and more particularly is directed to a phase inverter for a master-slave flip-flop circuit to invert the phase of the output signals of the master and slave flip-flop circuits at any desired time by means of a phase in-verting signal wherein the tolerance for selecting the pulse width and phase of the phase inverting signal is relatively large, The Prior Art In PAL color television receivers master-slave flip-flop circuits are frequently u9ed a9 a circuit to generate switch-ing signals. At certain time9 the phase of the output signal of the flip-flop cir~ it must be inverted. A ~ypical master-slave flip-flop circuit includes an input terminal to which an input timing signal is applied. One of the two output terminals of the master flip-fl~ is connected to one of t~o input terminals of an AND gate and the other output terminal "
- of the master flip-flop is connected to one of two input terminals of another AND gate. The two output terminals of I the AND gates are connected to the SET and RESET te~minals of the slave flip-flop. The output terminals of the slave flip-flop are the output terminals of the master-slave flip-flop circuit, and each of these output terminals is connected to one Lnput terminal of each of a second pair of AND gates.
The master-slave flip-flop circ~it has a signaL receiving input terminal connected to the other input terminal of each .. . .. .. . . .
'~ ;' . '' ' - 3~
S03~.
oE the first pair of AND gates, and the same input terminal is connected through an inverter to the other input terminal of each AND gate of the second pair. The o~t put terminals of the second pair of AND gateC are connected to the RES2T
and SET terminals, respectively, of the master flip-flop.
Normally the input signal to control the operation o~
the master-slave flip-flop circuit is a square wave having a desired repetition rate. The output signal of the master flip-flop is also a square wave having one-half the repetition rate of the input signal, and the output signal of the slave flip-flop has the same repetition rate as the master flip-flop but is timed to be offset by one-fourth of a complete cycle relative to the master flip-flop output signal.
When it is desired to invert the phase of the master and slave flip-flop circuits one of the input pulses may be eliminated or an additional input pulse may be inserted However, the duration and the timing of the phase inverting signal must be such that its le~ing edge occurs when the regular input signal has a "0" value and the inverting sig-nal must terminate after one pulse of the regular input sig-nal has been eliminated and the signal level of the normal ~iming signal is again at its "0" value. Alternatively, to add an extra control pulse, the additional inverting signal must be quite narrow so that it can start and finish in the same half cycle of the regular timing signal when the regular timing signal has a "0" value. The~e timing limitations- make it difficult to provide a satisfactory inverting operation.
The circuit ~for forming the phase invertlng signal must be .
~ -3-.. .. .. . ..
' ` ~0798Z0 ~0384 very complicated, and it is susceptible to noise superimposed on the phase inverting signal.
OBJECTS AND SUM~JARY OF THE INVENTION `' -One of the principal objects of this invention is to provide an improved phase inverting circuit for a master-slave flip-flop circuit to generate a phase inverting signal that has a relatively wide leeway as to timing and duration.
A circuit to obtain improved operation of phase in-version in a master-slave flip-flop circuit includes a second input signal terminal connected to one input terminal of an additional AND gate. The circuit also includes an OR gate that has its output terminal connected to the SET input termi-nal of the master flip-flop and one of it9 input terminals connected to the output terminal of the AND gate that has one of its input terminals connected to the complementary output ter,minal of the slave flip-flop~ This complementary slave flip-flop output terminal is also connected to one of the input terminals of the AND ~ te in the inverting circuit and the output terminal of this latter AND gate is connected to another input terminal of the OR gate. The base input terminal of a transistor is also connected to the output of the additional AND gate, and the emitter-collector circuit of the transistor is connected between the phase inv~rsion signal input terminal of that AND gate and ground so that a "1" signal generated at the output of the additional AND gate creates,a short circuiting condition at the phase inversion input terminals of that AND gate and thus creates a "O" which turns the AND gate off to prevent the AND gate from remaining .. . . . . . . . .
.'~ ''' ' ' ' ~
-~` 10~98Z0 con~uctive for a long period.
More particularly, there is provided:
A master-slave flip-flop circuit for producing a rectangular wave output signal comprising:
a first input terminal to which a timing signal is applied;
a master flip-flop circuit having inpu~ terminals and output terminalsi a slave flip-flop circuit having input terminals and output terminals;
a master-slave output terminal connected to one of said slave flip-flop output terminals for delivering said rectangular wave output signal;
gating means for connecting said output terminals of said master flip-flop circuit to said input terminals of said slave flip-flop circuit and for connecting said output terminals of said slave flip-flop circuit to said input terminals of said master flip-flop circuit;
said first input terminal being connected to said gating .
means to control the operation thereof with the assistance of output signals from said output terminals of said master flip-flop circuit;
a gating circuit, separate from said gating means and having a connection to one of said output terminals of said slave flip-flop circuit, said gating circuit further being connected to one of said input terminals of said master flip-flop circuit ~:
to assist in controlling the operation of said master flip-flop : circuit; and a second input terminal to receive signals to produce phase inversion of the rectangular wave output signal of said mast~r-slave flip-flop circuit 9 said second input terminal being , ~ -5 .~
connected to said gating circuit to cooperate with said con-nection to said one output terminal of said slave flip-flop circuit in controlling the operation of said gating circuit to achieve controlled phase inversion of the signals at said output terminals of said slave flip-flop circuit.
BRIEF DESCRIPTION_OF THE DRAWINGS
The main and other objects of this invention which will become apparent hereinafter to those skilled in the art will be described in the following specification with reference to the drawings in which:
Fig. 1 is a block circuit diagram of a typical e~isting master-slave flip-flop that hac provisions for dropping out or addi-*g-a~timing pulse to achieve pha~e inversion, Fig. 2 shows the operating signals achieved in the cir-cuit in Fig. 1 in the absence of phase inversion.
Fig. 3 shows signals in the circuit ~f Fig. 1 when the circuit ic operating to invert the phase of the output ~ig-nals by dPIéting one of the regular timing pulses, Fig. 4 shows operating signals in the circuit in Fig. 1 when the circuit is arranged to invert the phase of the output signals by addin~ a short duration phase inversion pulse.
Fig. 5 shows a block circu~ diagram for obtaining im-proved phase inversion o~ the master-slave flip-flop output signals in accordance with the present invention.
Fig. 6 shows operating signals obtained in the use o~
the circuit in Fig. 5.
Fig. 7 is a schematic circuit diagram correqponding to the bloc~ circuit di~gram in Fig. 5.
DETAI~ED DESCRIPTION OF THE PREFERRED EMBOD~ENTS
The circuit in Fig. 1 ha~ an input ter~inal la to which ;~ the nor=al timiDg sigDal is applied. The circuit as showD, ~0798Z~ S0~3 includes an AND gate lb and an OR gate lc, each of which has an input terminal connected to the terminal la. The output terminals of the OR gate and the AND gate are con-nected to two terminals ld and le, respectively, of a three-position switch/that has a third terminal lf connected directly to the input terminal la. This input circuit is not normally used in a master-slave flip-flop circuit but is shown here only as a convenient way of providing means to apply an inversion signal in accordance with existing practice.
The master flip-flop is identified by reference numeral 1 and its normal output terminal Ql is connected to a first gating circuit 2. More specifically the Ql output terminal of the master flip-flop 1 is connected to one of two input terminals of an AND gate that is one of the components of the gating circuit 2. The output o~ the AND gate 3 i9 con-nected to the SET input terminal S4 of the sla~e flip-flop 4.
The complementary output terminal Ql of the master flip-flop 1 i9 connected to one of the in~ut terminals of an A~D gate 5 that is the other component of the gating circuit 2. The output of the AND gate 5 is connected to the RESET terminal R4 of the slave flip-flop circuit 4.
The normal output terminal Q4 of the slave flip-flop 4 is connected to one of the input terminals of a second gating circuit 6, specifically, the terminal Q4 is connected to one of two input terminals of an AND gate 7 that forms one of the components of the gating circuit 6. With the arm lg connect-ing tha input terminal la directly to the master-slave flip-flop circuit, a normal timing s~gnal is applied to the second . .
S o~ `7 -~0798Z0 input terminal of each of the A~ gates 3 and 5 and to the input of an inverter 8 that inverts the signal and connects it to the second input terminal of the AND gate 7. The complementary output terminal Q4 of the slave flip-flop 4 is connected to one of the terminals of an AND gate 9 that forms the second component of the gating circuit 6, and the output terminal of the inverter 8 is also connected to the second input terminal of the AND gate 9. The output termi-nal of the AND gate 9 is connected to the SET input terminal Sl of the master flip-flop 1 and the output terminal of the AND gate 7 is connected to the RESET input terminal Rl of the master flip-flop circuit.
The normal operation o the master-slave flip-flop cir-cuit in Fig. 1 will first be described without any phase inversion but with reference to the waveforms in Fig. 2.
The normal timing signal in Fig. 2A has a value of "11' for one unit of time tl followed by a value of "O" for an equal interval of time t2. This cyc/e~is repeated for the inter-vals t3 and t4 and then starts over again at tl. Assuming that the period tl in Fig. 2 begins when the input signal in Fig. 2A goes from 10ll to "1" and the normal output signal from the Ql terminal of the master flip-flop 1 is already at the value "1", and the normal output signal at the termi-nal Q4 of the slave flip-flop has been at ~a~, the effeet of applying a "1" signal to both input terminals of the AND gate 3 causes that AND gate to apply a "1" eignal to the SET input terminal S4 of the slave flip-flop and raise the normal vaLue of the output signal at the terminal Q4 from "O" to ~ , At , .
the same time the complementary output sig.lal a~ the terminal Ql of the master flip-flop is "0" so that the output of the AND gate 5 is also "0" and thus a "0" resetting signal is applied to the RESET input terminalR4 of the s7ave flip-flop.
At the end of the period tl, the input signal applied to the terminal la reverses to "0", which is inverted by the inverter 8 to a value "1" and applied to the AND gate 7.
Since the normal output signal at the terminal Q4 of the slave flip-10p i9 already "1", as shown in Fig. 2C, a "1"
signal is applied from the AND gate 7 to the RESET terminal Rl of the master flip-flop 1, thereby resetting the master flip-flop circuit and making its normal output signal at the terminal Ql "" and its complementary output signal at the terminal Ql ~1~. At the end of the interval t2, the timing signal applied to the terminal la goes to its "1" value and thereby makes the output of the A~D gate S "1" since both of its input terminals have a "l" signal applied to them. The "1" output signal o~/the AND gate 5 is applied to the RESET terminal R~ to reset the slave flip-flop 4 and cause its normal output voltage at the terminal Q4 to drop to "0" as shown in Fig. 2C while its complementary output terminal Q4 returns to a "1". These output signals disable the AND gate 7 and enable the AND gate 9. ~s a result~ when the input signal applled to the input terminal la drops to "0" at the end of the interval t3, the inverter 8 reverses this ~ælue from "0" to "11' and allows a "1" signal to be applied to the SET input terminal 51 of the ma9ter flip-10p 1.
This brings the condition of the circuit during the interval .
:.... : .: ., .: ..... . -~ 0798Z0 t4 back to t'ne came condition that it had prior to the initial interval tl and thus completes a cycle of operation.
A new cycle begi~s with a second interval tl and the be-ginning of each successive interval ~1 When the input signal is "1" only the ~irst gating cir-cuit 2 is operative, or enabled, and when the input signal at the terminal la is "0" only the second gating circuit 6 is operative. Therefore, when the input s~gnal i5 ~1", the state of the slave flip-flop 4 changes, and when the input signal is "Q", the state of the master 1ip-flop circuit 1 changes. This produces stable operation of the master-slave flip-flop in response to the ~ignal in Fig. 2A being applied to the input terminal la and the switch arm lg connected to ; the terminal lf. The signal shown in Fig. 2D appears at the normal output terminal Ql of the master flip-flop 1.
Sometimes the pha9e of the output ~ignaL of the master-slave flip-flop circuit must be in~erted at a certain tLme.
For example, such operation is required in P~L color tele-vision receivers for certain circuits that require such phase inversion at the end of each vertical scanning interval.
Fig. 1 shows two means of providing in~ersion. The first uses the AND gate lb and requires that the switch arm lg be shifted to engage the terminal la at the output of the AND
gate lb. The timing circuit applied to the input terminal la is shown in Fig. 3 and is the same as the timing signal shown in Fig. 2A. An inverting siOnal shown in Fig. 3B is applied to the sÆcond input terminal lh of the AND gate lb. Thie inverting signal in Fig. 3B has a value "1" except during a certain part of the interval t5,wh~ h extends ~rom the be-, ~ .
- .
,: :. . , ' 10~98Z0 s08~4 ginning of the "O" value of one of the timing intervals in the signal shown in Fig. 3A immediately preceding a timing signal pulse Pl that occupies the next timing inter-val and has the value "1". The interval t5 continues to some part of the timing interval i~mediately following the pulse Pl when the signal in Fig. 3A is again at its "O"
value. The effect of applying the phase inverting signal in Fig. 3B to the input terminal lh is to allow all of the regular timing pulses of the signal in Fig. 3A to pass through the AND gate lb except the pulse Pl that occurs when the signal in Fig. 3B has a "O" value. The pulse thus eliminated is the pulse Pl in Fig. 3A. Except or the elimination of thi~ pulse from the normal timing signal, . .
the operation of the master-slave flip-flop remains the same as described in connection with the non-inverting oper-ation. The effect of eliminatlng pulse Pl entirely is to cause the oircuit in Fig. 1 to maintain the status it achieved when the timing signal shown in Fig~ 3A dropped to its ,o-t value preceding the time of occurrence of the pulse Pl.
Since there is no pulse Pl to 2ffect the status of the master flip-flop 1 or the slave flip-flop 4 in Fig. 1, they maintain the voltage conditions in which the normal output signal at the term~nal Q4 of the slave flip flop 4 is at its "1" value and the normal output value at the tenminal Ql of the master flip-flop 1 rcmains at its "O" value. At t~e end of the phase inversion pulse shown în Fig. 3B, which must occur prior to the next positive pulse ollowing the pulse Pl in the timing signal in Fig. 3A, the circuit is free to make the changes .
. . . .
S038' 1 ~79 8 ~0 that it would normally make insofar as the states of con-ductivity of the master flip-flop 1 and the slave flip-flop 4 are concerned. That is, when the value of the timing signal in Fig. 3A goes positive from the "O" value to the "1" value following the missing pulse Pl, the voltage vaIue at the terminal Q4 drops to "O". Later after the passage o~ another unit of time equal to the width of the positive pulse following next after the pulse Pl, the master flip-flop would change its state of conductivity from llo-- to "1".
In effect what has happened is that the output voltage con-ditions of both the master and slave flip-flops remain un-changed for an additional two intervals of time of the timing signal in Fig. 3A. As measured in the chart in ~ig. 2A, these two intervals could be tl and t2 or t3 and t4 or any repetition of those pairs. This changeY the condition o conductivity of the master and slave flip-flops to the re-verse of what they would have been if the pulse Pl had been allowed to pass through to the gating circuits 2 and 6 in the normal manner.
The other form of phase inversion is accomplished by connecting the switch arm lg to the contact le at the output of the OR gate lc. The waveforms in Fig. 4 show the oper-ation. In this configuration of the circuit the phase in-verting pulse is shown in Fig. 4B and must be less than one unit of time indicated by the time interval t6 in Fig. 4A, the timing waveform. This phase inversion signal is applied to an input terminal li of the OR gate lc.
In accordance with the usual operation of an OR gate ' S 0~
107~8Z0 the timing signal in Fig. 4A, which is actually identical with the timing signal in Fig. 2.4, passes through to the switch arm lg without change, provided the inversion pulse in Fig. 4B does not partially overlap with the pulses P2 and P3 on either side of the time interval t6 in Fig. 4A.
Fig. 4C shows the signal at the complementary output termi-nal Q4 of the slave flip-flop-4 in Fig. 1, and Fig. 4D shows the regular output signal at the terminal Ql of the master flip-flop 1 in Fig. 1. The leading edge of the phase inversion pulse in Fig. 4B causes the AND gates 3 and 5 to be enabled.
At this time the complementary output at the terminal Ql has the value "1" and can therefore pass through to the RESET
terminal R4 of the slave flip-flop 4. The output of the AND
gate 3 is kept at a "O" value and it is this value that is applied to the SET terminal S4 of the slave flip-flop 4.
These conditions cause the slave flip-flop to be reset so that the output at the Q4 terminal drops to its "O" value and the output at the complementary terminal Q4 therefore rises to its "l;' value. The master flip-flop 1 does not change its condition of conductivity until the phase inver~îon signal in Fig. 4B is terminated and drops to its "O" value durin~ the interval t6. This enables the AND gates 7 and 9.
Since the complementary output-terminal Q4 is at its "1"
value, a "l" signal is available at the output terminal o~
the AND gate 9 but only a "O" value i9 available at the output terminal of the AND gate 7. The "1" value output signal fxom the AND gate 9 i~ applied t~ the SET terminal Sl o the master flip-flop 1 and switches-the state of con-- , ' , ' ' : ~
S~83 ductivity of that flip-flop so that the normal terminal Ql rises to a "1" value and, correspondingly, the complementary terminal Ql drops to "0" These conditions are shown in Figs. 4C and 4D. Thereafter, it will be observed that the operation of the master-slave flip-flop continues but with its phase inverted from what it was prior to the phase inversion pulse.
Both of these arrangements for applying phase inversion signals to a master-slave flip-flop circuit require very accurate generation of the phase inversion pulses both in terms of beginning and ending and in terms of duration of these pulqes. In terms of the switching signal generating circuit in PAL color television receivers, the phase in-version pulse must be accurately timed with respect to the pulse width of a single horizontal time interval, which means that the pulses must be very accurately timed. This is difficult to obtain and therefore it has been required in the past that the circuit for forming the phase inversion signal must be very complicated to operate with sufficient accuracy. Furthermore, if electrical noise is superimposed : ' on the phase inversion signal the noisy operation will be unstable, and misoperation will easily occur.
Fig. 5 shows one embodiment of the present invention The master-slave flip-flop section of Fig. 5 is identical with that of Fig. 1 except that Fig. 5 has a third gating circuit lZ and an additional 0~ gate 18. The gating circuit includes an input terminal lj to which a phase inversîon signal is applied. This terminal is connected to one of two . .
s08&~
1~798ZO
, input terminals of an AND gate 13 by way o~ an RC circuit comprising a resistor 14 and a capacitor 15 that slightly delay or integrate pulses applied to the terminal lj. The circuit 12 also includes a trancistor 16 that has its emitter-collector circuit connected directly in parallel with the capacitor 15. The output of the AND gate 13 is connected by means of a series resistor 17 to the base of the transistor 16 and is also connected to one of the input terminals of the OR gate 18. The other input terminal o~ the OR gate 18 is connected to the output terminal of the AN~ gate 9, and the output of the OR gate 18 is connected to the SET input termi-nal Sl of the master flip-flop 1. The complemcntary output terminal Q4 of the slave flip-flop 4 is connected to one of the input terminals of the AND gate as shown in the circuit in Fig. 1 and is also connected to the second input terminal of the AND gate 13.
The operation of the circuit in Fig. 5 will be described in relation to waveforms in Fig. 6. The wavefor~ in Fig. 6A
is the timing pulse signal similar to the timing pulse signals previously considered in Figs. 2-4. Fig. 6B shows the sig-nal at the regular output terminal Q4 of the slave flip-flop 4, and Fig. 6C shows the signal at the complementary output terminal Q~ of the slave flip-flop 4. Fig. 6D shows a phase inversion signal that happens to begin during the time inter-val t7 and Fig. 6E shows the normal output signal at the terminal Ql of the master flip-10p 1.
The operation of the circuit in Fig. 5 is identical with that of the circuit in Fig. 1 for the first five timing ' S088' 1~79820 intervals t2, t~, t4, tl and t2. Therefore it is unneeessary to describe again the way in which the signale in Figs. 6B, 6C and 6E are generated prior to the interval t7. The inter-val t7 i5 SO identified simply to set it apart from the regular intervals in which the phase inversion signal does not fall; actually it is an interval that includes a positive pulse P4 of the timing signal in Fig. 6A. Also at the be-ginning of the interval t7 the normal output at the terminal Q4 of the slave flip-flop drops to its "O" value as shown in Fig. 6B, and the complementary output terminal Q4 rises to its "1" value to enable the ANB gate 13. The phase inversion signal shown in Fig. 6D occurs shortly after the beginning of the time interval t7 and produces a "1" signal at the out-put of the AND gate 13. This signal passes through the OR
gate 18 to the SET input terminal Sl of the master flip-flop 1 and thereby changes the conditions of the conductivity at the normal and complementary output terminals Ql and Q
As a result, the voltage value at the output terminal Ql rises to "l". The signal at the normal output terminal Ql and the complementary signal at the output Ql of the master flip-flop are applied to the SET input terminal S4 and the RESET terminal R4, respectively, through the AND gate cir-cuits 3 and 5. The "1" value signal at the normal output terminal Ql thus sets the slave flip-flop 4 so that its sig-nal value at the nonmal output terminal Q4 becomes "1". As a result, the phase of the regular output terminals of the master and slave flip-flop circuits are inverted from that point on as shown in the right hand portion of the signals :
so~s/~
~ 0 7 9 8ZO
of Figs. 6B, 6C and 6~.
The pulse width of the phase inverting signal shown in Fig. 6D can be selected to have any value within the time region indicated by the broken line in Fig. 6D, provided at least part of the phase inversion signal overlaps with at least part of the time interval t7. Even if impulse noise is superimposed on the phase inversion signal, such noise can be eliminated by the integrating circuit formed by the resistor 14 and the capacitor 15.
When the output signal of the AND gate 13 is raised to -"1" by having a "1" signal applied to both of its input termi-nals, this "l" output signal fed to the base of the transistor 16 through the resistor 17 causes the transistor 16 to become conductive and thereby to drop the level -of the lower input terminal of the AND gate 13 to "0". This causes the output terminal of the AND gate 13 also to become lloll virtually simultaneously. Even if the pulse width of the phase inversion signal is relatively great, and the lower input terminal of the AND gate becomes "1" after the transistor 16 becomes non-conductive as the slave flip-flop 4 is set by the regular input terminal Ql of the master flip-flop l, causing the complementary outpllt terminal Q4 of the slave flip-flop to become "0", the output terminal of the AND gate 13 will be maintained at a 190ll value during the remainder of the period t7. Since both the SET and RESET input terminals of the master flip-10p are maintained at "0" under such conditions, the state of conductivity of the master flip-flop is un-changed during the remainder of the time interval t7.
.
.
~u~4 ~ O 79 ~ ZO
Fig~ 7 shows a schematic circuit diagram representing the block diagram in Fig, 5. The same reference numerals are applied to circuits in Fig. 7 that correspond to cir-cuits in Fig, 5, and the detailed explanation o~ those circuits is therefore abbreviated, An input signal from the input terminal la i~ supplied through a resistor 19 to the base of an NPN transistor 20, The same input signal is also supplied through a resistor 21, which is part of a voltage divider, to the base of a transistor 22, A resistor 23 connected between the base of the transistor 22 and ground constitutes the other part of the voltage-divider, The collector of the transistor 20 is connected to the emitters of two NPN transistors 24 and 25 in the ma9ter flip-flop 1, and the-emitter of the transistor 20 i9 grounded. The collector of the transistor 24 is connected to the ba9e of the tran9i9tor 25 and is also connected through a load resistor 26 to a power supply terminal B+, In like manner the collector of the transistor 25 is connected to the ba9e of the transistor 24 and is also connected to the power supply terminal B+ by way Pf a load resistor 27, The collector-emitter circuit of the transistor 22 is connected in series between the emitters of two NPN transis-tors 28 and 29 and ground. The ba9es of the transistors 28 and 29 is connected to the collectors of the transistor~ 25 .~
and 24, respectively, and the collector9 of the transistors 28 and 29 are connected to the bases of two transistors 30 and 31, which form the active element of the slave flip-flop 4.
.
- . - .
: . . . ~ : .
so~
1~79820 The collector of the transistor 28 is also connected to the collector of the transistor 31 and, through a load resistor 32 to the B+ terminal. Correspondingly, the collector of the transistor 29 is connected to the collector of the tran-sistor 30 and, thrDugh a load resistor 33, to the B+ terminal.
The collector of the transistor 30 is also connected directly to the base of an NPN transistor 34 which is connected as a grounded emitter circuit. The collector of the transistor 34 is connected to the B+ terminal by way of a load resistor 35. The transistor 34 inverts the output signal at the col-lector of the transistor 30.
The phase inversion signal applied to the te~rminal lj passes through the integrating circuit resistor 14 to the base of a transistor 36. The base of the transistor 36 is grounded through the capacitor 15 to achieve the 9 lightly integrating operation of the RC circuit. The collector of the transistor 36 is connected directly to the power supply terminal B+ and ~he emitter of the transistor 36 is connected to ground by way of a resistor 37. The emitter of the tran-sistor 36 is also connected to the emitter of another NPN
transistor 38, the collector of which is connected through a load resistor 39 to the power SUL~P1Y terminal B+. A biasing circuit comprising resistors 40 and 41 is connected to the ~ase of the transistor 38 to establish a reference voltage at that point.
The collector of the transistor 38 is connected to ths base of a PNP transistor 42, the emitter of which is directly connected to the power supply terminal B+. The collector of .~ , 1079~3Z0 the transistor 42 is connected to ground through a series circuit comprising two resistors 43 and 44. The junction between the latter resistors is connected to the base of a transistor 45, the emitter of which is grounded. A resis-tor 46 connects the collector of the transistor 34 to the collector of the transistor 45, and through a resistor 47 to the base of the transistor 16. As shown in Fig. 5, the emitter collector circuit of this NPN transistor is connected directly in parallel with the capacitor 15, The resistor 46 also connects the collector of the transi9tor 34 to the base of an NFN transistor 48 by way of another series connected resistor 49. The collector of the transistor 48 is connected back to the common circuit point of the collector of the transistor 24 and the load resistor 26, The operation of the circuit in Fig. 7 will be explained with reference to the waveforms in Fig. 6, since Fig. 7 is basically only a more detailed circuit drawing corresponding to the circuit diagram in Fig. 5. The input timing signal in Fig. 6A applied to the input terminal la although illustrated as being perfectly square actually has some slope to both the leading and lagging edge of each of the pulses such as the pulse P4, As a result9 the signal applied through the resistor 19 to the base of the transistor reaches the con-ductivity level of that transistor more quickly than the volt-age applied through the attenuation produced by the resistors 21 and 23. The attenuation causes the transistor 22 to become conductive just slightly after the transistor 20, The con-verse is true at the lagging edge of each of the pulses making . .
.
,.
.
.
S~9,84 ~07~8~0 up the timing signal in Fig. 6A; the transistor 22 reaches its cutoff level just slightly before the transistor 20 reaches its cu~off level. It is convenient to call the transition time between cutoff and non-cutoff as a transient condition and to refer to the condition in which the timing pulses are either at their "0" value or their "1" value for a relatively long time ac the steady state condition.
If the phase inversion signal applied to the input terminal 1~ is "0", the transistor 36 will be nonconductive.
By differential operation, the transistor 38 will be con-ductive and produce a voltage drop across the resistor 39 that causes the transistor 42 to be conductive. The current flowing through the base emitter circuit of the transistor 42 also flows through the resistors 43 and 44~ This raises the voltage at the base of the transistor 45 to a "1" value and causes the bases of the transistors 16 and 48 to be at the "0" value, no matter whether the collector of the transistor 34 is a "1" or a "0".
In the time period t2 in Fig. 6, the normal output termi- -nal Ql of the master flip-flop is "0" and the normal output of the slave flip-flop is "1" and both of the transistors 20 and 22 are nonconductive. At the beginning Qf the time period t3 when the input signal in Fig. 6A is rising, the transistor 20 becomes conductive first while the transistor 22 is still nonconductive, thereby causing the transistors 28 and 29 to continue to be nonconductive. This is the transient condition during which the state of conductivity of the flip-flops 1 and 4 is changing, and in this condition as the complementary output
-2~-s08~-~79820 term.inal Ql ~ the master flip-flop is "1", the transistor 25 becomes conductive and the transistor 24 still remains nonconductive. The normal output terminal Ql at the collector of the transistor 25 is ItO" and the complementary output Q
at the collector of the transistor 24 is "1". Slightly later during the transient condition the transistor 22 becomes conductive as the complementary output Ql is "1" and the nor-mal output terminal Ql is "0". Due to the conductivity of the transistor 22 and the signals applied to the transistors 28 and 29 from the terminals Ql and Ql, the transistor 29 becomes conductive and the transistor 28 remains nonconductive.
This is the steady condition during the interval t3. At the beginning of this steady condition, when the transistor 29 is conductive, the normal output terminal Q4 at the collector of the transistor 30 in the slave flip-flop 4 becomes "0" and so the transistor 31 becomes nonconductive, causing the comple-mentary output terminal Q4 at the collector of the transistor 31 to become "1". This condition, in which the transistor 31 is nonconductive and the transistor 30 is conductive lasts until the end of the timing interval t3.
At the beginning of the timing interval t4, when the timing pulse is descending from its "1" value to its "0" value, the transistor 22 becomes nonconductive just ahead of the transistor 20. When the transistor 22 becomes non-onductive the transistor 29 also becomes nonconductive, but since the transistor 28 is still nonconductive, the condition of con-ductivity o the slave flip-flop 4 is not changed and so the normal output terminal Q4 remains at "0" and the complementary .
.. , -S~3~
1~7982~
output terminal Q4 remains at "1".
When the transistor 25 also becomes nonconductive, the transistor 24 in the master flip-flop 1 is still nonconductive and so the current does not flow through the resistor 27 and, therefore, does not flow through the collector-emitter circuit of the transistor 25 any longer. Moreover, as the complementary output terminal Q4 is still "1", the current does not flo~
through the resistor 27 and the base collector circuit of the transistor 28. Therefore, the normal output terminal Ql of the master flip-flop changes from "1" to "O" This causes the complementary output terminal Ql to become "O" because the current fo~lowing through the resistor 26 and the base collector path of the transistor 29, which operates as a reverse transistor under these conditions. This condition lastc until the end of the timing interval t4. A similar operation can be repeated as long as the phase inversion signal is "O" and the transistor 45 is conductive.
When the phase inversion signal is "~", and the comple-mentary output terminal Q4 of the slave flip-flop 4 is "1"
and the complementary output terminal Q~ of the master flip-flop is also "1", and furthermore, when the input timing sig-nal in Fig 6A is "1"~ the conditions correspond to the period t7 in Fig. 6. The transistor 45 can now become nonconductive and, as the transistor 34 is nonconductive so that its col-lector is '11"? the transistors 48 and 16 are able to become conductive. Therefore, the complementary output terminal Ql changes from "1'1 to "0"~ The transistor 25 becomes nonconductiv2 and the ~ormal output terminal Ql changes from 1'oll to "1".
s~34 ~079820 At the same time the transistor 28 is turned on and the transistor 29 is turned off. Then the condition of con-ductivity of the slave flip-flop 4 is changed, and the complementary output terminal Q4 becomes "O" and the normal output terminal Q4 becomes "1". Thus, after the phase in-version signal in the period t7, the phases of the normal output terminals Ql and Q4 are inverted.
While this invention has been described in terms of specific embodiments, it will be understood by those skilled in the art that modifications may be made therein within the true scope of the invention as defined by the following claims.
at the collector of the transistor 24 is "1". Slightly later during the transient condition the transistor 22 becomes conductive as the complementary output Ql is "1" and the nor-mal output terminal Ql is "0". Due to the conductivity of the transistor 22 and the signals applied to the transistors 28 and 29 from the terminals Ql and Ql, the transistor 29 becomes conductive and the transistor 28 remains nonconductive.
This is the steady condition during the interval t3. At the beginning of this steady condition, when the transistor 29 is conductive, the normal output terminal Q4 at the collector of the transistor 30 in the slave flip-flop 4 becomes "0" and so the transistor 31 becomes nonconductive, causing the comple-mentary output terminal Q4 at the collector of the transistor 31 to become "1". This condition, in which the transistor 31 is nonconductive and the transistor 30 is conductive lasts until the end of the timing interval t3.
At the beginning of the timing interval t4, when the timing pulse is descending from its "1" value to its "0" value, the transistor 22 becomes nonconductive just ahead of the transistor 20. When the transistor 22 becomes non-onductive the transistor 29 also becomes nonconductive, but since the transistor 28 is still nonconductive, the condition of con-ductivity o the slave flip-flop 4 is not changed and so the normal output terminal Q4 remains at "0" and the complementary .
.. , -S~3~
1~7982~
output terminal Q4 remains at "1".
When the transistor 25 also becomes nonconductive, the transistor 24 in the master flip-flop 1 is still nonconductive and so the current does not flow through the resistor 27 and, therefore, does not flow through the collector-emitter circuit of the transistor 25 any longer. Moreover, as the complementary output terminal Q4 is still "1", the current does not flo~
through the resistor 27 and the base collector circuit of the transistor 28. Therefore, the normal output terminal Ql of the master flip-flop changes from "1" to "O" This causes the complementary output terminal Ql to become "O" because the current fo~lowing through the resistor 26 and the base collector path of the transistor 29, which operates as a reverse transistor under these conditions. This condition lastc until the end of the timing interval t4. A similar operation can be repeated as long as the phase inversion signal is "O" and the transistor 45 is conductive.
When the phase inversion signal is "~", and the comple-mentary output terminal Q4 of the slave flip-flop 4 is "1"
and the complementary output terminal Q~ of the master flip-flop is also "1", and furthermore, when the input timing sig-nal in Fig 6A is "1"~ the conditions correspond to the period t7 in Fig. 6. The transistor 45 can now become nonconductive and, as the transistor 34 is nonconductive so that its col-lector is '11"? the transistors 48 and 16 are able to become conductive. Therefore, the complementary output terminal Ql changes from "1'1 to "0"~ The transistor 25 becomes nonconductiv2 and the ~ormal output terminal Ql changes from 1'oll to "1".
s~34 ~079820 At the same time the transistor 28 is turned on and the transistor 29 is turned off. Then the condition of con-ductivity of the slave flip-flop 4 is changed, and the complementary output terminal Q4 becomes "O" and the normal output terminal Q4 becomes "1". Thus, after the phase in-version signal in the period t7, the phases of the normal output terminals Ql and Q4 are inverted.
While this invention has been described in terms of specific embodiments, it will be understood by those skilled in the art that modifications may be made therein within the true scope of the invention as defined by the following claims.
Claims (9)
OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A master-slave flip-flop circuit for producing a rectangular wave output signal comprising:
a first input terminal to which a timing signal is applied;
a master flip-flop circuit having input terminals and output terminals;
a slave flip-flop circuit having input terminals and output terminals;
a master-slave output terminal connected to one of said slave flip-flop output terminals for delivering said rectangular wave output signal;
gating means for connecting said output terminals of said master flip-flop circuit to said input terminals of said slave flip-flop circuit and for connecting said output terminals of said slave flip-flop circuit to said input terminals of said master flip-flop circuit;
said first input terminal being connected to said gating means to control the operation thereof with the assistance of output signals from said output terminals of said master flip-flop circuit;
a gating circuit, separate from said gating means and having a connection to one of said output terminals of said slave flip-flop circuit, said gating circuit further being connected to one of said input terminals of said master flip-flop circuit to assist in controlling the operation of said master flip-flop circuit; and a second input terminal to receive signals to produce phase inversion of the rectangular wave output signal of said master-slave flip-flop circuit, said second input terminal being connected to said gating circuit to cooperate with said con-nection to said one output terminal of said slave flip-flop circuit in controlling the operation of said gating circuit to achieve controlled phase inversion of the signals at said output terminals of said slave flip-flop circuit.
a first input terminal to which a timing signal is applied;
a master flip-flop circuit having input terminals and output terminals;
a slave flip-flop circuit having input terminals and output terminals;
a master-slave output terminal connected to one of said slave flip-flop output terminals for delivering said rectangular wave output signal;
gating means for connecting said output terminals of said master flip-flop circuit to said input terminals of said slave flip-flop circuit and for connecting said output terminals of said slave flip-flop circuit to said input terminals of said master flip-flop circuit;
said first input terminal being connected to said gating means to control the operation thereof with the assistance of output signals from said output terminals of said master flip-flop circuit;
a gating circuit, separate from said gating means and having a connection to one of said output terminals of said slave flip-flop circuit, said gating circuit further being connected to one of said input terminals of said master flip-flop circuit to assist in controlling the operation of said master flip-flop circuit; and a second input terminal to receive signals to produce phase inversion of the rectangular wave output signal of said master-slave flip-flop circuit, said second input terminal being connected to said gating circuit to cooperate with said con-nection to said one output terminal of said slave flip-flop circuit in controlling the operation of said gating circuit to achieve controlled phase inversion of the signals at said output terminals of said slave flip-flop circuit.
2. The master-slave flip-flop circuit of claim 1 in which said slave flip-flop has a normal and a complementary output terminal, and said complementary output terminal is connected to said gating circuit.
3. The master-slave flip-flop circuit of claim 1 further comprising an OR gate having an output terminal con-nected to one of said input terminals of said master flip-flop circuit and first and second input terminals connected, respec-tively, to said gating means and to said gating circuit.
4. The master-slave flip-flop circuit of claim 3 in which said gating circuit comprises:
an AND gate having a first AND gate input terminal con-nected to one of said output terminals of said slave flip-flop circuit and a second AND gate input terminal; and means connecting said second input terminal to said second AND gate input terminal.
an AND gate having a first AND gate input terminal con-nected to one of said output terminals of said slave flip-flop circuit and a second AND gate input terminal; and means connecting said second input terminal to said second AND gate input terminal.
5. The master-slave flip-flop circuit of claim 4 in which said last-named means comprises an integrating circuit that includes a capacitor connected between said second AND gate input terminal and a constant voltage point.
6. The master-slave flip-flop circuit of claim 5 in which said gating circuit further comprises a transistor having its emitter-collector circuit connected in parallel with said capacitor and its base connected to the output of said AND gate.
7. The master-slave flip-flop circuit of claim 1 in which said gating means includes first and second pairs of AND gates, said first pair of AND gates being connected between said output terminals of said master flip-flop circuit and said input terminals of said slave flip-flop circuit and said second pair of AND gates being connected between said output terminals of said slave flip-flop circuit and said input terminals of said master flip-flop circuit.
8. The master-slave flip-flop circuit of claim 7 in which said first input terminal is connected to an input of each of the AND gates of said first and second pairs of AND gates.
9. The master-slave flip-flop circuit of claim 1 in which each of said master flip-flop input terminals is coterminous with a separate master flip-flop output terminal and each of said slave flip-flop input terminals is coterminous with a separate slave flip-flop output terminal.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP51009157A JPS5813045B2 (en) | 1976-01-30 | 1976-01-30 | Master-slave flip-flop circuit phase inversion circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1079820A true CA1079820A (en) | 1980-06-17 |
Family
ID=11712774
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA270,682A Expired CA1079820A (en) | 1976-01-30 | 1977-01-28 | Master slave flip-flop circuit |
Country Status (7)
| Country | Link |
|---|---|
| JP (1) | JPS5813045B2 (en) |
| AU (1) | AU514388B2 (en) |
| CA (1) | CA1079820A (en) |
| DE (1) | DE2703903C2 (en) |
| FR (1) | FR2339995A1 (en) |
| GB (1) | GB1532764A (en) |
| NL (1) | NL7700996A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4591737A (en) * | 1982-12-13 | 1986-05-27 | Advanced Micro Devices, Inc. | Master-slave multivibrator with improved metastable response characteristic |
| JPS59190713A (en) * | 1983-04-13 | 1984-10-29 | Agency Of Ind Science & Technol | Josephson logical circuit |
| SE505963C2 (en) * | 1993-02-25 | 1997-10-27 | Nitro Nobel Ab | Method for loading boreholes with explosives |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3454935A (en) * | 1966-06-28 | 1969-07-08 | Honeywell Inc | High-speed dual-rank flip-flop |
| NL6805036A (en) * | 1968-04-09 | 1969-10-13 | ||
| GB1399523A (en) * | 1971-06-22 | 1975-07-02 | Matsushita Electric Ind Co Ltd | Colour television receiver |
| GB1461443A (en) * | 1973-02-06 | 1977-01-13 | Sony Corp | Bistable multivibrator circuit |
| JPS5524313B2 (en) * | 1973-08-10 | 1980-06-27 |
-
1976
- 1976-01-30 JP JP51009157A patent/JPS5813045B2/en not_active Expired
-
1977
- 1977-01-28 GB GB355977A patent/GB1532764A/en not_active Expired
- 1977-01-28 CA CA270,682A patent/CA1079820A/en not_active Expired
- 1977-01-31 FR FR7702643A patent/FR2339995A1/en active Granted
- 1977-01-31 NL NL7700996A patent/NL7700996A/en not_active Application Discontinuation
- 1977-01-31 DE DE19772703903 patent/DE2703903C2/en not_active Expired
- 1977-02-01 AU AU21841/77A patent/AU514388B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| FR2339995B1 (en) | 1982-09-03 |
| DE2703903C2 (en) | 1985-10-17 |
| AU2184177A (en) | 1978-08-10 |
| NL7700996A (en) | 1977-08-02 |
| AU514388B2 (en) | 1981-02-05 |
| FR2339995A1 (en) | 1977-08-26 |
| DE2703903A1 (en) | 1977-08-04 |
| JPS5293259A (en) | 1977-08-05 |
| JPS5813045B2 (en) | 1983-03-11 |
| GB1532764A (en) | 1978-11-22 |
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