CA1070437A - Semiconductor integrated circuit device composed of insulated gate field-effect transistors - Google Patents

Abstract

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
COMPOSED OF INSULATED GATE FIELD-EFFECT TRANSISTORS

Abstract of the Disclosure In a semiconductor integrated circuit device composed of insulated gate field-effect transistors, the improvement comprising the facts that the insulated gate field-effect transistors having gate insulating films of substantially equal thicknesses are arranged on a principal surface of a semiconductor substrate in the shape of a matrix, that gate input columns of the transistors are formed of polycrystal silicon layers, and that some of the transistors are made the enhancement type, while the others are made the depletion type. Further, the respective transistors are formed by the self-alignment technique which employs the polycrystal silicon layers as a diffusion mask, and the depletion type transistors arc formed by implanting impurity ions opposite in the conductivity type to the substrate into selected areas of the surface of the substrate. Thus, a read only memory in a MOS-IC chip has its occupying area reduced remarkably.

Description

-` 1070437 r Back~rou_~(l ot tl!e lnvention (I) Field of the Invention Tllis invention relates to an integrated circuit device compoæed of insulated gate field-effect transistors (hereinbclow termed "MOSIC") and also to a method of manu-facturirlg tlle same.

(2) Description of the Prior Art In general, t11e ~IOSIC uses alumilium or silicon as tlle material of a gate electrode. On tlle other lland, there are known integrated circuits (IC) in wllicll, in an inverter stage forming one internal circuit thereof, a load MOSFET of the enhancement mode is employed as the load of a driving ~IOSFET operative in the enhancement mode (hereinafter called "E/E type IC") and the IC in which a load ~IOSFET of tlle depletion mode is employed (hereinafter called "E/D type IC").
Among the IC's, the silicon gate MOSIC employing the depletion load has recently come into extensive use as a device which is of higher performance for various uses and has a higher density of integration than the aluminum gate ~IOSIC. According to experiments by the inventor, the occupying area of an Si gate ~IOS transistor having a self-aligned gate structure is reduced by approximately 20 to 30% as compared with that of an Al gate IIOS transistor.
As the result of the investigation of ~IOSIC's commercially available as produced by several manufacturers, however, it has been found that, in a read only memory (here-inbelow abbreviated to "ROM"~ wllicll occupies a considerable part of a ~IOSIC chip, the size of the single bit of the RO~I
is not always significantly smaller in tlle conventional Si gate ROIS structure than in the Al gate one as indicated in the following Tahle 1:

Table 1: Comparisons of ROM bit sizes ._ _ _ IC manufacturer Si ~te ROM Al gate ROM type of IC
A _ ~m 336 ~m dynam~c type ~ ~ ~1 6 Summary of the I~vention It is accordingly the prlncipal object of this invention to provide a novel ROM structure which is conspi-cuously smaller in occupying area than the prior-art Al gate or Si gate ROM's, and a method of manufacturing such novel :i ROM structure.
Another object of this invention i8 to provide an IC in which the occupying area of a ~OM per unit function ~n the prlor-art MOSIC of the Si gate E/D type i8 conspicuously dlminished, and 8 method of manufacturing such IC.
According to one aspect of this invention, there is provided a method of manufacturing a semiconductor integrated circuit device comprising the steps of: ~a) forming a first insulating layer on the surface of a semiconductor substrate of a first conductivity type, said first insulating layer having relatively thin and relatively thick portions; (b) selectively introducing impurities of a second conductivity type, opposite said first conductivity type, into precribed surface portions of said substrate beneath selected areas of relatively thin portions of said first insulating layer; (c) sel-ectively forming polycrystalline silicon layers on at ~070437 least spaced apart areas of the relatively thin portions of said first insulating layer some of which silicon layers overlie said prescribed surface portions of said substrate; and (d) introducing further impurities of said second conductivity type into selected regions of the surface of said substrate between adjacent ones of said silicon layers by using said silicon layers as a mask to form a plurality of regions of said second conductivity type in the surface of said substrate.
Other aspects of this invention are claimed in our Canadian patent application Serial No. 240,274 filed on November 24, 1975, of which the present application is a division, and in other applications divided therefrom.
According to another feature of the invention, at least in preferred forms, the respective tran-sistors are formed by a self-alignment technique which employs the polycrystal silicon layer as a - 2a -r diffusinn mask. The depletion type transistors are formed by implantin~ impl)rIty ions opposite in conductivity type to tl1e substrate into selected areas of the surface of the substrate.
Brie Description o tl1e Drawin~

.
FlG. 1 is a fundamental circolt diagram of a prior-art MOSRO~1, FI(;s. 2(a~ and 2(b) are enlarged plan and sectional vicws of a part of tl1e prior-art MOSROM, respectively, FIG. 3 is a fundamental circuit diagram of a ~lOSROM
according to this inve11tion, FICs. 4(a) and 4(b) as well as 4(c) are enlarged ; plan and sectional views of a part of the MOSRO~I according to this invention, respectively, FIG. 5 is a diagram of a circuit which uses the MOSRO~I according to this invention, FIGs. fi(a) to 6(f) and FlGs, 7(a) to 7(d) are enlarged sectional views and plan viewso a part of t11e ~IOSROM
accordlng to this invention for explaining a manufacturing process of the ~IOSROM, respectively, FlGs. 8(a) and 8(b) are top pattern diagrams of LSl chips of a MOSLSI utilizing this invention and a ~IOSLSl fabricated by a prior art technique for making a comparison-therebetween, respectively, and FI~. 9(b) is a diagram showing an example of a circuit in the case of actua1ly employing the ~10SRO~ of this invention, while FI~.. 9(a) is a graph showing the measured results of operating speeds in the circuit of FIG. 9(b).
Description of the Preferred Embodiments . 30 }~ereunder the improved ROM (MOS matrix) accnrding to this invention will be descrihed in detail in comparison with a prinr-art ~i ~ate RO~I with refercnce to ~he drawings.
FIG. 1 shows the fundamental circuit which is used ln the prior-art Si gate ROM. FIG. 2(a) is a plan view showing a part of the prior-art Si gate RO~I on an enlarged scale, while Fll;. 2(b) is a sectional view of the part of the prior-art Si ~ate ~IOSROr~ as taken along a linc X - ~' in FlG.
2(a).
~ s illustrated in FIC. 1, the prior-art Si gate MOSRO~I consists of ~lOSFET's which are arran~ed in parallel.
The states of the respective memory cells are discriminated by the thLcknesses of gate oxide films. ~ signal of low level close to a supply voltage is applied to a selected address line, whereas a signal of high level close to 0 (zero) volt is applied to an unselected address line. Considering by way of example a case where a line IN2 is selected, the PIOSFET
underlying tllis line has a thick gate oxide film and is usually "off," so that tlle output level becomes the low level. ~s shown in FIGs. 2(a) and 2(b), such prior-art ROPI
ls constructed of P -type diffused layers 2, 3 and 4; poly-crystal silicon layers 7 and 8; silicon dioxide films 5 and6; phosphosilicatc glass 9; a through-hole 11; and an alumlnum layer 10. The polycrystal silicon layer is used as an address input line, while the aluminum layer is used as an output line. The through-lloles between the Al layer and the P -type diffused layers are necessary for commonly connecting the drain electrodes of the PlOSFET's whicll are arranged at each row. As apparent from the figures, the states of the memory cells at Ll-e points of intersection ~etwecn the input lines and the Outpllt lincs are determined by the thicknesses of the gate oxide films. ~lore specifically~ where the ~IOSFET which conducts the "on-of r" operation by the signal voltages ~pplied to th~ input line i8 necessary at a cePtain point of intersection, the gate oxide film beneath the polycrystal Si layer at that place is made thin, while at the place where the MOSFET which conducts such oper~tion is unnecessary, the ox~de operation is unnecessary, ~ha oxido film beneath the poly-cry3tal Si l~yer at that place i8 mads thick. Thus, the ROM
ha~ing a prsdetermined bit pattern i8 constructed. The mini~u~
siee per unit bit of th~ Si gate RO~ of such con~truction i~
about ~10 ~m2, and it i8 substAntially equal to that of the Al g~t~ ~O~.
A~ de~cribed abovo the con~entional ROM i8 character-lzed by the foll-wi~g con~truction:
(1) The ~tate3 of ~he re~pdctive me~ory cells are dis-tinæuish~d b~ the thick~es3 of the gate oxide fi 1~8.
( 2 ) Since the self-aligned gate 3tructure i~ adopted, the polycrystal Si layer cannot cro~ o~or the p+-type diff~sed layer. Thorofore, the Al wiring layer i8 ~eces~itated, and the through-hole i~ required between the p+-type diffused la~er and the Al layer.
Accordingly, the occupying area per bit of the prior-art S1 gate ROM cannot be ~ dc 81t2all in ~pite of the ad~ptian of the ~elf-aligned structure.
The S~ gate ~OSROM according to this isvention will now be sxplained with reference to Fig. 3, Figs. ~(a), 4(b) and ~(c), and Fig~ 5.
Fig. 3 ~hows the ~unda~ntal circuit wh~ch i~
~pl0yed in the R~M accor~ing to th~s i~ve~tion..It is compo3cd of a plurallty of enhanc~e~t ~ode and depletion mode MOSFET's which are connect~d in ~erle~ as ~riving elements~ The deple-tion mode MOSF~T functions al50 as one resistance element. A
read-out i8 ~tably executed in such way that a 8i gnal of h~gh 10 70 ~3 7 level clo~e to O (zero) volt i~ impres~ed on a selected address line. At thiY time, a signal of low level is impressed on a~
un~elccted address line.
By way of exampl~, in case where the address line ~N
i~ sel~cted, the ~OSFET und~rlying this ~ddress line IN turns ~on~ as it i~ the depletion modo MOSFET, Since the MO~FET's associat~d with the othar addr~ss line~ IN , IN ,.... and IN
1 3 n are the enhancem~nt mode MOSFET's, they turn "on" by haYing th~
low lsvel signal applied to their gates. Since the MOSFEr a~30ciated with the ad(lre~s line IN i~ the depletion mode n-l MOSF13T, it i "on" even when the low level slgnal i8 applied to its g~te. In this case, ~ccordingly, all tho driving ele~nt~
are ~ubstantially "on, n so that an output signal of high level close to O (zero) olt i8 produced at an output termir~al OUT.
On the other hand, in cas~ where the address line IN
ia selected, the MOSFET as~ociated with thl3 line becomes the nonconcuctive (oîf) state by the input slgaal of high level as it operate3 in tha enhancement mod~. Therefore, an output signal of low l~rol appears at the output termin;ll OUT.
As apparent fro~n the abo~e explanation, in the ItOM
according to thi~ invention, the output dat~ line to be pre-¢harged hold~ the lo~r le~lrel or i~ shifted to the high level in depe~d~nce on wh~ther the enhancem~nt or d~pletion mode M~SFET
i8 addressed, re~pectivelr.
Fig. 5 shows a ROM circuit which is const~ucted by ~pplying this inv~ntion to a~ actual RO~ of MOSIC on the basis of the funda~ental c~rcui'c of the ~n~rantion illu~trated in Fig, 39 and whlch comprlse~ the fir~t ~ddre~s decoder 2~0S matrix and the sec3Rd MOS matrix recei~ing an oatpat o~ the first ~IOS
~natrix a~ it~ input. A flip-flop eircu~ t 21 eonslsts of a plural~ ty of stages (for example, k/2 stages~ c-nne~ed in ~0'7~ 3'~

cascade. G~tputs from the respective stage~ are deli~,rer~d dlre~tly or through inverter circuits 22 into the first MOS
natrix 23, whoso output~ are doll~ered i~ato the second MOS
matrix 2~. The ~econd ~OS m~trix provides output 8 OuT 1- to OUT n. The matricas 23 and 24 have one MOSFEr operative in the depletion or enhancement ~ode in any of the place~ ia ~hich input lines and output lines lntere~oct~ Such FET ' s are connected in series between a supply voltage F ard a reference potential eource (earth) at every column, Connected to the respective matrices a~ load~ of the driving MOSF~'s are enhancament Dlode MOSFET'~ (27, 2~) which ~javo clock ~ignals appliod to the gates thereof. In the figure, tho driving MOSFhT's with circles as indicat~ at 25 are those operating in the depletlon modo, while the other driving MOSFEr'3 are those operating in the enhancement mode. Each Or the plurality of inverters 22 consits of a driving MOSFET
which operates ln the enhancement mode, and a load MOSFET
which is conn~cted in ~eries ther~with ~nd whl~ operate~
in the depletion mode. As will be ~tate~ later, all the MOSF13:Tts in the flgure have gat~ insulatlng film~ (for e~camplo, 8iO films) of substantially equal thlchnesse~ (about 500 to 1,500 angstrom~) lrre3pectlvo of the depletlon mode or tho enhance1nent mode. The depletlon MOSFET~ in the MOS
matrice~ are formed simultaneou~ly with the depleti3n MOSFET~ in tho in~erter~ 22 by quite an identical prGces~.
The i~put line~ of the first and s~cond matrices are for~ed Or polycr~st~l silicon wiring layers, while the connectlon from the output line of th~ ~irst matri~ to the i~put line of the second matr~x l~ p~rformed by th~ u~e of an alur~nu~
wiring which ~onnects a p~-type diffu~ed layer and the poly-crystal Si layer. Wh~n FIG. 5 is studi~d ~ith reference to lO'~V ~7 FIG~ 3, the operation of ~he circuit in FIG. 5 will b~ self-explanatory. To be particularly mentioned i8 that clock pulses ~ and ~ whose phases differ from each other are impressed on the gates of the load ~OSFET's ~n the first and ~ec-nd matricos, respectively, and that the amplitudes Or the~e pulses ~for example, -12 to -16 volts) are greater han the ampl~tude of the supply voltage ~ (for example, DD
-6 volts).
Referring now to FIGs. 4(a), 4(b) and 4(c), these deYice stru~turo of the MOSRO~ according to this lnvontion will be describsd. FIG~ 4(a) is a plan vie~ with a part of the MOSROM enlarged, ~hile FIGs. 4(b) and ~c) show X - X' and Y - Y~ ~ections in FIG. 4(a~, respecti~lr. In the figures, nu~eral 31 designates an N-type 8i~gle c~y3tal Si sub~trate; numerals 32 to 3~ and numerals ~7 to ~9 p~-type diffu~ed layers which are formed by being self-aligned by Si gate electrodes; numerals 35, 36 and 43 ga~e insulating films of sillcon dloxi~e which have es~entially equal thick-~ `0 ness~ (about 1,000 A); nu~erals 37 and 3~ input lines of polycrystal Si; nu~eral 39 an insulating fllm of phosphosili-cate glas~; numsrals ~1 and 42 P-type channel layers whi~h ar~ ~or~ed by i~plant~ng P-type impurity ions into selected area~ of the ~urface of the substrate in order to form the deplotion M~SFETls; and numeral~ 44 to 46 ~ield insulating films of s~licon dio~id~ wh~ch are c~mparatively thic~
(about 1 to 2 u). A~ apparent from the fig~res, one memory cell is formed i~ any of the places of intersection between the polyc~ystal Si wiring layers (37, 3~) as the addre~s input lines and the P~-type diffu~ed layers as the sol~-connected data output l~n~. The states of the respectivo memory cells are determ~ned by the pre3ence or abs~nce of tl~e l'~ c ~ el [ormed hy tl-e ion implant~-ttion. ~11 the memory cells ha~e the thin gate oxidc films so as to operate as the enhancement or depletion MOSFET.
As seen rom the figures, the llOS matrix according to this invention has the self-aligned gate structure and needs no throlJgll-llole. It is therefore understood that tlle occupying area to the single bit is remarkably smaller in the ~IOS matrix of this invention than in the prior-art one.
FlGs. fl(a) and 8(b) show by comparison the semiconductor chip sizes and the occupying areas of respective circuits in the cases wherc ~IOSIC's for acllieving the same circuit function are formcd by the technique of this invention and by tl)e Si gate MOS manufacturing technique of tlle prior art, respectively. By the adoption of the MOS matrix according to this invention, in comparison Witll the case of adopting the mere self-aligned type Si gate ~IOSRO~I, the RO~I part which occupic.s a comparatively large area in the LSI is reduced by approximately 50~. ~s the result, it becomes possible to lessen the whole chip size by approximately 20%.
The operating speed of the ROM according to this invention will now be explained with reference to FIGs.
9(a) and 9(b). Since a ratioless circuit as shown in FIG.
9(b) is employed, the output level of the RO~I has two states, and as previously set forth, the precharged data line holds the low level or is shifted to the high level.
In this case, the operating speed of the RO~I is mainly dependent upon the discharge time td in wllich the pre-char~ed d~-tta line is shifted to the high level. FIG. 9(a) illustrates the measorements of the relationship between the discharge time of the MOSROM shown in FIG. 9(b) (the axis of ordinates, t~) atld tlle amplitude of the clock pulse supplied to the ~ate n~ the load ~IOSFET ol the enhancement mode (the axis oF al>scissas, V ), the MOSRO~I possessing 48 address lines and havillg 48 enl-ancement or ~epletion ~IOS~ET's con-nected in series. Herein, the output capacitance of the RO~
is made approximately 1.5 pF. ~s seen from the graph, the discharge time is smaller than 1.5 Us. Especially as an IC
for an electronic desk top calculator, essentially no pro-blem is posed in practical use because an operation in the order of 100 Kl~ is possible.
Description will now be made of a mcthod of manu-facturing the ~IOSRO~I according to this invention as shown in FIGs. 4(a) to 4(c) and FIG. 5, reference being had to FIGs.
6(a) to 6(f~ and FIGs. 7(a) to 7(d). First, an SiO2 film being about 1.4 ~ tllick is formed in the surface of an N-type Si single crystal substrate 31 whose one principal surface is the (1 1 l)-face and wllich has a specific resistance of ! s to 8Qcm. Thereafter, those parts of the SiO2 film on the principal surface of the substrate at which the IIOSFET's are to be formed are removed in the sllape of narrow slots. The exposed substrate surface is oxidized to form a thin SiO2 film 30 (gate oxide film) of about 1,200 ~ there (refer to FIGs. 6(a) and 7(a)). Subsequently, boron ions are implanted .
into tlle substrate surface through tlle thin SiO2 film 30 at a concentration of about 1.4 x 101 k/cm . Further, a photoresist material layer 50 i9 deposited onto that part of ; the thin oxide film 30 on tlle substrate surface at which the depletion ~lOSFET is not to be formed. Using the photoresist layer and the thick oxide film as a mask, boron ions are again implanted into the substrate surface through the exposed tllin SiO2 film at a concentration of 6.5 x 10 k/cm .
Thus, the P-type region 41 which constitutes tlle channel of -- I (3 --tl~e n-rlOSIr:l` is f~rme(l (refer ~ Fl~s. 6(l)) ancl 7(b~).
Subsequently, the pl~otoresist layer Ls re~ovcd. Polycry-stal sillcon is deposited on the entire oxide films to the extent of about 5,000 ~. Those parts of the polycrystal Si layer whicll are other than parts for constructing the address lines (37, 38) are removed treEer to FIG. 6(c)).
Subsequently, using the parts 37 and 38 Or the polycrystal Si layer left bellind, the thin SiO2 film 30 is removed to expose the suhstrate surface (reEer to FI~s. 6(d) and ~(c)).
Subsequently, by employing the polycrystal Si layer 37, 38 and the thick SiO2 film 40 as a mask, boron is diffused into tlle exposed substrate surface by the conventional vapor dif-fusion process. Th~s, the P -type diffused regions 32, 33, 34, 47, 48 and 49 having a thickness of about 0.8 ~ are formed ~refer to FIGs. 6(e) and 7(d)). Thereafter, the phosphosilicate ~lass (PSG film) 39 having a thickness of about 0.9 to 1 ll is deposited from vapor, to finish the llOSROM as sllown in FIG. 6(f). In this way, there is produced the ~OS matrlx of the present invention as comprises the combination of the enhancement mode and depletion mode ~IOSFET's having the gate oxide films of substantially equal thicknesses. As described above, in the ~lOS matrix of this invention, the re-spective input lines of the polycryst?l Si and the respective P -type diffused layers intersect sub-stantially orthogonally, and all the insulating films under the polycrystal Si layers in any place of the intersection ~,; are made the equal thic~ness of about 1,200 ~, so that the t;ansistor operation is positively carried out. I~hich transistors are ma~e the depletlon type is determined by the implantation of tlle boron ions as illustrated in FIG. 6(b).
Such technique of abricating the deplction MOSFET's is not ~070437 espcci.llly ad~le(l~ but in case of formin~ the circuit as shown in FlG. 5 or FIG. 9tb) within the surface of a single - -semiconductor substrate, the aforecited ~IOSFET's are fabri-cated by the same process as that of the other depletion ~IOSFET's, for example, the depletion load ~IOSFET's of the inverters.
To sum up, the RO~l according to this invention has the followin~ features:
(1) The ROM of this invention is constituted of the cnllancement type and depletion type ~IOSFET's as the driving elements.
,~
(2) The size of the ROI~I of this invelttion is remarkably small, and i,t is reduced by about 50%
as compared with that of the RO~I oE tlle prior-art Si gate structure.

(3) I'he RO~l of this invention is fabricated by a proccsfi wllicll is compatible witll the Si gate ~IOSLSI
employing thc depletion loads as is presently being used extensively.

(4) The cascade ratioless circuit is applicable to the RO~I of this invention, and LSI's with extra-ordinarily excellent cllaracteristics can be realized by paying sufficient attention to the estimation of the operating speed.
The idea of this invention as stated above can also be applied to other complicated logical circuits such as a programmable logic array and a four-phase ratioless dynamic circnit. It is accordingly to be un~erstood that the scope of right o~ the present applicatioll is not restricted to the foregoing specific aspects of performance.

Claims (3)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A method of manufacturing a semiconductor integrated circuit device comprising the steps of:
(a) forming a first insulating layer on the surface of a semiconductor substrate of a first conductivity type, said first insulating layer having relatively thin and relatively thick portions;
(b) selectively introducing impurities of a second conductivity type, opposite said first conductivity type, into precribed surface portions of said substrate beneath selected areas of relatively thin portions of said first insulating layer;
(c) selectively forming polycrystalline silicon layers on at least spaced apart areas of the relatively thin portions of said first insulating layer some of which silicon layers overlie said prescribed surface portions of said substrate; and (d) introducing further impurities of said second conductivity type into selected regions of the surface of said substrate between adjacent ones of said silicon layers by using said silicon layers as a mask to form a plurality of regions of said second conductivity type in the surface of said substrate.

2. A method according to claim 1, wherein step (b) comprises the step of implanting ions of said second conductivity type into said prescribed surface portions of said substrate.

3. A method according to claim 1, wherein step (d) comprises the step of diffusing said further impurities of said second conductivity type into said selected regions of said substrate using said silicon layers.