CA1066816A - Impact sound stressing for semiconductor devices - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE
Methods of making semiconductor devices using the technique of impact sound stressing are disclosed. Impact sound stressing (ISS) is a mechanical acoustical technique to damage, in a known and controlled manner. semi-conductor wafers. Wafers are subjected to ISS on the backsides before semi-conductor processing steps. The application of ISS before the first high temperature application with control the generation and subsequent direction of flow (gradient) of vacancies (interstitials) generated through all device high temperature processing steps including ion implantation. ISS redirects the flow of vacancies/interstitials into the backside away from the device area of the wafer. Thus, the device area is swept clean in a gettering action of vacancy/interstitials and their complexes which are detrimental to device performance. The techniques of impact sound stressing finds application in improvement the performance of all semiconductor devices, specifically dynamic memories, bipolars, solar cells and power devices.

Description

1066B~6 Field of the Invention .
This invention relates to a method of making semiconductors.
Prior Art The fabrication of semiconcluctor devices involves the application of high temperatures to silicon wafers and this step is known to pro-vide stresses across or through the wafer. The relief of stresses, thereby controlling the generation and subsequent direction of flow of vacancies (interstitials) in the lattice structure, has been a sub-ject of interest in the prior art. The mechanical damaging of a wafersurface has been propused as a means of "gettering" impurities within a wafer. It has been recognized that if the surface, generally op-posite the side where device processing will occur, is appropriately damaged, the gettering effect will sweep the device area clean of ~acancy/
interstitia1s and their complexes including stacking faults and dislo-cations which are detrimental to device performance. While the problem has been defined, the solutions to-date have been unsatisfactory. Fûr example, Netz in J. Electro Chemical Society, 112, 420 (1965) suggests ;
the application of sand blas-ting as a technique o~ inducing backside surface damage to improve semiconductor yields. This technique has not found practical application because non-uniform results in terms of damage patterns are the inevitable consequence of sandblasting. Also, Lawrence in Semiconductor Silicon 1973, pg. 17, references a getter-ing technique by means of generating fresh lattice damage as a result of mechanlcal lappina. This proposal is also not useful in a manufacturing system because the results are not easily reproduced and it cannot be applied on a volume basis to a large Fl9-7~-020 2 -.
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j 1066816 number of wafers.

2 In addition to these difficulties, the primary shortcoming in the prior

3 art i~ that the degree of damage in terms of depth cannot be controlled. A

4 a xesult, di~locations created on wafer back~3ides by mechanical action propagate through the wafer upon high temperature a~plication onto the device 6 surface$ thu~ destroying the device. Hence, while improvement in yield 7 ratios wa6 predicated analytically, incon~iatent and di~appointing results are 8 ~he practical consequences of these prior art techniques. A~ a result, semi-9 conductor technology has not been able to prov~de the wafer manufacturer wil~h a reliable technique of impraving yield ratios.
11 A related problem in the prior art is the generation of a high den3ity 12 of oxidatio~-induced staclcing faults in ipitaxial silicon. It ha~ generally been 13 a~sumed that epitaxial silicon was free frorn mechanical damage; however, 14 recent experiments [C. M. Dxurn and W, van Gelder, ~ ~e~, 43, 11, lS 4465 ~1972); C.M. HsiehandD.M, Maher, J. ApE~LPhys., 44, 3, 1302 ~}973) ]
16 ha~e, using preferential etching of the oxidized epi, demonstrated the 17 existence of stacking fault~ in the structure. The generation lifetime of the 18 epitaxial layers is in most ca9e9 ~everal order~ oE magnitude lower than 19 ~hat of CZ-grown substrates ~P, Rai-Choudhury and D.K, Schroder, J. Electrochem. Soc,, 119,11, }580 (1972)}. These experiments have al90 21 pointed out that in ~pite of high ~tructural perfection of epitaxial silicon, p-n 2Z jlmctions involving epitaxial ~ilicon give either high-re~rerse leakage current Z3 I or exhibit considerably lower junction breakdown voltage than diffused junc 24 ¦ tions in GZ-grown silicon. Improvernent in the generatio~ lifetimes of the~e ¦ deviceq ib an important con~ideration a~d heretofore iodine e~ching before 26 ¦ epitaxial proces~ing wa~ a common technique to remove a portion o the ~27 bilicon surfaceO Etching i~, however, an expen~ive and time consurning pro-Z8 ceB~ and dC)~ab not guarantee the desixed improvement in eE~ita~sial layer ;~9 perfection.
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Fl ~9-75-020 ~ -3-:, : . . . -~ ` 1C~6t~8~L~i This invention uses -the technique of impact sound stressing as an inte~ral proce~siny step in the production of semiconductor de-vices. Impact sound stressing, in its most basic form, involves the acoustic vibration of spherical objects on the waFer surface to mechani-cally damage the wafer. In U.S. patent 4,004,449 of ~chwuttke and Gorey, entitled "Impact Sound Stressing for Semiconductors", issued January 25, 1977, the basic structure and analysis of impact sound stressing is presented. That patent uses impact sound s~ressing to produce, in a known and duplicative manner, damage to the surface of silicon to study and predict the effects of stacking faults, disloca-tiolls, etc., on device processing. Irl particular, Schwuttke and Gorey use imPact sound stressing as a laboratory tool for the accurate analysis of the physical properties of semiconductors by imparting uniform damage to the wafer surface designated for device processing.
This invention uses impact sound stressing as an integral process step in the fabrication of semiconductor devices. The use~of ISS on the backside of ~afers, that is, the side opposite the one onto which de-vices '.!ill be applied, serves to create a ~ettering effect in the crystal which redirects the flow~of interstitials (vacancies) which are generated throughout all device high temperature processing steps. The re-direc-tion of this flow into the backside of the wafer "sweepsl' the device area clean ~ interstitials (vacancies). As a result, lifetime in the device area is improved and pipe formation in the presence of multiple junctions is minimi2ed.
Accordingly, it is an object of this invention to provide a method for improving semiconductor performance by the use of impact sound stressing.
It is another object of this invention ~o provide a technique for ; achieving the uniform damaging of wafer backsides to control the genera-6~8~
1 tion and movement of interstitials (vacancies) in the wafer during hiyh temperature processing.
It is yet another object of this in~ention to provide a reliable and reproducible means of damaging wafers without subsequent propaga-tion of damage during high temperature processing.
Still another object of this invention is l:he creation of a new class of semiconductor substrates having uniform backside damage.
These and other objects of the invention and a full understanding may be had by reFerring to the following description and claims taken in conjunction Witll the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 sho~s a schematic series of wafer sections portraying the ; -basic steps of this invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
The basic implementation of impact sound stressing is ciisclosed in the related U.S. patent 4,004,449 of Schwuttke and Gorey ancl the struc-ture need not be described here. Essentially, the technique involves f .. .
the placement of a ~a-Fer in an acoustical relationship with a loud-speaker and a series of pellets, normally of spherical configuration, are placed on the surface to be damaged. The loudspeaker is driven at a suitable power level and frequency, usually the resonant frequency of the wafer, causing the wafer to vibrate in a harmonic mode. As a con-sequence, the pellets bounce on the surface, the magnitude of the boun-cing being a function of the power level. The pellets are typical,y tung-sten about 30D ~m in diameter, and any convenient number may be used.
By varying the time, power and number of pellets, uniform and repro- -ducible damage patterns can be created. The damage is in the form of Hert2ian fracture cones and micro-splits. These damage patterns result - in increased device lifetimes by : ~ :
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66~3~1L6 1 the creation of interstitials (vacancies~ towarcl the damaged side of the wafer, away from the device area.
Referrin~ now to Figure 1, ~he basic method is shown in three stages. In Figure la, the wafer 10 typically silicon has a polished surface 12 upon which the particular semiconductor device is to be fashioned and an opposite or backside 14. On the backside, impact sound stressing is performed to create a uniform pattern of damage shown out of proportion as 10. Because ISS damage serves as a stress relief agent during proc~ssing, this step must be carried out prior to high temperature processing. As shown in Figure lb, this step is shown as the oxidation of silicon; however, other high temperature opera-ti~ns such as epitaxy, diffusion or ion implantdtion of silicon and other semiconductor materials are obviously included. The final step of the device application is shown in Figure lc, and is the deposition of aluminum metallurgy to form basic MOS capacitors in the wafer is only one '~ypical application.
, The following examples demonstrate, by comparative test value, the utility of this invention.

A series of Si wafers were sound stressed on the backside by bouncing tungsten balls (12 mils in diameter) un~er the following para-meters:
(a) power - 40 watts (b) frequency - 1.38 kHz (c) time - 5 min.
As a result of the sound stressing, a high density ~105/cm2) of Hertzian cracks and damage clusters form on the wafer backside. The wafers were then precleaned and MOS capacitors made on the samples. ~ ;
Comparative runs, measur-FT9-75-020 . - 6 . :

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¦ ing yields with control ~a~nples were:
2 ¦ Back~ide Range, MOS A~ve~, MOS
3 ¦ ~ S~lbstrate Stre~ed # of WaferD Yield % _Yield ~0 4 ¦1. Control --- 4 76-100 92. 6 . .
I p <100~
6 1 ~Q_ cm ? ¦ 2. Standard Ye~ 4 94. 5-100 98. 6 8 1 . p~100 9 2fL -cm 3. Standard Ye~ 5 8û. 6-100 91. Z
1 1 P <1 00~, 12 2~- cm 13 ; 4. " ~ No 2 25_2$ 25 14 . 5u " Yes : 3 80. 6-97 87~ 9 6. " No 2 30. 6-36. 2 33O 4 16 7. " Ye~ 3 80. 6-97 91, 7 17 8. Standard Yee 7 86. 3-100 . 93. 8 18 p <100>
19 15~- cm .
:9, Standard. No 6 ~ 8. 5-60 37. 3 21 : n<100~ ~ ~
22 1~- cm `
23 10. " Yes~ 10 61. 3-81, 3 70. S
24 The re~ult~: can be summarized by:
` 1. Stre~sing the backside of ~e high qualit~r control wafer did 26 : not ahow any degrndation of the wafer~, but improvements wit~ a 27 ~arrower range o~ MOS yield was ob~erved.
28 ~ 2.: ~ Back~ide ~tre~sing resulted in remarkable Improvement in the 29 ~ ~ MOS yield of Standard ~wafer8. All~:Standard p-type wafers mea~ured ater ~tre~sing have a yield of 80% s)r more wi1~h an average yield of 31 ~: about 90'10. I n~ order to i~ure that improvement wa~ not a3 a result 32 of chance in the ~ample~, non-stressed and stre~sed;tail end wafers 33 ~ (samples ~4-7) were~yroce0Yed oimultan~ou~ly. The improvement i9 3~: ~self_evident:in sample~ ~-7 whic~ were reject wafer~,:
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; ~661~6 A comparative test usinS various treatments, such as I2 etch, subcol7ector diffusion into 5 squares (eg. 5 n ) and sound stressing of substrate bac~sides were used to see if any improvement of epi-taxial quality can be achieved. An n-epi layer was grown on p ~100>
substrates (15 L -cm) by the hydrogen reduction of SiC14 at 1100C.
The thickness of the n-epitaxial layer was dbout 6 ,u and the dopant (As~ cDncentraticn ranged from 0.8 to 1.6 x 1016 atoms/cc as calculated from the C-V measurements of MOS capacitors.
In one run, âome wafers were I2 etched to r~move 1 JU` of surfacc before epitaxial processing. In another run, the suustrates were sub-jected to two different treatments before epitaxial deposition. Im-pact sound stressing of substrate backsides was carried out by bouncing tungsten balls (12 mils in diameter) on the backside of the wafers at 40 ~atts power and 1.38 kHz for 5 minutes. For the 5t] test, the wafers ~ere oxidized and had subcollector diffusion in the five squares and subcollector reoxidation.
Fcllowing epitaxial deposition, MOS capacitors with 1400 A-thick dry oxide were made in the n-epi layer, and the C-V curves of the capacitors measured.

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`~ lOG68~6 Effect of I2-etch on the Lifetime of N-Epitaxial Silicon Ave. Life-Substrate I EtchLifetime, ~s time, ~s 2 _ Standard1 No 0.076~ 0.3,B 0.19 3 " 0.18 ~ 0.89 0.58 :
" 0.016~ 0.56 0.22 7 " 0.12~ O.n~l 0.038 0.26 Standard2 Yes 0.50~- 3.11 1.09 4 " 0.21 ~ 2.96 0.83 6 " 0.34-~ 7.31 2.91 :
8 " 0.27 ~ 1.75 0.7S
1.40 SelectedA No 0.60 ~18.0 8.48 C " 0.26 ~ 3.51 1.51 -E " 0.044- 5.28 2.52 G " 0.036- 0.36 0.14 3.16 SelectedB Yes 0.054~ 3.73 1.21 D " 1.005~ 2.42 1.23 1.22 Standard 5 0 No 0.48~143.6 43.0 Control 140-1 No epi 15 ~ 286.2 107.2 141-1 " 162-638 441.3 142-2 " 27-131 63.3 : .
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~ .:, `~Lal6~ 6 1 Effect of 5 O and Backside Sound-Stressing on the Lifetime of N-Epitaxial Silicon Backside Ave. Li~e-Substrate Stressed Lifetime, ~s time, ~s Standard 5~1 1 No 0.38 ~ 2.94 1.10 2 "0.063 ~ 0.73 0.32 3 "0.0~ ~ 1.41~ 0.39 4 "9.93 ~ 53.9 25.9 "0.12 ~ 4.5.~ 1.02

5.75 :
Standard 1 Yes0.64 ~ 6.81 2O47 2 "2.87 ~ 12.9 7.56 3 "25.8 ~ 93.5 53.6 .-4 "0.68 ~ 7.66 3.93 .
"0.016 ~ 2.02 1.14 13.7 Selected A Yes0.19 ~ 14.3 6.29 B "10.3 r~ 60.7 32.2 C "0.17 ~ 14.7 8.50 D "11.4 ~ 43.5 23.7 E "5.74 ~ 9.38 7.09 15.6 Control 148-1 No epi 363 ^~ 488 359 149-1 " 433 ~ 712 558 150-1 "43.4 ^~ 108 ~0.5 -, ..-. .
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1 A compar;son with the values on the two charts indicates the imp~r-tance of impact sound-stressing as compared with available wafer treatments. TEM and SEM investigations revealed the main defects in the n-epitaxial si1icon are grown-in stacking faults, oxidation-in-duced stacking faults and mounds. These defects, notably oxida~ion-induced stacking f~ulis, cause serious reduction of lifetime. The conclusion reached is significant in terms of the effect oF sound-stressing wafer backsides before epitaxial deposition on lifetime.
This improvement is a esult of reduction in defect density.
E~AI~PLE 3 The use of this technique in device processing can also be de-monstrated in the grow~h of high quality epitaxial silicon films on implanted nitrvgen layers. It has been demonstrated that silicon nitride films can be produced subsurface through high energy implan-tation of nitrogen and that the silicon layer above the surface re-mains a single crystal. Dev;ce Fl9-75-020 .
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1 application revealed problems with the lifetime of carriers in this single crystal si1icon layer. As a consequence, it has been pro-posed to grow epitaxial silicon on such implanted crystals to improve the silicon quality; however, difficulties arose in the quality of the epitaxial film. The use of impact sound-stressing to improve the lifetimes of epitaxial silicon on the ion-implanted silicon surface can be accomplished after implantation, but before epitaxy. The pro-cessing can be summarized by the following steps:
(a) high energy implantation of a type described in U.S.
10Patent No. 3,622,382, "Semiconductor Isolation Structure and Method of Producing";
(b) impact sound-stressing of the implanted wafer on the non-implanted wafer side;
(c) annealing of the wafer to obtain the silicon-nitride film as described in U.S. Patent No. 3,622,382, and (d) epitaxial deposition.
~, The following tables show the lifetime of n-ep;tax;al silicon -~
on As implanted substrates, both with and without backside sound-stressing~

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1 Lifetime of N-epitaxial silicon on As Implanted Substrates En~rgy = 80Kev No ImplantAs Implant (Half Wafer)(Half Wafer)Dos~e Sample Lifetime, ~sLifetime, ~s lcm~
Standard 127-1 0.15 0.028 1013 Selected 127-9 0.5 0.035 1013 Standard 127-5 0.37 0.251 lol3 Selected 127-11 1.37 0.79 lQ 4 Standard 128-1 0.051 0.068 1015 Selected 128-9 0.76 0 94 1015 Standard 128-5 4.86 2.51 1 ol 6 Selected 128-11 1.54 0.92 lol5 Effect of Backside Sound-Stressing on Lifetime of N-epitaxial Silicon on As Implanted Substrates ':
Energy= 80Kev No ImplantAs Implant (Half Wafer)(Half Wafer) Dose Sample Lifetime~usLifetime, ~s lc~2 1~ ~
Standard 127-2 5.43 2.64 10'~
Selected 127-10 2.57 1.63 lol3 Standard 127-6 2.30 1.51 1014 Selected 127-12 2.51 1.37 1014 Standard 128-2 0.47 0.13 1015 Selected 128-10 2.42 0.21 15 Standard 128-6 0.085 0.15 10 Selected 128-12 3.48 1.39 1ol6 . ~. .
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FI9-75-020 -~13 -. ~ ', 1 ~66~1~6 ¦ From theae examples, ;t is readily apyarent that the application of 2 1 impact sound-stre~sing result~ in improved lifetime in the device area.
3 This technique is beneficial to all ~emiconductor devices, ~pecifically to 4 dynamic memaries, bipolar~, . solar cells and ps: wer de~ice~. ~~
While e~emplary embodiments have been specifically di~closed, it 6 ~hould be under tood that the practice of this invention i8 not limited to

7 those embodiments. Modifications and varicLtions falling within the spirit

8 of the invèntion will occur to tho~e skilled in the art. Therefore, it i8

9 not intended that the scope of the invention be determined by ~e di~-closed exemplary embodirnents, but rather should be deterrnined by the Il ~ Ib~e I h ol ~ e-~e~ cl~im~.

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Claims (11)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. In the process of making semiconductor devices, the improvement comprising the steps of placing a plurality of loose spherical shaped objects on one face of a semiconductor wafer and acoustically vi-brating said wafer whereby said face is damaged in a controlled and uniform manner.

2. The method of claim 1 wherein the wafer is vibrated prior to high temperature processing to fashion the device.

3. The method of claim 1 wherein the wafer is acoustically vibrated at the resonant frequency of the wafer.

4. The method of claim 1 including the steps of cleaning the wafer following acoustical vibration and fabricating an MOS device on the side of the wafer opposite that upon which said spherical shaped ob-jects were placed.

5. The method of claim 4 wherein said MOS device is a capacitor made by deposition of aluminum into said wafer.

6. The method of claim 1 wherein implantation of the wafer occurs prior to acoustical vibration.

7. The method of claim 6 wherein nitrogen is implanted and including the steps of annealing the wafer following acoustical vibration to obtain a silicon nitride film and epitaxial deposition.

8. A method of making improved semiconductor substrates comprising the step of damaging one face of the substrate by vibrating a plurality of loose spherical objects on said face to create a uniform damage pattern having Hertzian fracture cones and micro-splits.

9. The method of claim 8 wherein said vibration is acoustical.

10. The method of claim 9 wherein said acoustical vibration is at the resonant frequency of said wafer.

11. The method of claim 10 wherein said vibration occurs prior to high temperature processing of said substrate.