CA1049652A - Charge-coupled area array - Google Patents
Charge-coupled area arrayInfo
- Publication number
- CA1049652A CA1049652A CA205,678A CA205678A CA1049652A CA 1049652 A CA1049652 A CA 1049652A CA 205678 A CA205678 A CA 205678A CA 1049652 A CA1049652 A CA 1049652A
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- Prior art keywords
- light
- ccd elements
- shift register
- region
- sensitive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 claims abstract description 45
- 230000004888 barrier function Effects 0.000 claims abstract description 33
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 28
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 11
- 238000003384 imaging method Methods 0.000 claims description 42
- 239000000758 substrate Substances 0.000 claims description 39
- 230000000875 corresponding effect Effects 0.000 claims description 28
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 238000005036 potential barrier Methods 0.000 claims description 6
- 238000003860 storage Methods 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 229910052681 coesite Inorganic materials 0.000 claims 2
- 229910052906 cristobalite Inorganic materials 0.000 claims 2
- 229910052682 stishovite Inorganic materials 0.000 claims 2
- 229910052905 tridymite Inorganic materials 0.000 claims 2
- 239000010410 layer Substances 0.000 description 43
- 238000000034 method Methods 0.000 description 14
- 230000006870 function Effects 0.000 description 10
- 239000012535 impurity Substances 0.000 description 6
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 229910052729 chemical element Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 244000187656 Eucalyptus cornuta Species 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- -1 by vapor deposition Chemical compound 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000002674 ointment Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
- H01L27/14831—Area CCD imagers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
Application for Patent of Lloyd R. Walsh and James M. Early for CHARGE-COUPLED AREA ARRAY
Abstract of the Disclosure A charge-coupled area array comprises a two-phase, buried channel semiconductor charge-coupled device (CCD) array which combines vertical CCD
shift registers interdigitated and distinct from columns of light-sensing CCD elements. Two electrically isolated levels of doped polycrystalline silicon are utilized for the gate electrode structures of the CCD shift register elements and the light-sensing CCD elements of the array, Both of the doped polycrystalline gate electrode layers (vertical transport gates and frame gates) cooperate with barrier semiconductor regions of the array to permit bits of information (charge packets) generated in the light-sensing CCD elements to be laterally transported into the vertical CCD shift registers associated with the light-sensing CCD elements. One of the doped polycrystalline silicon gate electrode layers (vertical transport gates) is used to provide clock pulses to vertically move the charge packets within the shift register CCD elements of the array. These semiconductor barrier regions are of the same conductivity type as the buried region used to transport charge packets in the array. Insulating layers including silicon nitride are used to electrically insulate the semiconductor surface and the doped polycrystalline silicon gate electrode layers from each other.
Abstract of the Disclosure A charge-coupled area array comprises a two-phase, buried channel semiconductor charge-coupled device (CCD) array which combines vertical CCD
shift registers interdigitated and distinct from columns of light-sensing CCD elements. Two electrically isolated levels of doped polycrystalline silicon are utilized for the gate electrode structures of the CCD shift register elements and the light-sensing CCD elements of the array, Both of the doped polycrystalline gate electrode layers (vertical transport gates and frame gates) cooperate with barrier semiconductor regions of the array to permit bits of information (charge packets) generated in the light-sensing CCD elements to be laterally transported into the vertical CCD shift registers associated with the light-sensing CCD elements. One of the doped polycrystalline silicon gate electrode layers (vertical transport gates) is used to provide clock pulses to vertically move the charge packets within the shift register CCD elements of the array. These semiconductor barrier regions are of the same conductivity type as the buried region used to transport charge packets in the array. Insulating layers including silicon nitride are used to electrically insulate the semiconductor surface and the doped polycrystalline silicon gate electrode layers from each other.
Description
965;~
Back~_ound of the In_ ntion Field of the Invention This inven-tion rela-tes to charge-coupled area arrays and, more particularly, -to charye-coupled area ima~iny sel-lliconductor device arrays utilizing light-sensitive charge-coupled device (CCD) elements and shift register charge-coupled device (CCD) elernents.
Description of the Prior Art __ .
A number o-f publications and patents describe the basic theory of operation of the charge-coupled semiconductor device. These publications include an article by Boyle and Smith published in the April 1970 Bell System Technical Journal, page 587, en-titled "Charge-Coupled Semiconductor Devices";
a paper on page 593 of the same Bell System Technical Journal by Amelio et al entitled "Experimental Verification of the Charge-Coupled Device Concept";
and U.S. Patent 3,72~,590, issued to Kim et al, assigned to the same assignee a-F the subject application.
A linear ilnaging array which utilizes a single line of light-sensitive elements in combination with a pair of vertical registers located on opposite sjdes of the line of liyht-sensiny elements is disclosed and described in a copending patent application entitled "A Buried-Channel, Charge-Coupled Linear Imaging Device, inventors Kim et al, filed January 15, 197~, Serial - No. 190,11~. This copending patent application discloses a technique for providing a linear (single line) array of light-sensitive elements; however, a need existed for providing an area array imaying semiconductor device that used a plurality of lines of light-sensitive elements. This need became very evident as it became more important to transmit pictures electronically by electronic communication apparatus. Pictures made up, for example, of 10,000 black or white dots could not be sent previously with the use of a single light-sensitive line imaging semiconductor device that did not have a mechanical scanning device associated therewith. These types pf pictures were previously sent with the use of large, complex and rather expensive electron or CRT types of devices.
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Ul ary _ the nvention Accordinyly, it is an object of this invention to provide a CCD area array imaging semiconductor device.
It is a -Further object of this invention to provide a CCD area array imaging semiconductor device which utilizes a plurality of lines of light-sensitive CC~ elernents.
It is another object o-F this invention to provide a high density, reliable, CCD area array ill!aging semiconductor device.
It is still another object of this invention to provide a CCD area array imaging semiconductor device which utilizes a plurality of shift register lines composed of CCD elements interdigitated and distinct from a plurality of lines of light-sensitive CCD elements.
It is still a further obiect of this invention to provide a system including input and output registers and a CCD area array imagjng semiconduc-tor device to permit input information either in the form of light or electrical signals to be reliably transmitted.
Description of the Preferred Embodiment In accordance with one embodiment of this invention, an imaging array is disclosed which comprises a semiconductor substrate having a plurality of ~- 2Q lines of light-sensitive CCD elements associated with portions of the semi-conductor substrate. Means are provided for trans-ferring charge packets generated in the light-sensitive elements to corresponding CCD elements of the shift register lines to an output portion of the array. Additional Features of the preferred embodiment include means for shifting the cllarge packets along the shift register lines and means for receiving said charge packets at the end of the shift register lines. The means for transferring charge packets generated in the light-sensitive elements to corresponding CCD elements comprises a pair of light-transparent gate electrode means associated with each of the light-sensitive elements. Preferably, both of 3~ the pair of light-transparent gate electrode means comprises a doped poly-crystalline silicon electrode. Preferably, the light-sensitive elements of - . ~ . ..
the array have both a buried region of one conductivity type located in a region or substrate of opposite type conductivity, and a higher resistivity buried barrier region of the same one conductivity type located adjacent the buried region.
In accordance with another embodiment of this invention, a system is disclosed which includes an imaging array comprising a semiconductor sub-strate having a plurality of lines of light-sensitive CCD elements associated with portions of the semiconductor substrate. The imaging array also con-tains a corresponding plurality of shift register lines each having a plurality of CCD elements associated with other portions of the semiconductor substrate. Means are provided for transferring charge packets generated in the light-sensitive CCD elements to corresponding CCD elements of the shift register lines for subsequent movement within the shift register lines to an ;; output portion of the array. The system further includes output register means, preferably of CCD elements, electrically connected to the imaging array for receiving and further transferring the charge packets coming from the output portion of the array. Additional features of the system include input register means and electrical input signal means for transferring electrical input signals into the array in the event electrical signals .
rather than light are used as an input to the system.
According to a first broad aspect of the invention, there is pro-vided an imaging array comprising: a semiconductor substrate having a top surface; a plurality of lines of light-sensitive CCD elements associated with portions of said semiconductor substrate; a corresponding plurality of shift register lines each having a plurality of CCD elements associated with other portions of said semiconductor substrate; and means for transferring - charge packets generated in said light-sensitive CCD elements to correspond-ing CCD elements o said shift register lines for subsequent movement within said shift register lines to an output portion of said array, wherein each of said light-sensitive CCD elements ls separated from adjacent light-sensitive CCD elements by a heavily doped channel stop region formed in the top surface of said semiconductor substrate, said heavily doped channel stop ~r -4-'~ .
` 1~4~65%
regions surrounding each light-sensitive CCD element such that every light-sensitive CCD elenlent has open to one of said shift registers a side on which there is no channel stop region.
According to a second broad aspect of the invention, there is provided an imaging array comprising: a semiconductor substrate; a plurality of light-sensitive CCD elements associated with portions of said semicon-ductor substrate; a corresponding plurality of shift register lines each having a plurality of CCD elements associated with other portions of said semiconductor substrate, and means for transferring charge packets generated in said light-sensitive CCD elements to corresponding CCD elements of said shift register lines for subsequent movement within said shift register lines to an output portion of said array, said light-sensitive CCD elements ~ ~-comprising a buried region of one conductivity type located in a region of opposite conductivity type, and a higher resistivity buried barrier region of said one conductivity type located adjacent to said buried region.
According to a third broad aspect of the invention, there is provided a system for transmitting electrical energy comprising: an imaging array comprising a semiconductor substrate having a top surface and having ~.
a plurality of lines of light-sensitive CCD elements associated with portions . 20 of said semiconductor substrate; a.corresponding plurality of shift register lines each having a plurality of CCD elements associated with other portions of said semiconductor substrate; means for transferring charge packets generated in said light-sensitive CCD elements to corresponding CCD elements :~
: of said shift register lines for subsequent movement within said shift register lines to an output portion of said array; and output register means electrically connected to said imaging array for receiving and further transferring the charge packets coming from the output portion of said array, ~-~ wherein each of said light-sensitive CCD elements is separated from adjacent light-sensitive CCD elements by a heavily doped channel stop region formed :
-: 3Q in the top surface of said semiconductar substrate, said heavily doped channel stop regions surrounding each light-sensitive CCD element such that every light-sensitive CCD element has open to one of said shift registers a ~ -4a-,.
:' ' ' ' :~ ., ~49~;5Z
side on which there is no channel stop region.
The invention will now be described in greater detail with reference to the accompanying drawings described below.
FIG. 1 is a sectional view, in elevation, showing a single light-sensitive CCD element located in one of the plurality of lines of light-sensitive CCD elements of a CCD area imaging array adjacent a corresponding single shift register CCD element located in one of the plurality of lines of shift register elements of the same CCD area imaging array.
-4b-.
5i2 FIG. 2 is a top planar view of the light-sensitive CCD element and its corresponding shift register CCD element of FIG. 1 with parts broken away to illustrate particular regions and portions of each of the elements shown beneath the surface layers, and with certain selected overlying layers also shown.
FIG. 3 is ~ block diagram of a system utilizing a CCD area array composed of a plurali~y of lines of light-sensitive CCD elements of the type shown in FIG. 1 and a plurality of shift register lines having shift register CCD deYices of the type shown in FIG. 1 in combination with input and output registers and associated elements to provide a total area array imaging system.
Referring to FIG. 1, a semiconduc~or substrate 10 is shown which, in the disclosed embodiment, is made of P type material. The substrate 10 is preferably a boron doped substrate containing 1014 impurities per cubic centi~
meter and has a thickness of about 150 microns. Although the described ~ ~ ~
embodiment preferably uses a semiconductor substrate made of silicon ma~erial, ~ ;
it is evident to those skilled in the art that other semiconductor materials ; may be used. Furthermore, the conductivity type regions described in the , embodiment of FIG. 1 can be of opposite type conducti~ity, if desired, in order to pro~ide an array with CCD elements using charge packets with the - opposite type of minority carriers.
Located on a surface o~ the substrate 10 is a buried N type region `
12 and a buried N type region 14. Region 12 is surrounded on three sides by region 20 (shown dotted in FIG. 2). Region 14 is bounded at opposite sides by barrier regions 23 and 25 ~also shown dotted in FIG. 2), and is bounded on the right-hand side of FIG. 2 by a channel stop region ~not numbered) analagous to region 20. The cross-hatched regions within the regions 12 and 14 are the potential wells of each CCD element, as shown in FIGURE 2. The buried N type region 12 is part of light-sensitive CCD ele-ment 16 that is used in the CCD area array. The buried N type region 14 is part of shift register CCD element 18. Preferably, the buried N type regions _ 5 _ ,:
J :~
. .
5'~:
12 and 1~ are formed during a single process step using, for example, ion implantation techniques for creating the N doped regions 12 and 14. Arsenic or phosphorous, for exampleJ is used as the N type dopant for the regions 12 and 14. In the disclosed embodiment, the N type regions 12 and 14 have a thickness of about one-half micron and a phosphorous impurity level of 3 x 1016 atoms per cubic centimeter. rhe operation and function of the buried channel regions 12 and 14 are set forth in U.S. Patent No. 3,739,240 entitled BURIED C~NNEL CHARGE COUPLED DEVICES issued to R. H. Krambeck on June 12, 1973.
A channel stop region 20 is shown in both FIGS. 1 and 2, which region serves to prevent charge packets generated by light striking the light-sensitive regions (N buried region 12) of the light-sensitive element 16 rom being transferred into adjacent light-sensitive elements or other un-desired areas of the array. The channel stop region 20 is preferably a P~
type region which can be formed by ion implantation or by diffusion techni-ques. The P~ channel stop region 20 contains from about 1018 to about 102 impurities per cubic centimeter, for example, of boron. The advantages and functions of the channel stop region are discussed in U.S. Patent No.
3,739~240 mentioned abo~e.
Ihe P~ channel stop region 20, as shown by the dotted region at the left-hand side of ~IG. 2, surrounds three sides of the light-sensitive CCD
element 16 and thus blocks charge packets from passing through these three sides of the light-sensitive CCD element 16. There is only one opening that the charge packets generated in the light sensitive CCD element 16 can be transmitted through and that is through a buried barrier region 22 which is the electrical gate between the light-sensitive CCD element 16 and its cor-responding shift register CCD element 18. The buried barrier region 22 is preferably of N-type conductivity and has a resistivity of, for example, 1 x 1016 impurities per cubic centimeter where the impurities are, for 3~ example, arsenic or phosphorous. The buried barrier region 22 is formed i during a separate step in the process of fabricating the array. Preferably, ,.. ~
, ion implantation techniq~les are used to form the N- buried barrier region 22.
As can be seen with respect to FIG. 2, a buried barrier 23 and a buried barrier region 25 are located on opposite sides of the N type region 14 of the shift register CCD element 18. The buried barrier regions 22, 23 and 25 are all formed in the same process step.
As a consequence, all of the N type regions 12 and 14 for the light-sensitive CCD element 16 and the shift register CCD element 18 for the entire array is formed during the same process step and the N- type buried barrier regions 22, 23 and 25 for each of the light-sensitive CCD elements 16 and the shift register CCD elements 18 of the array are also formed during a separate step in the process of fabricating the array. The ~+ channel stop regions 20 are formed using a single separate process step to provide a C-shaped channel stop region for each o the light-sensitive CCD elements 16 during the fabrication of the array.
The thickness of the N- buried barrier regions 22, 23 and 25 is pre-ferably about one-hal~ micron, which is equivalent to the thickness of the buried N type regions 12 and l4.- The channel stop regions 20 are thicker than the buried channel N type regions 12 and 14 in order to serve the func-tion of providing a channel stop for preventing charge packets generated in 20 the light-sensitive CCD elements by light~photons striking the N region 12 from entering into adjacent light-sensitive elements or other undesired areas of the array.
In the disclosed embodiment, and with reference to FIG. 1~ an insu-lating layer 24 is located on the active N, N- and P~ surface regions of the semiconductor substrate. Preferably, the insulating layer 24 is a thermal silicon dioxide layer-having, for example, a thickness of about 1200 Ang-stroms. This thermal oxide layer is formed using well known thermal oxida-tion techniques. A second insulating layer 26 is located on ~he first in-sulating layer 24 and serves the function of providing a double pin hole 30 - protection layer when used in combination with the underlying insulating ' 96S'~
layer 24 to prevent or signif'icantly minimize the possibility o~ having electrically conductive ma-terial deposited on the surface of the semiconductor substrate penetrating through a pin hole in the insulating layer to electric-ally short out portions of the array.
Preferably, the second insulating layer 26 is made of silicon nitride and is formed by any of the well known techniques for depositing silicon nitride such as by vapor deposition, R.F. sputtering, etc. The thickness of the silicon nitride layer 26 is preferably about 300 Angstroms. Another important ;unction of the si1icon nitride layer 26 is that it prevents further growth of the thermal ox;de insulating layer 24 which is very sensi-tive to subsequent thermal process steps such as is used, for example, in the fornlation of the subsequent layers on the substrate surface. In this manner, ' the silicon nitride layer 26 serves to provide the double function of a pin hole protection layer as well as a thermal insulation layer for the thermal ' oxide insulating layer 24.
A first polycrystalline silicon layer 28 doped with, for example, phosphorous impurities, is deposited on the silicon nitride layer 26. This first polycrystalline silicon layer 28 is deposited by well known techniques used in forming a polycrystalline silicon layer onto an insulating surface. - ' The doped polycrystalline silicon layer 28 is etched to form the separated, longitudinal gate electrode pattern shown in FIG. l. Subsequently, a third insulating layer 30 is deposited onto the silicon nitride surface and on the exterior surface of the first polycrystalline silicon dioxide layer which is formed by well known thermal oxidation deposition techniques.
The doped -First polycrystalline silicon layer 2~ is a current conduc-ting element and thus provides the function of being a gate electrode. The electrode gate formed by the doped polycrystalline silicon layer 28 is the "frame gate" for the light-sensitive element 16 which functions to help per-mit the charge packets (generated in the light-sensitive element 16 from light impinging thereon) to pass laterally into the corresponding shift register element 18. The charge packets generated within the N type region 12 of the light-sensitive CC~ element 16 are shifted laterally into the _~_ ... . .
; ~ .. . . .
;5;2 charge storage region 14 of the shift register CCD element 18 so that they may then be trc~nsferred up the shift register line to the output portion of the array. The doped polycrystalline electrode 28 is transparent to light so that it can function as a gate electrode and yet permit light to be trans-mitted through the electrode 28 and into contact with the light-sensitive portion 12 of the light-sensitive CCD element 16 to thereby generate the charge packets.
A second polycrystalline silicon layer 32 is deposited on the ex-posed surface portions of the silicon nitride layer 26 and on the surface portion of the thermal oxide region 30. The second polycrystalline silicon layer 32 is selectively doped with phosphorous in regions thereof to provide alternate conductive or nonconductive (insulating) regions where desired.
The electrically conductive or electrode portions of the second polycrystal-line silicon layer 32 provide, with the gate electrode 28, an orthogonal gate electrode axray configuration. 'Ihe electrode portions o~ the polycrystalline layer 32 are the "vertical gates" for carrying clock pulses in~o the array in order to lower the potential barrier of the buried barrier region 23, for example, of the shift register elemént 18 to thereby pass the charge packets vertically along the shift register line. An encapsulating insulating layer 34 is provided on the second polycrystalline silicon layer 32 to protect the :~ .
polycrystalline silicon layer 32 to protect the polycrystalline silicon layer 32 and also to provide electrical insulation from an aluminum light-blocking shield 36 which is located on the portion of the insulating layer 34 that is located over the shift register element 18. The insulating layer 34 `-is preferably a vapor-deposited oxide layer. The thickness of the second polycrystalline silicon layer 32 is preferably about 4000 Angstroms. The thickness of the aluminum light shield i~ preferably about 1 micron and this material thickness serYes to prevent light from passing through the aluminum light-blocking shield 36.
_ :
. .................. ; , . , . : , . . :
.
:, ,. , ~. , : . . . : .
..
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In one example, an array containing 10,000 photo-sensitive CCD ele-ments was formed o-f 100 x 100 light-sensitive CCD elements 16 and 100 shiFt reyister CCD columns with each column containing 100 shift register elements 18. The light-sensitive CCD elements 16 were formed in a plurality oF vertical shiFt register lines wi-th each one of the shift reyister elements 18 located adjacent to and, as explained above, electrically coupled to a corresponding light-sensitive element 16 to receive, under certain conditions, charge packets generated within and transmitted from the light-sensitive elements 16. For example, transfer of charge packets from the liyht-sensitive CCD element 16 to the shift reyister COD element 18 occurs when the "ver-tical gate" electrode portion of the second polycrystalline line 32 (which is the portion that overlies the frame electrode 28~ is at a higher electrical potential than the electrical potential applied to the "frame gate" elec-trode 28.
In more detail, a potential o-F +5 Yolts applied to the "vertical gate" electrode portion of the second polycrystalline layer 32 as compared with holding the potential of the "fran1e gate" electrode 28 to 0 volts causes the charge packets to laterally pass through the N- buried barrier region 22 from the light-sensitive CCD element 16 to the shift register CCD
element 18. In one embodiment, the width of the ~uried barrier region 22 is about 0.2 mils wide, the width of the "vertical gate" is about 0.9 mils . wide, the width of the P+ channel stop region 20 is about 0.2 mils wide, the width of the "frame gate" electrode 28 is about 0.6 mils wide and the separation distance hetween "vertical gate" electrodes is about 0.~ mils wide.
Referring to FIG. 3, a system is disclosed which includes an imping-ing array 100 which is composed of pluralities oF light-sensitive CCD ele-;: ments 16 and the shift reyister CCD elements 18. In the embodiment wherein 10,000 (100 x 10Q) light-sensitive CCD elements 16 are used in combination with 10Q columns of vertical shift registers (each column contains 100 CCD
shift registers), 50 two-phase vertical shifts (or I00 jumps) are needed to transfer charge packets entering the lowermost shift register elements at ~ `
', , , ' ~ 0~9~2 the hottom portion of -the array 100 to the outermost shi-ft register elements located at the upper portion o-F the array 100. Since the system disclosed in FIfi. 3 is a two-phase CCD system, clock pulses applied to electrodes (~v1 and '~V2 which are electrically connected to alternate, adjacen-t "vertical yates"
(electrode portions of the second polycrystalline layer 32) cause the charge packets to be transferred vertically through the shiFt register CCD elements 18 Forming the vertical shift re~ister CCD lines. As generally disclosed in the above-mentioned copending Kim et al application, control oF the pulsed potentials applied to the electrodes ~v1 and ~v2 causes the charye packets in the shift register CCD elements 18 to be transferred vertically through the vertical shift register CCD line~. A pulsed potential oF, for example, about -8 to about +14 volts applied to the electrodes (~v1 and (~v2 causes the charge packets to be transferred vertically through the shift register CCD elements 18 provided that the pulsed voltages applied to the two electrodes ~v1 and ~V2 are out-of-phase or complementary to each other. When the potential applied to selected vertical gate electrode portions of the second polycrystal-line silicon layer 32 is ~ volts (most positive portion of the potential swing), charge packets are passed through the buried barrier region 23 (or 25) located beneath the vertical gate electrode which is at the most pos-itive potential. The positive ~ volts applied to the vertical gate elec-trode lowers the potential barrier of the associated buried barrier region 23 (or 25) located beneath the most positive vertical gate electrode.
Frame electrode ~F electrically connects a clock ~not shown) to the frame electrodes 28 of the array 100. The clock supplies a swinging voltage of from about 0 to about +10 volts.
In the detailed disclosed embodiment, 100 bits or charge packets are dumped into output register 102 from the array 100 at one time.
Preferably,the two-phase CCD output register 102 contains 102 gates associated with the electrode ~H1 and 102 gates associated with the electrode (~H2. ~H1 and ~H2 are similar to electrodes ~v1 and ~v2 associated with the array 100. Thus, clocks connected to electrodes ~H1 and ~H2 apply a swing-ing voltage of from about -~ to about +~ volts which causes a corresponding : ; :
. . . . .... . .. . .
... . ~.~, . . . . . .
. .. . . . . ... . .. . . . .
. . .. . .
. . , ~ . . . . . . . .
.. . . .
.
~ 9 t;5 ~
potential -to be applied to the gate electrodes associated with each electrode (~H1 and (lH2. The output register 102 has 204 shift register elements of the -type shown by reference numeral 18 in FIGS. 1 and 2. Thus 102 two-phase shifts (or 204 jurr~ps) are needed to move the bits or charge packets from one end oF the output register 102 to the other (or output) end thereof.
Electrically connected to the output portion of the output reyister 102 is an output amplifier 104 to which is electrically connected a source electrode S1 and a drain electrode D1. The output amplifier 10~ is an MOS
or FET type of amplifier of the type disclosed and described in the above-mentioned Kim et al appl-ication. A compensation amplifier 106 made of ~OS
or FET type devices having source S2 and drain D2 electrodes connected there-to is electrically connected to the output amplifier 104 and functions to compensate for the noise generated by reset circuit 108 to which is connected a reset drain electrode RD. A reset clock (not shown) is connected to the reset circuit 108 by means of electrode ~R which is eleotrically connected to the reset circuit 108. The operation of the compensation amplifier 106 and the output amplifier 104 which together function as a differential ampli-fier is disclosed and described in the above-mentioned Kim et al application Which also discusses the need for the reset circuit 108 to clear the appara-tus for the next signal.
At the input portion of the system disclosed in FIG. 3 is an input register llQ which is similar to the output register 102. Thus both the input and output registers use CCD shift register elernents of the type shown generally by reFerence nuDIeral 18 in FIGS. 1 and 2. Accordingly lQ2 two-phase shifts (or 204 jumps.) are needed to move bits or charge packets -From one end ot the input register 110 to the other end thereof. However only one shift is needed to move the charge packets vertically into the array 100. ; ~`
A total of 100 bits or charge packets are moved into the array lOQ from the input register 110. Clocks (not shown) are electrically connected to elec-trodes ~H1' and ~H2' to move the charge packets through the shift registers forming the input register 110. An input section 112 is composed of an input source electrode which is pulsed with a voltage that swings from about S~
-8 to about +4 volts that i.5 connected to an N+ diffused region (not shown).
An input ~ate located over the Nt diffused region is held to a potential of -about O volts. The input source 112 generates electrical signals to the input register 110 and serves as an alternative method oF providing an input to the array 100. Thus the systern of FIG. 3 can be used with a light source input directly striking the light-sensitive elernents 16 of the array 100 or with an electrical (electron) input from the input section 112.
While the invention has been particularly shown and described in reference to the preferred embodiment thereof it will be understood by ~ !
those skilled in the art that changes in the form~and details may be made therein without departing from the spirit and scope of the invention.
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Back~_ound of the In_ ntion Field of the Invention This inven-tion rela-tes to charge-coupled area arrays and, more particularly, -to charye-coupled area ima~iny sel-lliconductor device arrays utilizing light-sensitive charge-coupled device (CCD) elements and shift register charge-coupled device (CCD) elernents.
Description of the Prior Art __ .
A number o-f publications and patents describe the basic theory of operation of the charge-coupled semiconductor device. These publications include an article by Boyle and Smith published in the April 1970 Bell System Technical Journal, page 587, en-titled "Charge-Coupled Semiconductor Devices";
a paper on page 593 of the same Bell System Technical Journal by Amelio et al entitled "Experimental Verification of the Charge-Coupled Device Concept";
and U.S. Patent 3,72~,590, issued to Kim et al, assigned to the same assignee a-F the subject application.
A linear ilnaging array which utilizes a single line of light-sensitive elements in combination with a pair of vertical registers located on opposite sjdes of the line of liyht-sensiny elements is disclosed and described in a copending patent application entitled "A Buried-Channel, Charge-Coupled Linear Imaging Device, inventors Kim et al, filed January 15, 197~, Serial - No. 190,11~. This copending patent application discloses a technique for providing a linear (single line) array of light-sensitive elements; however, a need existed for providing an area array imaying semiconductor device that used a plurality of lines of light-sensitive elements. This need became very evident as it became more important to transmit pictures electronically by electronic communication apparatus. Pictures made up, for example, of 10,000 black or white dots could not be sent previously with the use of a single light-sensitive line imaging semiconductor device that did not have a mechanical scanning device associated therewith. These types pf pictures were previously sent with the use of large, complex and rather expensive electron or CRT types of devices.
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Ul ary _ the nvention Accordinyly, it is an object of this invention to provide a CCD area array imaging semiconductor device.
It is a -Further object of this invention to provide a CCD area array imaging semiconductor device which utilizes a plurality of lines of light-sensitive CC~ elernents.
It is another object o-F this invention to provide a high density, reliable, CCD area array ill!aging semiconductor device.
It is still another object of this invention to provide a CCD area array imaging semiconductor device which utilizes a plurality of shift register lines composed of CCD elements interdigitated and distinct from a plurality of lines of light-sensitive CCD elements.
It is still a further obiect of this invention to provide a system including input and output registers and a CCD area array imagjng semiconduc-tor device to permit input information either in the form of light or electrical signals to be reliably transmitted.
Description of the Preferred Embodiment In accordance with one embodiment of this invention, an imaging array is disclosed which comprises a semiconductor substrate having a plurality of ~- 2Q lines of light-sensitive CCD elements associated with portions of the semi-conductor substrate. Means are provided for trans-ferring charge packets generated in the light-sensitive elements to corresponding CCD elements of the shift register lines to an output portion of the array. Additional Features of the preferred embodiment include means for shifting the cllarge packets along the shift register lines and means for receiving said charge packets at the end of the shift register lines. The means for transferring charge packets generated in the light-sensitive elements to corresponding CCD elements comprises a pair of light-transparent gate electrode means associated with each of the light-sensitive elements. Preferably, both of 3~ the pair of light-transparent gate electrode means comprises a doped poly-crystalline silicon electrode. Preferably, the light-sensitive elements of - . ~ . ..
the array have both a buried region of one conductivity type located in a region or substrate of opposite type conductivity, and a higher resistivity buried barrier region of the same one conductivity type located adjacent the buried region.
In accordance with another embodiment of this invention, a system is disclosed which includes an imaging array comprising a semiconductor sub-strate having a plurality of lines of light-sensitive CCD elements associated with portions of the semiconductor substrate. The imaging array also con-tains a corresponding plurality of shift register lines each having a plurality of CCD elements associated with other portions of the semiconductor substrate. Means are provided for transferring charge packets generated in the light-sensitive CCD elements to corresponding CCD elements of the shift register lines for subsequent movement within the shift register lines to an ;; output portion of the array. The system further includes output register means, preferably of CCD elements, electrically connected to the imaging array for receiving and further transferring the charge packets coming from the output portion of the array. Additional features of the system include input register means and electrical input signal means for transferring electrical input signals into the array in the event electrical signals .
rather than light are used as an input to the system.
According to a first broad aspect of the invention, there is pro-vided an imaging array comprising: a semiconductor substrate having a top surface; a plurality of lines of light-sensitive CCD elements associated with portions of said semiconductor substrate; a corresponding plurality of shift register lines each having a plurality of CCD elements associated with other portions of said semiconductor substrate; and means for transferring - charge packets generated in said light-sensitive CCD elements to correspond-ing CCD elements o said shift register lines for subsequent movement within said shift register lines to an output portion of said array, wherein each of said light-sensitive CCD elements ls separated from adjacent light-sensitive CCD elements by a heavily doped channel stop region formed in the top surface of said semiconductor substrate, said heavily doped channel stop ~r -4-'~ .
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regions surrounding each light-sensitive CCD element such that every light-sensitive CCD elenlent has open to one of said shift registers a side on which there is no channel stop region.
According to a second broad aspect of the invention, there is provided an imaging array comprising: a semiconductor substrate; a plurality of light-sensitive CCD elements associated with portions of said semicon-ductor substrate; a corresponding plurality of shift register lines each having a plurality of CCD elements associated with other portions of said semiconductor substrate, and means for transferring charge packets generated in said light-sensitive CCD elements to corresponding CCD elements of said shift register lines for subsequent movement within said shift register lines to an output portion of said array, said light-sensitive CCD elements ~ ~-comprising a buried region of one conductivity type located in a region of opposite conductivity type, and a higher resistivity buried barrier region of said one conductivity type located adjacent to said buried region.
According to a third broad aspect of the invention, there is provided a system for transmitting electrical energy comprising: an imaging array comprising a semiconductor substrate having a top surface and having ~.
a plurality of lines of light-sensitive CCD elements associated with portions . 20 of said semiconductor substrate; a.corresponding plurality of shift register lines each having a plurality of CCD elements associated with other portions of said semiconductor substrate; means for transferring charge packets generated in said light-sensitive CCD elements to corresponding CCD elements :~
: of said shift register lines for subsequent movement within said shift register lines to an output portion of said array; and output register means electrically connected to said imaging array for receiving and further transferring the charge packets coming from the output portion of said array, ~-~ wherein each of said light-sensitive CCD elements is separated from adjacent light-sensitive CCD elements by a heavily doped channel stop region formed :
-: 3Q in the top surface of said semiconductar substrate, said heavily doped channel stop regions surrounding each light-sensitive CCD element such that every light-sensitive CCD element has open to one of said shift registers a ~ -4a-,.
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side on which there is no channel stop region.
The invention will now be described in greater detail with reference to the accompanying drawings described below.
FIG. 1 is a sectional view, in elevation, showing a single light-sensitive CCD element located in one of the plurality of lines of light-sensitive CCD elements of a CCD area imaging array adjacent a corresponding single shift register CCD element located in one of the plurality of lines of shift register elements of the same CCD area imaging array.
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5i2 FIG. 2 is a top planar view of the light-sensitive CCD element and its corresponding shift register CCD element of FIG. 1 with parts broken away to illustrate particular regions and portions of each of the elements shown beneath the surface layers, and with certain selected overlying layers also shown.
FIG. 3 is ~ block diagram of a system utilizing a CCD area array composed of a plurali~y of lines of light-sensitive CCD elements of the type shown in FIG. 1 and a plurality of shift register lines having shift register CCD deYices of the type shown in FIG. 1 in combination with input and output registers and associated elements to provide a total area array imaging system.
Referring to FIG. 1, a semiconduc~or substrate 10 is shown which, in the disclosed embodiment, is made of P type material. The substrate 10 is preferably a boron doped substrate containing 1014 impurities per cubic centi~
meter and has a thickness of about 150 microns. Although the described ~ ~ ~
embodiment preferably uses a semiconductor substrate made of silicon ma~erial, ~ ;
it is evident to those skilled in the art that other semiconductor materials ; may be used. Furthermore, the conductivity type regions described in the , embodiment of FIG. 1 can be of opposite type conducti~ity, if desired, in order to pro~ide an array with CCD elements using charge packets with the - opposite type of minority carriers.
Located on a surface o~ the substrate 10 is a buried N type region `
12 and a buried N type region 14. Region 12 is surrounded on three sides by region 20 (shown dotted in FIG. 2). Region 14 is bounded at opposite sides by barrier regions 23 and 25 ~also shown dotted in FIG. 2), and is bounded on the right-hand side of FIG. 2 by a channel stop region ~not numbered) analagous to region 20. The cross-hatched regions within the regions 12 and 14 are the potential wells of each CCD element, as shown in FIGURE 2. The buried N type region 12 is part of light-sensitive CCD ele-ment 16 that is used in the CCD area array. The buried N type region 14 is part of shift register CCD element 18. Preferably, the buried N type regions _ 5 _ ,:
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12 and 1~ are formed during a single process step using, for example, ion implantation techniques for creating the N doped regions 12 and 14. Arsenic or phosphorous, for exampleJ is used as the N type dopant for the regions 12 and 14. In the disclosed embodiment, the N type regions 12 and 14 have a thickness of about one-half micron and a phosphorous impurity level of 3 x 1016 atoms per cubic centimeter. rhe operation and function of the buried channel regions 12 and 14 are set forth in U.S. Patent No. 3,739,240 entitled BURIED C~NNEL CHARGE COUPLED DEVICES issued to R. H. Krambeck on June 12, 1973.
A channel stop region 20 is shown in both FIGS. 1 and 2, which region serves to prevent charge packets generated by light striking the light-sensitive regions (N buried region 12) of the light-sensitive element 16 rom being transferred into adjacent light-sensitive elements or other un-desired areas of the array. The channel stop region 20 is preferably a P~
type region which can be formed by ion implantation or by diffusion techni-ques. The P~ channel stop region 20 contains from about 1018 to about 102 impurities per cubic centimeter, for example, of boron. The advantages and functions of the channel stop region are discussed in U.S. Patent No.
3,739~240 mentioned abo~e.
Ihe P~ channel stop region 20, as shown by the dotted region at the left-hand side of ~IG. 2, surrounds three sides of the light-sensitive CCD
element 16 and thus blocks charge packets from passing through these three sides of the light-sensitive CCD element 16. There is only one opening that the charge packets generated in the light sensitive CCD element 16 can be transmitted through and that is through a buried barrier region 22 which is the electrical gate between the light-sensitive CCD element 16 and its cor-responding shift register CCD element 18. The buried barrier region 22 is preferably of N-type conductivity and has a resistivity of, for example, 1 x 1016 impurities per cubic centimeter where the impurities are, for 3~ example, arsenic or phosphorous. The buried barrier region 22 is formed i during a separate step in the process of fabricating the array. Preferably, ,.. ~
, ion implantation techniq~les are used to form the N- buried barrier region 22.
As can be seen with respect to FIG. 2, a buried barrier 23 and a buried barrier region 25 are located on opposite sides of the N type region 14 of the shift register CCD element 18. The buried barrier regions 22, 23 and 25 are all formed in the same process step.
As a consequence, all of the N type regions 12 and 14 for the light-sensitive CCD element 16 and the shift register CCD element 18 for the entire array is formed during the same process step and the N- type buried barrier regions 22, 23 and 25 for each of the light-sensitive CCD elements 16 and the shift register CCD elements 18 of the array are also formed during a separate step in the process of fabricating the array. The ~+ channel stop regions 20 are formed using a single separate process step to provide a C-shaped channel stop region for each o the light-sensitive CCD elements 16 during the fabrication of the array.
The thickness of the N- buried barrier regions 22, 23 and 25 is pre-ferably about one-hal~ micron, which is equivalent to the thickness of the buried N type regions 12 and l4.- The channel stop regions 20 are thicker than the buried channel N type regions 12 and 14 in order to serve the func-tion of providing a channel stop for preventing charge packets generated in 20 the light-sensitive CCD elements by light~photons striking the N region 12 from entering into adjacent light-sensitive elements or other undesired areas of the array.
In the disclosed embodiment, and with reference to FIG. 1~ an insu-lating layer 24 is located on the active N, N- and P~ surface regions of the semiconductor substrate. Preferably, the insulating layer 24 is a thermal silicon dioxide layer-having, for example, a thickness of about 1200 Ang-stroms. This thermal oxide layer is formed using well known thermal oxida-tion techniques. A second insulating layer 26 is located on ~he first in-sulating layer 24 and serves the function of providing a double pin hole 30 - protection layer when used in combination with the underlying insulating ' 96S'~
layer 24 to prevent or signif'icantly minimize the possibility o~ having electrically conductive ma-terial deposited on the surface of the semiconductor substrate penetrating through a pin hole in the insulating layer to electric-ally short out portions of the array.
Preferably, the second insulating layer 26 is made of silicon nitride and is formed by any of the well known techniques for depositing silicon nitride such as by vapor deposition, R.F. sputtering, etc. The thickness of the silicon nitride layer 26 is preferably about 300 Angstroms. Another important ;unction of the si1icon nitride layer 26 is that it prevents further growth of the thermal ox;de insulating layer 24 which is very sensi-tive to subsequent thermal process steps such as is used, for example, in the fornlation of the subsequent layers on the substrate surface. In this manner, ' the silicon nitride layer 26 serves to provide the double function of a pin hole protection layer as well as a thermal insulation layer for the thermal ' oxide insulating layer 24.
A first polycrystalline silicon layer 28 doped with, for example, phosphorous impurities, is deposited on the silicon nitride layer 26. This first polycrystalline silicon layer 28 is deposited by well known techniques used in forming a polycrystalline silicon layer onto an insulating surface. - ' The doped polycrystalline silicon layer 28 is etched to form the separated, longitudinal gate electrode pattern shown in FIG. l. Subsequently, a third insulating layer 30 is deposited onto the silicon nitride surface and on the exterior surface of the first polycrystalline silicon dioxide layer which is formed by well known thermal oxidation deposition techniques.
The doped -First polycrystalline silicon layer 2~ is a current conduc-ting element and thus provides the function of being a gate electrode. The electrode gate formed by the doped polycrystalline silicon layer 28 is the "frame gate" for the light-sensitive element 16 which functions to help per-mit the charge packets (generated in the light-sensitive element 16 from light impinging thereon) to pass laterally into the corresponding shift register element 18. The charge packets generated within the N type region 12 of the light-sensitive CC~ element 16 are shifted laterally into the _~_ ... . .
; ~ .. . . .
;5;2 charge storage region 14 of the shift register CCD element 18 so that they may then be trc~nsferred up the shift register line to the output portion of the array. The doped polycrystalline electrode 28 is transparent to light so that it can function as a gate electrode and yet permit light to be trans-mitted through the electrode 28 and into contact with the light-sensitive portion 12 of the light-sensitive CCD element 16 to thereby generate the charge packets.
A second polycrystalline silicon layer 32 is deposited on the ex-posed surface portions of the silicon nitride layer 26 and on the surface portion of the thermal oxide region 30. The second polycrystalline silicon layer 32 is selectively doped with phosphorous in regions thereof to provide alternate conductive or nonconductive (insulating) regions where desired.
The electrically conductive or electrode portions of the second polycrystal-line silicon layer 32 provide, with the gate electrode 28, an orthogonal gate electrode axray configuration. 'Ihe electrode portions o~ the polycrystalline layer 32 are the "vertical gates" for carrying clock pulses in~o the array in order to lower the potential barrier of the buried barrier region 23, for example, of the shift register elemént 18 to thereby pass the charge packets vertically along the shift register line. An encapsulating insulating layer 34 is provided on the second polycrystalline silicon layer 32 to protect the :~ .
polycrystalline silicon layer 32 to protect the polycrystalline silicon layer 32 and also to provide electrical insulation from an aluminum light-blocking shield 36 which is located on the portion of the insulating layer 34 that is located over the shift register element 18. The insulating layer 34 `-is preferably a vapor-deposited oxide layer. The thickness of the second polycrystalline silicon layer 32 is preferably about 4000 Angstroms. The thickness of the aluminum light shield i~ preferably about 1 micron and this material thickness serYes to prevent light from passing through the aluminum light-blocking shield 36.
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In one example, an array containing 10,000 photo-sensitive CCD ele-ments was formed o-f 100 x 100 light-sensitive CCD elements 16 and 100 shiFt reyister CCD columns with each column containing 100 shift register elements 18. The light-sensitive CCD elements 16 were formed in a plurality oF vertical shiFt register lines wi-th each one of the shift reyister elements 18 located adjacent to and, as explained above, electrically coupled to a corresponding light-sensitive element 16 to receive, under certain conditions, charge packets generated within and transmitted from the light-sensitive elements 16. For example, transfer of charge packets from the liyht-sensitive CCD element 16 to the shift reyister COD element 18 occurs when the "ver-tical gate" electrode portion of the second polycrystalline line 32 (which is the portion that overlies the frame electrode 28~ is at a higher electrical potential than the electrical potential applied to the "frame gate" elec-trode 28.
In more detail, a potential o-F +5 Yolts applied to the "vertical gate" electrode portion of the second polycrystalline layer 32 as compared with holding the potential of the "fran1e gate" electrode 28 to 0 volts causes the charge packets to laterally pass through the N- buried barrier region 22 from the light-sensitive CCD element 16 to the shift register CCD
element 18. In one embodiment, the width of the ~uried barrier region 22 is about 0.2 mils wide, the width of the "vertical gate" is about 0.9 mils . wide, the width of the P+ channel stop region 20 is about 0.2 mils wide, the width of the "frame gate" electrode 28 is about 0.6 mils wide and the separation distance hetween "vertical gate" electrodes is about 0.~ mils wide.
Referring to FIG. 3, a system is disclosed which includes an imping-ing array 100 which is composed of pluralities oF light-sensitive CCD ele-;: ments 16 and the shift reyister CCD elements 18. In the embodiment wherein 10,000 (100 x 10Q) light-sensitive CCD elements 16 are used in combination with 10Q columns of vertical shift registers (each column contains 100 CCD
shift registers), 50 two-phase vertical shifts (or I00 jumps) are needed to transfer charge packets entering the lowermost shift register elements at ~ `
', , , ' ~ 0~9~2 the hottom portion of -the array 100 to the outermost shi-ft register elements located at the upper portion o-F the array 100. Since the system disclosed in FIfi. 3 is a two-phase CCD system, clock pulses applied to electrodes (~v1 and '~V2 which are electrically connected to alternate, adjacen-t "vertical yates"
(electrode portions of the second polycrystalline layer 32) cause the charge packets to be transferred vertically through the shiFt register CCD elements 18 Forming the vertical shift re~ister CCD lines. As generally disclosed in the above-mentioned copending Kim et al application, control oF the pulsed potentials applied to the electrodes ~v1 and ~v2 causes the charye packets in the shift register CCD elements 18 to be transferred vertically through the vertical shift register CCD line~. A pulsed potential oF, for example, about -8 to about +14 volts applied to the electrodes (~v1 and (~v2 causes the charge packets to be transferred vertically through the shift register CCD elements 18 provided that the pulsed voltages applied to the two electrodes ~v1 and ~V2 are out-of-phase or complementary to each other. When the potential applied to selected vertical gate electrode portions of the second polycrystal-line silicon layer 32 is ~ volts (most positive portion of the potential swing), charge packets are passed through the buried barrier region 23 (or 25) located beneath the vertical gate electrode which is at the most pos-itive potential. The positive ~ volts applied to the vertical gate elec-trode lowers the potential barrier of the associated buried barrier region 23 (or 25) located beneath the most positive vertical gate electrode.
Frame electrode ~F electrically connects a clock ~not shown) to the frame electrodes 28 of the array 100. The clock supplies a swinging voltage of from about 0 to about +10 volts.
In the detailed disclosed embodiment, 100 bits or charge packets are dumped into output register 102 from the array 100 at one time.
Preferably,the two-phase CCD output register 102 contains 102 gates associated with the electrode ~H1 and 102 gates associated with the electrode (~H2. ~H1 and ~H2 are similar to electrodes ~v1 and ~v2 associated with the array 100. Thus, clocks connected to electrodes ~H1 and ~H2 apply a swing-ing voltage of from about -~ to about +~ volts which causes a corresponding : ; :
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potential -to be applied to the gate electrodes associated with each electrode (~H1 and (lH2. The output register 102 has 204 shift register elements of the -type shown by reference numeral 18 in FIGS. 1 and 2. Thus 102 two-phase shifts (or 204 jurr~ps) are needed to move the bits or charge packets from one end oF the output register 102 to the other (or output) end thereof.
Electrically connected to the output portion of the output reyister 102 is an output amplifier 104 to which is electrically connected a source electrode S1 and a drain electrode D1. The output amplifier 10~ is an MOS
or FET type of amplifier of the type disclosed and described in the above-mentioned Kim et al appl-ication. A compensation amplifier 106 made of ~OS
or FET type devices having source S2 and drain D2 electrodes connected there-to is electrically connected to the output amplifier 104 and functions to compensate for the noise generated by reset circuit 108 to which is connected a reset drain electrode RD. A reset clock (not shown) is connected to the reset circuit 108 by means of electrode ~R which is eleotrically connected to the reset circuit 108. The operation of the compensation amplifier 106 and the output amplifier 104 which together function as a differential ampli-fier is disclosed and described in the above-mentioned Kim et al application Which also discusses the need for the reset circuit 108 to clear the appara-tus for the next signal.
At the input portion of the system disclosed in FIG. 3 is an input register llQ which is similar to the output register 102. Thus both the input and output registers use CCD shift register elernents of the type shown generally by reFerence nuDIeral 18 in FIGS. 1 and 2. Accordingly lQ2 two-phase shifts (or 204 jumps.) are needed to move bits or charge packets -From one end ot the input register 110 to the other end thereof. However only one shift is needed to move the charge packets vertically into the array 100. ; ~`
A total of 100 bits or charge packets are moved into the array lOQ from the input register 110. Clocks (not shown) are electrically connected to elec-trodes ~H1' and ~H2' to move the charge packets through the shift registers forming the input register 110. An input section 112 is composed of an input source electrode which is pulsed with a voltage that swings from about S~
-8 to about +4 volts that i.5 connected to an N+ diffused region (not shown).
An input ~ate located over the Nt diffused region is held to a potential of -about O volts. The input source 112 generates electrical signals to the input register 110 and serves as an alternative method oF providing an input to the array 100. Thus the systern of FIG. 3 can be used with a light source input directly striking the light-sensitive elernents 16 of the array 100 or with an electrical (electron) input from the input section 112.
While the invention has been particularly shown and described in reference to the preferred embodiment thereof it will be understood by ~ !
those skilled in the art that changes in the form~and details may be made therein without departing from the spirit and scope of the invention.
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Claims (26)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. An imaging array comprising: a semiconductor substrate having a top surface; a plurality of lines of light-sensitive CCD elements associated with portions of said semiconductor substrate; a corresponding plurality of shift register lines each having a plurality of CCD elements associated with other portions of said semiconductor substrate; and means for transferring charge packets generated in said light-sensitive CCD elements to correspond-ing CCD elements of said shift register lines for subsequent movement within said shift register lines to an output portion of said array, wherein each of said light-sensitive CCD elements is separated from adjacent light-sensitive CCD elements by a heavily doped channel stop region formed in the top surface of said semiconductor substrate, said heavily doped channel stop regions surrounding each light-sensitive CCD element such that every light-sensitive CCD element has open to one of said shift registers a side on which there is no channel stop region.
2. An imaging array in accordance with claim 1 including means for shifting said charge packets along said shift register lines.
3. An imaging array in accordance with claim 2 including means for receiving said charge packets at the end of said shift register lines.
4. An imaging array in accordance with claim 1 wherein said means for transferring charge packets generated in said light-sensitive CCD
elements to corresponding CCD elements of said shift register lines comprises a pair of light-transparent gate electrode means associated with each of said light-sensitive CCD elements.
elements to corresponding CCD elements of said shift register lines comprises a pair of light-transparent gate electrode means associated with each of said light-sensitive CCD elements.
5. An imaging array in accordance with claim 4 wherein each of said pair of light-transparent gate electrode means comprises a doped poly-crystalline silicon electrode.
6. An imaging array in accordance with claim 5 wherein each of said pair of light-transparent gate electrode means comprises a doped polycrystal-line silicon electrode.
7. An imaging array in accordance with claim 1 wherein said means for transferring charge packets generated in said light-sensitive CCD elements to corresponding CCD elements of said shift register lines comprises a pair of light-transparent gate electrode means associated with each of said light-sensitive CCD elements, each of said pair of light-transparent gate elec-trode means comprises a doped polycrystalline silicon electrode, means for shifting said charge packets along said shift register lines, and means for receiving said charge packets at the end of said shift register lines.
8. An imaging array in accordance with claim 1 wherein each of said light-sensitive CCD elements is four sided and said heavily doped channel stop regions surround each light-sensitive CCD element on at least three sides, leaving open to one of said shift registers the fourth side of said light-sensitive CCD element.
9. An imaging array in accordance with claim 1 wherein said light-sensitive CCD elements comprise a buried region of one conductivity type located in a region of opposite conductivity type, and a higher resistivity buried barrier region of said one conductivity type located adjacent to said buried region and on the side on which there is no channel stop region.
10. An imaging array in accordance with claim 9 wherein said one conductivity type is N type and said opposite type conductivity is P type, said heavily doped channel stop region is of P type conductivity.
11. An imaging array in accordance with claim 1 wherein each of said shift registers is covered with an opaque material.
12. An imaging array in accordance with claim 11 wherein said opaque material is aluminum.
13. An imaging array in accordance with claim 1 wherein each of said light-sensitive CCD elements is separated from adjacent light-sensitive CCD elements by a three-sided channel stop region, each of said light-sensitive CCD elements has one open side to said corresponding CCD element of said shift register lines which is not blocked by a channel stop region, a barrier region located along said open side of each of said light-sensitive CCD elements, means lowering the potential barrier of said barrier region to permit charge packets generated in said light-sensitive CCD elements to pass into said corresponding CCD elements of said shift register lines, each of said CCD elements of said shift register lines having a charge packet storage region and a pair of barrier regions one of which is located on one side of said charge packet storage region and the other of which is located on the opposite side of said charge packet storage region, and means for lowering the potential barrier of said barrier regions to permit charge packets located in each of the charge packet storage region to be trans-ferred to the next charge packet storage region.
14. An imaging array in accordance with claim 13 wherein each of said CCD elements of said shift register lines comprising a buried region of one conductivity type located in a region of opposite conductivity type, said pair of barrier regions comprising a pair of higher resistivity buried barrier regions of said one conductivity type located on opposite sides of said buried region, and means for shifting said charge packets along said shift register lines through said barrier regions.
15. An imaging array in accordance with claim 1 wherein each of said light-sensitive CCD elements and each of said CCD elements of said shift register lines comprises a buried region of one conductivity type located within a region of opposite conductivity type, each of said light-sensitive CCD elements and each of said CCD elements of said shift register lines having at least one buried barrier region of said one conductivity type, said buried barrier region having a higher resistivity than said buried region, and a pair of orthogonal gate electrode means associated with each of said light-sensitive CCD elements and said CCD elements of said shift register lines for lowering the potential barrier of said buried barrier region to transfer charge packets into said CCD element of said shift register lines from said light-sensitive CCD elements and to move charge packets through the CCD elements of said shift register lines.
16. An imaging array in accordance with claim 15 wherein each one of said pair of orthogonal gate electrode means comprises a light-transparent gate electrode.
17. An imaging array in accordance with claim 16 wherein both of said pair of orthogonal gate electrode means comprises a doped polycrystal-line silicon electrode.
18. An imaging array in accordance with claim 17 wherein a surface of said semiconductor substrate is covered with an insulating layer of SiO2, a protecting layer of silicon nitride is located on said SiO2 layer, one of said pair of doped polycrystalline silicon electrodes is located on one side of said silicon nitride layer, an insulating layer is located on and electrically insulates the outer surface of said one of said pair of doped polycrystalline silicon electrodes, the other of said pair of doped polycrystalline silicon electrodes is located on both said silicon nitride layer and on said insulating layer, and an encapsulating insulating layer is located on the exterior surface of said other of said pair of doped polycrystalline silicon electrodes.
19. An imaging array in accordance with claim 13 wherein each of said shift registers is covered with an opaque layer of aluminum located on said encapsulating insulating layer.
20. An imaging array comprising:
a semiconductor substrate, a plurality of light-sensitive CCD elements associated with portions of said semiconductor substrate;
a corresponding plurality of shift register lines each having a plurality of CCD elements associated with other portions of said semiconductor substrate, and means for transferring charge packets generated in said light-sensitive CCD elements to corresponding CCD elements of said shift register lines for subsequent movement within said shift register lines to an output portion of said array, said light-sensitive CCD elements comprising a buried region of one conductivity type located in a region of opposite conductivity type, and a higher resistivity buried barrier region of said one conductivity type located adjacent to said buried region.
a semiconductor substrate, a plurality of light-sensitive CCD elements associated with portions of said semiconductor substrate;
a corresponding plurality of shift register lines each having a plurality of CCD elements associated with other portions of said semiconductor substrate, and means for transferring charge packets generated in said light-sensitive CCD elements to corresponding CCD elements of said shift register lines for subsequent movement within said shift register lines to an output portion of said array, said light-sensitive CCD elements comprising a buried region of one conductivity type located in a region of opposite conductivity type, and a higher resistivity buried barrier region of said one conductivity type located adjacent to said buried region.
21. An imaging array in accordance with claim 20 wherein said means for transferring charge packets generated in said light-sensitive CCD
elements to corresponding CCD elements of said shift register lines comprising light-transparent gate electrode means coupled to said barrier region for lowering the potential barrier of said barrier region to permit charge packets generated in said light-sensitive CCD elements to pass into corresponding CCD elements of said shift register lines.
elements to corresponding CCD elements of said shift register lines comprising light-transparent gate electrode means coupled to said barrier region for lowering the potential barrier of said barrier region to permit charge packets generated in said light-sensitive CCD elements to pass into corresponding CCD elements of said shift register lines.
22. An imaging array in accordance with claim 21 wherein said light-transparent gate electrode means comprises a pair of doped polycrystal-line silicon electrodes.
23. An imaging array in accordance with claim 20 wherein said one conductivity type is N type and said opposite type conductivity is P type.
24. An imaging array in accordance with claim 23 wherein said semi-conductor substrate is a silicon substrate.
25. A system for transmitting electrical energy comprising: an imaging array comprising a semiconductor substrate having a top surface and having a plurality of lines of light-sensitive CCD elements associated with portions of said semiconductor substrate; a corresponding plurality of shift register lines each having a plurality of CCD elements associated with other portions of said semiconductor substrate; means for transferring charge packets generated in said light-sensitive CCD elements to corresponding CCD elements of said shift register lines for subsequent movement within said shift register lines to an output portion of said array; and output register means electrically connected to said imaging array for receiving and further transferring the charge packets coming from the output portion of said array, wherein each of said light-sensitive CCD elements is separated from adjacent light-sensitive CCD elements by a heavily doped channel stop region formed in the top surface of said semiconductor substrate, said heavily doped channel stop regions surrounding each light-sensitive CCD element such that every light-sensitive CCD element has open to one of said shift registers a side on which there is no channel stop region.
26. A system in accordance with claim 25 including input register means and electrical input means for transferring electrical input signals into said array.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US39111973A | 1973-08-27 | 1973-08-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1049652A true CA1049652A (en) | 1979-02-27 |
Family
ID=23545328
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA205,678A Expired CA1049652A (en) | 1973-08-27 | 1974-07-25 | Charge-coupled area array |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPS5615592B2 (en) |
| CA (1) | CA1049652A (en) |
| DE (1) | DE2439680A1 (en) |
| FR (1) | FR2242779B1 (en) |
| GB (1) | GB1480761A (en) |
| HK (1) | HK47480A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5636143Y2 (en) * | 1976-09-27 | 1981-08-25 | ||
| JPS5642118U (en) * | 1979-09-06 | 1981-04-17 | ||
| JPS6024093U (en) * | 1983-07-26 | 1985-02-19 | 株式会社日立ホームテック | Heating coil for induction cooker |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5443330B2 (en) * | 1971-08-26 | 1979-12-19 |
-
1974
- 1974-07-25 CA CA205,678A patent/CA1049652A/en not_active Expired
- 1974-07-31 GB GB33848/74A patent/GB1480761A/en not_active Expired
- 1974-08-19 DE DE2439680A patent/DE2439680A1/en active Pending
- 1974-08-23 FR FR7428985A patent/FR2242779B1/fr not_active Expired
- 1974-08-27 JP JP9829574A patent/JPS5615592B2/ja not_active Expired
-
1980
- 1980-08-28 HK HK474/80A patent/HK47480A/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5076995A (en) | 1975-06-24 |
| DE2439680A1 (en) | 1975-03-06 |
| GB1480761A (en) | 1977-07-27 |
| FR2242779A1 (en) | 1975-03-28 |
| FR2242779B1 (en) | 1978-12-01 |
| JPS5615592B2 (en) | 1981-04-10 |
| HK47480A (en) | 1980-09-05 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |
Effective date: 19960227 |