CA1038968A - Manufacture of complementary vertical transistors - Google Patents
Manufacture of complementary vertical transistorsInfo
- Publication number
- CA1038968A CA1038968A CA234,241A CA234241A CA1038968A CA 1038968 A CA1038968 A CA 1038968A CA 234241 A CA234241 A CA 234241A CA 1038968 A CA1038968 A CA 1038968A
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- 230000000295 complement effect Effects 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 239000012535 impurity Substances 0.000 claims abstract description 40
- 238000000034 method Methods 0.000 claims abstract description 26
- 238000010438 heat treatment Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims description 42
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 30
- 229910052796 boron Inorganic materials 0.000 claims description 30
- 229910052698 phosphorus Inorganic materials 0.000 claims description 17
- 239000011574 phosphorus Substances 0.000 claims description 17
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 16
- 229910052785 arsenic Inorganic materials 0.000 claims description 16
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims 3
- 230000000149 penetrating effect Effects 0.000 claims 1
- 238000002955 isolation Methods 0.000 abstract description 28
- 230000000694 effects Effects 0.000 abstract description 7
- 238000009792 diffusion process Methods 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 8
- 238000006243 chemical reaction Methods 0.000 description 8
- 238000005468 ion implantation Methods 0.000 description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 238000011282 treatment Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000007599 discharging Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000005465 channeling Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 150000003017 phosphorus Chemical class 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
- H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
- H01L27/0826—Combination of vertical complementary transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
- H01L21/8228—Complementary devices, e.g. complementary transistors
- H01L21/82285—Complementary vertical transistors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
Abstract
INTEGRATED COMPLEMENTARY VERTICAL TRANSISTORS AND METHOD
Abstract of the Disclosure The invention resides in a monolithic integrated circuit containing complementary bipolar transistors of the vertical configuration and having closely-matched transistor parameters. This structure is achieved by a particular combination of impurity introducing techniques and by matching the particular diffusants used to produce complementary transistors having substantially matching impurity distribution profiles. In particular, a first formed N-type isolation zone for the PNP transistor, in combination with the third-formed boron-doped P-type buried collector and a P-type zone in the epitaxial layer of the PNP transistor is a critical aspect of the device structure. Moreover, the particular sequence and mode of the impurity introducing steps for the base and emitter zones of the respective transistors enable, in effect, individual adjustment of the respective transistor electrical parameters by means of heat treatments, - i -
Abstract of the Disclosure The invention resides in a monolithic integrated circuit containing complementary bipolar transistors of the vertical configuration and having closely-matched transistor parameters. This structure is achieved by a particular combination of impurity introducing techniques and by matching the particular diffusants used to produce complementary transistors having substantially matching impurity distribution profiles. In particular, a first formed N-type isolation zone for the PNP transistor, in combination with the third-formed boron-doped P-type buried collector and a P-type zone in the epitaxial layer of the PNP transistor is a critical aspect of the device structure. Moreover, the particular sequence and mode of the impurity introducing steps for the base and emitter zones of the respective transistors enable, in effect, individual adjustment of the respective transistor electrical parameters by means of heat treatments, - i -
Description
~038968 This invention relates to semiconductor integrated circuits and more particularly, to an integrated circuit structure, and its method of fabrication, which has junction-isolated, complementary, planar bipolar transistors in a monolithic semiconductor body. More particularly, the fabrication method enables a substantially separate adjust-ment of the electrical parameters of the NPN and PNP
transistors.
Background of the Invention In U.S. Patent 3,793,088, granted to W.H. Eckton, Jr., there is set forth the need for and desirable aspects of complementary bipolar monolithic integrated circuits.
The arrangement disclosed in the above-noted patent relies on relatively high resistivity semiconductor material for electrical isolation between adjoining devices. This is not a completely satisfactory configuration for many circuit applications in which a more positive mode of isolation is ` needed. This is particularly so for many linear circuits where high impedance is important. Thus in many applications, more absolute isolation between devices coupled with low parasitic capacitance is essential.
Moreover, it is desirable to avoid having to form more than a single epitaxial vapor-deposited layer in the fabrication of monolithic integrated circuit devices.
- Accordingly, an object of this invention is to produce in a planar semiconductor structure truly complementary bipolar ~ -transistors having a high degree of isolation with closely-r matched and adjustable electrical parameters. It is an object also that this structure be provided without 30 resorting to more than a single vapor-deposited epitaxial ;
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~038968 layer. The foregoing objects are sought not only because of their desirability from the standpoint of device performance, but also from the standpoint of the complexity of fabrication and the consequent cost.
In accordance with one feature of the invention, the complementary symmetry of devices is a consequence of relatively closely-matched impurity concentration profiles.
S = ary of the Invention In accordance with this invention, there is provided a monolithic silicon semiconductor body comprising a P-type substrate and N-type epitaxial layer and including -isolated NPN and PNP buried collector transistors. An important feature of the structure is the formation of a -lightly doped, deep, N-type conductivity diffused zone which isolates the PNP transistor and its buried collector zone from the P-type conductivity substrate. It is significant that the dopant used for this zone is phosphorus.
.In sequence, there is next formed the N-type conductivity buried collector of the NPN transistor. It is significant that arsenic or antimony is the impurity introduced for the formation of this zone. Following this step, the P-type buried collector of the PNP transistor is formed using boron as the significant impurity. This collector is placed within the first-formed N-type isolation zone. Simultaneously with this step, P-type isolation zones of the buried type are also formed adjoining and isolating the NPN transistor. Completion of these steps provides the substrate configuration for the NPN and PNP
transistors and the necessary junction isolation zones in the substrate material. Next there is formed, typically
transistors.
Background of the Invention In U.S. Patent 3,793,088, granted to W.H. Eckton, Jr., there is set forth the need for and desirable aspects of complementary bipolar monolithic integrated circuits.
The arrangement disclosed in the above-noted patent relies on relatively high resistivity semiconductor material for electrical isolation between adjoining devices. This is not a completely satisfactory configuration for many circuit applications in which a more positive mode of isolation is ` needed. This is particularly so for many linear circuits where high impedance is important. Thus in many applications, more absolute isolation between devices coupled with low parasitic capacitance is essential.
Moreover, it is desirable to avoid having to form more than a single epitaxial vapor-deposited layer in the fabrication of monolithic integrated circuit devices.
- Accordingly, an object of this invention is to produce in a planar semiconductor structure truly complementary bipolar ~ -transistors having a high degree of isolation with closely-r matched and adjustable electrical parameters. It is an object also that this structure be provided without 30 resorting to more than a single vapor-deposited epitaxial ;
- 1 - q~ ~ .
~'' '. ;" ' .'' :'' ' .
.. : . ~ . . - .
~038968 layer. The foregoing objects are sought not only because of their desirability from the standpoint of device performance, but also from the standpoint of the complexity of fabrication and the consequent cost.
In accordance with one feature of the invention, the complementary symmetry of devices is a consequence of relatively closely-matched impurity concentration profiles.
S = ary of the Invention In accordance with this invention, there is provided a monolithic silicon semiconductor body comprising a P-type substrate and N-type epitaxial layer and including -isolated NPN and PNP buried collector transistors. An important feature of the structure is the formation of a -lightly doped, deep, N-type conductivity diffused zone which isolates the PNP transistor and its buried collector zone from the P-type conductivity substrate. It is significant that the dopant used for this zone is phosphorus.
.In sequence, there is next formed the N-type conductivity buried collector of the NPN transistor. It is significant that arsenic or antimony is the impurity introduced for the formation of this zone. Following this step, the P-type buried collector of the PNP transistor is formed using boron as the significant impurity. This collector is placed within the first-formed N-type isolation zone. Simultaneously with this step, P-type isolation zones of the buried type are also formed adjoining and isolating the NPN transistor. Completion of these steps provides the substrate configuration for the NPN and PNP
transistors and the necessary junction isolation zones in the substrate material. Next there is formed, typically
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1~38968 by vapor deposition, an N-type conductivity epitaxial layer into which there is the standard out-diffusion from the previously-formed buried conductivity type zones.
From this point, the processing is a sequence of operations involving the introduction of impurities selectively from the surface of the epitaxial layer.
Importantly, these operations provide a P-type conversion zone in the epitaxial layer of the PNP transistor. They produce also deep contact zones, contact enhancement zones, .10 isolation zones, channel stops and guard rings. Also importantly, this series of impurity introduction steps provide in a unique sequence: the N-type base, the P-type -base, the P-type emitter and the N-type emitter so as to enable adjustment of the gain, first of the PNP and then of the NPN transistors without the one affecting the other ~
substantially. ~ -A particularly significant structural feature is an N-type deep contact zone encircling the PNP transistor which has the effect of enabling rapid charging and dis-charging of the collector to substrate parasitic capacitanceas well as providing the more conventional function of inhibiting surface channeling.
Thus, the process in accordance with this invention produces NPN and PNP transistors which have complementary symmetry by virtue of substantially matching, although opposite in conductivity type, impurity doping profiles. Thus, the structure achieved is truly complementary rather than simply being a dual arrangement containing a transistor of each type but whose characteristics may be quite different.
- ~ :
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1~38968 by vapor deposition, an N-type conductivity epitaxial layer into which there is the standard out-diffusion from the previously-formed buried conductivity type zones.
From this point, the processing is a sequence of operations involving the introduction of impurities selectively from the surface of the epitaxial layer.
Importantly, these operations provide a P-type conversion zone in the epitaxial layer of the PNP transistor. They produce also deep contact zones, contact enhancement zones, .10 isolation zones, channel stops and guard rings. Also importantly, this series of impurity introduction steps provide in a unique sequence: the N-type base, the P-type -base, the P-type emitter and the N-type emitter so as to enable adjustment of the gain, first of the PNP and then of the NPN transistors without the one affecting the other ~
substantially. ~ -A particularly significant structural feature is an N-type deep contact zone encircling the PNP transistor which has the effect of enabling rapid charging and dis-charging of the collector to substrate parasitic capacitanceas well as providing the more conventional function of inhibiting surface channeling.
Thus, the process in accordance with this invention produces NPN and PNP transistors which have complementary symmetry by virtue of substantially matching, although opposite in conductivity type, impurity doping profiles. Thus, the structure achieved is truly complementary rather than simply being a dual arrangement containing a transistor of each type but whose characteristics may be quite different.
- 3 -.' . '- .
'''~"' 1~38968 Brief Description of the Drawing The invention and its other objects and features will be more clearly understood from the following detailed description taken in conjunction with the drawing in which:
FIG. 1 is a schematic representation partially in section and in perspective of portions of a monolithic - semiconductor body including complementary NPN and PNP
transistors in accordance with this invention;
FIGS. 2 through 12 inclusive and 7B are sectional views of the portions of FIG. 1 illustrating the significant steps in the fabrication of such complementary transistors;
FIGS. 3A, 4A, 5A, and 7A through 12A inclusive are block diagrams setting forth the processing steps in general terms related to the corresponding sectional views :
above; and ~.
~ FIGS. 13 and 14 are graphs depicting the impurity : concentration profiles of the NPN and PNP transistors, . respectively, in a typical embodiment in accordance with this invention.
Detailed Description The basic configuration of the complementary monolithic device structure of this invention is illustrated in FIG. 1. The break shown between the chip portions 10 and 11 containing the PNP and NPN devices, respectively, is representative of the fact that the complementary devices ~ .
may be located within the monolithic body of semiconductor .: material in a variety of arrangements other than side by ; side as shown. The semiconductor body typically is of : monocrystalline silicon, although it will be understood that other materials may be used The device structure is . . .
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.
. .
1~38968 formed on a common substrate 12, typically of relatively low P-type conductivity, and in an epitaxial layer 13 of moderate N-type conductivity formed on one surface of the substrate. Typically, the P-type substrate has a conduc-tivity of from about 4 to 15 ohm-cm and is monocrystalline, -normally <100> orientation. ~;
Referring first to the chip portion 10 containing the PNP transistor, the N-type isolation zone 14 isolates the P-type collector zone 15 from the substrate 12. The 10 N-type isolation zone 14 is an important feature of the ;-~
device structure and, in effect, extends the epitaxial -~ layer 13 into the substrate portion. The N-type zone 14 is relatively lightly doped and, inasmuch as it is the initially emplaced impurity zone, subsequent heat treatments serve to extend it relatively deeply into the substrate. -. - - :~.
Thus the zone provides the essential electrical isolation - without incurring deleteriously high collector to isolation parasitic capacitance.
The P-type buried collector zone 15 is formed within the substrate portion and particularly within and encompassed by the N-type isolation zone 14. The zone 15 is a very heavily doped zone of P-type conductivity and is surface-contacted by the epitaxial conversion zone 24, ;; enhanced by the deep collector zone 18 which, in turn, is contacted by the metallic electrode 23. Inside of the ` boundaries of the deep collector zone 18 and within the - P-type conversion zone 24 of the epitaxial layer 13, there is provided the N-type base zone 16 and the P-type emitter zone 17. The P-type conversion zone contributes significant- - -- 30 ly to the desired matching impurity profile. A contact ~
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1~38968 enhancement zone 20 to the base zone 16 provides a basis for the attachment of the base electrode 22 and an emitter contact electrode 21 is applied to the emitter zone 17.
Another important feature of the PNP transistor structure is the N-type enhancement zone 19 encircling the entire transistor structure. This zone functions both as a channel stop and as a contacting means to the N-type isolation zone 14, providing a low impedance path enabling fast charging and discharging of the PNP collector isolation junction. Although not shown, electrode means are provided at a surface portion connecting the zone 19 to an electric-ally positive point in the integrated circuit.
The chip portion 11 contains an NPN transistor, likewise of the vertical configuration and of somewhat more conventional arrangement. The collector zone 30 contains, as the significant impurity, the element arsenic in contrast to the phosphorus used for other N-type impurity zones in this device. Antimony may be used as an alternative to arsenic.
The P-type conductivity isolation zones 31 are formed in part by the buried impurity process, thus avoiding the deep diffusions from the epitaxial layer surface and the consequent long heating times usually required to form deep isolation zones by diffusion from the surface. The PNP transistor includes also the base zone 32 and emitter zone 33 with their respective contacting means including an enhancement zone 35 to the base zone 32 and base and emitter electrodes 39 and 38, respectively. Connection from the surface to the buried collector is m de by meens of the deep collector contact . ~.
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1~38968 zone 34 with the contact enhancement zone 36 and metal electrode 40. The advantageous aspects of this structure - will be more apparent from the following description of the mode of fabrication, taken in conjunction with the other figures of the drawing. ~ -As previously noted, fabrication of a complementary structure in accordance with this invention begins with the preparation of a P-type conductivity substrate 12 as represented in FIG. 2. It will be appreciated that the chip 10 portions identified as NPN transistor and PNP transistor -are but a small part of an entire integrated circuit chip containing other circuit elements such as diodes, resistors and capacitors, which itself is one of many produced from a single wafer of silicon semiconductor material. Typically, such wafers are two, three and even four inches in diameter and yield, possibly, hundreds of integrated circuit chips.
This description will treat with the fabrication only of a single PNP and a single NPN transistor within a monolithic body of semiconductor material.
The suitably prepared substrate 12 is treated to -~
form an oxide coating on its surface thereby permitting the formation of an oxide mask which, by well-known photo-lithographic techniques, is shaped to define the N-type isolation zone 14 in the PNP transistor portion of FIG. 3. !~' In a specific embodiment, the N-type conductivity zone 14 is formed by an ion implantation step using phosphorus at ! a dosage of 3 x 10 per square centimeter at 50 Kev. ; ;
All of the ion implantation steps recited herein conveniently ~
may be done at this energy level. Next, as indicated in ~` `
~ 30 FIG. 3A, this ion implantation is followed by a heat `
: - - 7 -.. ~.
~ --~ -~038968 treatment at 1270C. for 5-1/2 hours in an atmosphere of oxygen or oxygen and nitrogen. This heat treatment has the effect of diffusing the implanted impurity more deeply into the surface portion of the substrate 12. The heat treatment step done in oxygen also regenerates the oxide coating as will be the case in subsequent heating steps in this fabrication process. Accordingly, the details relating to the generation of oxide masks will not be repeated for each step but where a selective introduction of an impurity is described, such masking will be understood.
Referring to FIG. 4, the next step in the process is an ion implantation of arsenic to form the N-type zone 30 of the NPN transistor. This implantation is at a dosage of 3 x 10 and, as indicated in FIG. 4A, is ~
followed by a heat treatment, again at 1270C. for 5-1/2 ~- -hours in a mixture of oxygen or oxygen and nitrogen. -The next step is a P-type impurity introduction - selectively to form the buried collector 15 of the PNP
- 20 transistor and the isolation zones 31 of the NPN transistor.
This step involves the ion implantation of boron at a dosage of 1.5 x 1015 per square centimeter and is followed by a heat treatment at 1200C. for 45 minutes in pure oxygen. This latter treatment step is indicated in FIG. 5A. ~-At this point, the substrate has been processed by a unique sequence of impurity introduction steps using specific ~
.
matched diffusants which produces the foundation for the vertical configuration, matched, isolated complementary transistors. The buried zones formed as described above provide complementary device isolation in conjunction with r -- -.
.
. .. .
~038968 uniquely low and very well-matched collector-associated - parasitics, namely, for example, collector series resistance and collector to isolation capacitance.
FIG. 6 depicts the formation of an N-type - conductivity epitaxial layer. This is typically done by conventional vapor deposition techniques to form an - N-type film between about eight and eleven microns thick and having a resistivity of about 0.7 to 1.2 ohms centimeter.
Other techniques are known for forming such epitaxial films including methods such as molecular beam techniques and the practice of this invention is not limited to any partic-ular method. During the formation of the epitaxial layer 13, the heat accompanying the process produces an out-diffusion from the substrate into the epitaxial layer so that the buried impurity zones expand generally in the manner depicted in FIG. 6. Referring to the chip portion 10 in which the PNP transistor is formed, it will be appreciated that the -buried collector zone 15 remains encompassed in the N-type isolation zone 14 which, in effect, constitutes a selective ~
20 extension of the epitaxial layer 13 into the substrate 12. -Advantageously, the phosphorus doped zone 14 has diffused ;
the same extent deeper into the substrate than the arsenic -doped collector zone 30.
The fabrication process continues as indicated in FIG. 7 by a predeposit and diffusion of phosphorus selectively to enable formation of the desired collector connection zone 34 of the NPN transistor and the N-type zone 19 of the PNP transistor. This phosphorus predeposit, .:
as indicated by FIG. 7A, is at 1040C. for a period of 55 to 60 minutes.
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11)38968 - An optional step, illustrated in FIG. 7B, may be used at this point for devices in which it is important to minimize collector series resistance. A selective predeposition of boron at about 1140C. for about 30 minutes is a preliminary step to forming the P-type zone 25 which provide deep connections to the collector of the PNP transistor. The inclusion of this optional step occasions no alteration in subsequent processing steps described hereinafter.
` 10 Then, as indicated in FIG. 8, there is a selective introduction of a P-type impurity such as boron or aluminum by ion implantation into the isolation zone 37 of chip portion 11 and into the epitaxial conversion zone 24 of chip portion 10. The epitaxial conversion zone 24 is a : significant aspect of this invention. In particular, as will be apparent likewise from the discussion of the, impurity profiles as shown in FIGS. 13 and 14, the formation of the P-type zone 24 by boron introduction to convert the original N-type epitaxial material is important to the prov-ision of substantially matching impurity profiles for the complementary devices.
Then, as described in FIG. 8A, following this introduction by means of ion implantation at a dosage of about 2 x 1013, there is a heat treatment at 1200C. for about 120 minutes in pure oxygen. This heat treatment has the effect of driving in both the ion-implanted boron and the predeposited phosphorus of the previous step (FIG. 7) and the predeposited boron illustrated in FIG. 7B.
The following steps constitute the unique process for the fabrication of the base and emitter zones. As ~0;~8968 shown in FIG. 9, the N-ty~e base zone of the PNP transistor is formed by a selective ion implantation of phosphorus in the zone 16 at a dosage of about 3 x 1014 per square centimeter followed by a thirty minute heat treatment in pure oxygen at 1200C.
Next, as shown in FIG. 10, the P-type base zone 32 of the NPN transistor is formed selectively by a predeposition of boron at 870C. for 85 minutes using boron nitride discs as a source, followed by a heat treatment at 1150C. for about thirty minutes in pure oxygen. Also formed selectively during this step is the contact enhancement zone 38 to the P-type isolation zone 37 of chip portion 11 and P-type zone 18 to the :
epitaxial conversion zone 24 of chip portion 10. :
Then, as shown in FIG. 11, a selective boron diffusion at 1100C. for 36 minutes produces the base contact enhancement zone 35 of the NPN transistor in chip . .. . .
portion 11 and, in the chip portion 10, the P-type emitter zone 17 and collector contact enhancement zone 18 of the 20 PNP transistor. As shown in FIG. 12, the final step in : the formation of the two complementary transistors is a - :
selective phosphorus diffusion at 1000C. for about 55 minutes to produce, in chip portion 11, the N-type emitter zone 33 of the NPN transistor and, in chip portion 10, the base contact enhancement zone 20 of the PNP transistor.
It will be noted that the heat treatment steps used to drive in the emitter and base diffusions occur at succeedingly lower temperatures so that a subsequent heat treatment has little effect on the previously emplaced - 11 - .~
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impurity.
The individual adjustment of the gain of the complementary transistor structures is a consequence both of the unique order of forming the emitter and base zones and also the level of impurities provided in the zones by the various impurity introduction processes. It should be noted in particular that these zones are emplaced in the order: N-type base, P-type base, P-type emitter and finally, N-type emitter. Thus the PNP transistor is completed upon the introduction of the P-type emitter by the step illustra-ted in FIGS. 11 and llA. This step involves the diffusion of boron at 1100C. In practice, the gain of this PNP
transistor type is measured following the arbitrary heat treatment which may ensue for thirty-six minutes. Further adjustment in the gain may be made by additional short heat treatments. Then finally the N-type emitter is formed by a phosphorus diffusion at 1000C. for a considerably longer period of time which again may be adjusted to produce the desired gain value. The treatment at 1000C. little affects the boron previously introduced for the P-type emitter.
The impurity profiles finally achieved in a typical embodiment in accordance with this invention are shown in FIGS. 13 and 14 for the NPN and PNP transistors, respectively. Referring to FIG. 13, for the NPN transiStQr the level of arsenic impurity is determined in the portion near the surface constituting the epitaxial layer, by the doping of that N-type layer. The rise in the arsenic level is of course representative of the buried N-type collector. The phosphorus and boron impurity profiles 0 which are determinative of the emitter and base zones are 1~)38968 of a conventional form, the deeper boron impurity being aconsequence of the substrate doping.
Turning to the PNP profile, which is the more difficult to achieve as a substantial match to that of the NPN, the boron impurity level is of particular significance.
In this type of device, the arsenic impurity is a background doping from the epitaxial layer. The phosphorus impurity level is conventional base impurity doping added to the deep N-type buried isolation zone. The boron is a consequence of the epitaxial conversion zone 24 which is, in part, determinative of base-to-collector doping - supplemented by the buried collector zone 15 and by the - -surface diffused P-emitter zone 17. In particular, it is significant that the net impurity profile of the PNP is a relatively close match, but of opposite conductivity type, -to that of the NPN transistor.
The final doping levels for the various zones ;
are significant to the achievement of these relative impurity doping profiles and thus to the complementary 20 characteristic achieved in accordance with this invention. -In particular, the N-type isolation zone 14 which is -characterized as lightly doped, preferably has a depth of ;~
the N-P junction from the top of the substrate of not less than 10 microns and typically 15 microns. The sheet resistivity is not less than 150 ohms per square and a typical value is 250 ohms per square. The N-type collector zone 30, characterized as heayily doped, has a depth from the top of the substrate of from about 5 to 10 microns and a sheet resistivity of less than about 25 ohms per square.
Typical values for this zone are about 7 microns deep and .. ' ~ .
. .
- , - ,, : , ,, 1~)38968 about 20 ohms per square.
The P-type collector zone 15 and P-type isolation zones 31, which are characterized as heavily doped, have depths from the top of the substrate in the range of from about 4 to 8 microns with a sheet resistivity of from about 40 to 100 ohms per square. Typical values for these zones are about 6 microns deep and about 50 ohms per square.
Following the implantation of the various conductivity type zones constituting the complementary transistor structures described above, the device structures are completed by the application of suitable metallization patterns constituting the device inter-connections as well as means for external connection.
Many such arrangements are available in the art utilizing the various combinations of metals. A particular technique suitable for use with the foregoing described processes and providing a beam lead type of structure is disclosed in U.S. Patent 3,808,108, granted April 30, 1974, to G.K. Herb and E.F. Labuda.
The foregoing embodiments are disclosed in terms of particular processing techniques. Although the diffusants and the concentrations of impurities and dimensions are relatively restrictivel-y defined in order to enable one to achieve this advantageous invention, it -will be appreciated that techniques other than those specifically disclosed may become available as equivalent processes which will likewise fall within the scope and spirit of this invention.
-: ~
- .,
'''~"' 1~38968 Brief Description of the Drawing The invention and its other objects and features will be more clearly understood from the following detailed description taken in conjunction with the drawing in which:
FIG. 1 is a schematic representation partially in section and in perspective of portions of a monolithic - semiconductor body including complementary NPN and PNP
transistors in accordance with this invention;
FIGS. 2 through 12 inclusive and 7B are sectional views of the portions of FIG. 1 illustrating the significant steps in the fabrication of such complementary transistors;
FIGS. 3A, 4A, 5A, and 7A through 12A inclusive are block diagrams setting forth the processing steps in general terms related to the corresponding sectional views :
above; and ~.
~ FIGS. 13 and 14 are graphs depicting the impurity : concentration profiles of the NPN and PNP transistors, . respectively, in a typical embodiment in accordance with this invention.
Detailed Description The basic configuration of the complementary monolithic device structure of this invention is illustrated in FIG. 1. The break shown between the chip portions 10 and 11 containing the PNP and NPN devices, respectively, is representative of the fact that the complementary devices ~ .
may be located within the monolithic body of semiconductor .: material in a variety of arrangements other than side by ; side as shown. The semiconductor body typically is of : monocrystalline silicon, although it will be understood that other materials may be used The device structure is . . .
:. ~
.
. .
1~38968 formed on a common substrate 12, typically of relatively low P-type conductivity, and in an epitaxial layer 13 of moderate N-type conductivity formed on one surface of the substrate. Typically, the P-type substrate has a conduc-tivity of from about 4 to 15 ohm-cm and is monocrystalline, -normally <100> orientation. ~;
Referring first to the chip portion 10 containing the PNP transistor, the N-type isolation zone 14 isolates the P-type collector zone 15 from the substrate 12. The 10 N-type isolation zone 14 is an important feature of the ;-~
device structure and, in effect, extends the epitaxial -~ layer 13 into the substrate portion. The N-type zone 14 is relatively lightly doped and, inasmuch as it is the initially emplaced impurity zone, subsequent heat treatments serve to extend it relatively deeply into the substrate. -. - - :~.
Thus the zone provides the essential electrical isolation - without incurring deleteriously high collector to isolation parasitic capacitance.
The P-type buried collector zone 15 is formed within the substrate portion and particularly within and encompassed by the N-type isolation zone 14. The zone 15 is a very heavily doped zone of P-type conductivity and is surface-contacted by the epitaxial conversion zone 24, ;; enhanced by the deep collector zone 18 which, in turn, is contacted by the metallic electrode 23. Inside of the ` boundaries of the deep collector zone 18 and within the - P-type conversion zone 24 of the epitaxial layer 13, there is provided the N-type base zone 16 and the P-type emitter zone 17. The P-type conversion zone contributes significant- - -- 30 ly to the desired matching impurity profile. A contact ~
, ' ' ~ :
,.: .
", '.: :' .
: -; - , . .. .- , . ... :
1~38968 enhancement zone 20 to the base zone 16 provides a basis for the attachment of the base electrode 22 and an emitter contact electrode 21 is applied to the emitter zone 17.
Another important feature of the PNP transistor structure is the N-type enhancement zone 19 encircling the entire transistor structure. This zone functions both as a channel stop and as a contacting means to the N-type isolation zone 14, providing a low impedance path enabling fast charging and discharging of the PNP collector isolation junction. Although not shown, electrode means are provided at a surface portion connecting the zone 19 to an electric-ally positive point in the integrated circuit.
The chip portion 11 contains an NPN transistor, likewise of the vertical configuration and of somewhat more conventional arrangement. The collector zone 30 contains, as the significant impurity, the element arsenic in contrast to the phosphorus used for other N-type impurity zones in this device. Antimony may be used as an alternative to arsenic.
The P-type conductivity isolation zones 31 are formed in part by the buried impurity process, thus avoiding the deep diffusions from the epitaxial layer surface and the consequent long heating times usually required to form deep isolation zones by diffusion from the surface. The PNP transistor includes also the base zone 32 and emitter zone 33 with their respective contacting means including an enhancement zone 35 to the base zone 32 and base and emitter electrodes 39 and 38, respectively. Connection from the surface to the buried collector is m de by meens of the deep collector contact . ~.
.
.
.
. . ' , ' ~
1~38968 zone 34 with the contact enhancement zone 36 and metal electrode 40. The advantageous aspects of this structure - will be more apparent from the following description of the mode of fabrication, taken in conjunction with the other figures of the drawing. ~ -As previously noted, fabrication of a complementary structure in accordance with this invention begins with the preparation of a P-type conductivity substrate 12 as represented in FIG. 2. It will be appreciated that the chip 10 portions identified as NPN transistor and PNP transistor -are but a small part of an entire integrated circuit chip containing other circuit elements such as diodes, resistors and capacitors, which itself is one of many produced from a single wafer of silicon semiconductor material. Typically, such wafers are two, three and even four inches in diameter and yield, possibly, hundreds of integrated circuit chips.
This description will treat with the fabrication only of a single PNP and a single NPN transistor within a monolithic body of semiconductor material.
The suitably prepared substrate 12 is treated to -~
form an oxide coating on its surface thereby permitting the formation of an oxide mask which, by well-known photo-lithographic techniques, is shaped to define the N-type isolation zone 14 in the PNP transistor portion of FIG. 3. !~' In a specific embodiment, the N-type conductivity zone 14 is formed by an ion implantation step using phosphorus at ! a dosage of 3 x 10 per square centimeter at 50 Kev. ; ;
All of the ion implantation steps recited herein conveniently ~
may be done at this energy level. Next, as indicated in ~` `
~ 30 FIG. 3A, this ion implantation is followed by a heat `
: - - 7 -.. ~.
~ --~ -~038968 treatment at 1270C. for 5-1/2 hours in an atmosphere of oxygen or oxygen and nitrogen. This heat treatment has the effect of diffusing the implanted impurity more deeply into the surface portion of the substrate 12. The heat treatment step done in oxygen also regenerates the oxide coating as will be the case in subsequent heating steps in this fabrication process. Accordingly, the details relating to the generation of oxide masks will not be repeated for each step but where a selective introduction of an impurity is described, such masking will be understood.
Referring to FIG. 4, the next step in the process is an ion implantation of arsenic to form the N-type zone 30 of the NPN transistor. This implantation is at a dosage of 3 x 10 and, as indicated in FIG. 4A, is ~
followed by a heat treatment, again at 1270C. for 5-1/2 ~- -hours in a mixture of oxygen or oxygen and nitrogen. -The next step is a P-type impurity introduction - selectively to form the buried collector 15 of the PNP
- 20 transistor and the isolation zones 31 of the NPN transistor.
This step involves the ion implantation of boron at a dosage of 1.5 x 1015 per square centimeter and is followed by a heat treatment at 1200C. for 45 minutes in pure oxygen. This latter treatment step is indicated in FIG. 5A. ~-At this point, the substrate has been processed by a unique sequence of impurity introduction steps using specific ~
.
matched diffusants which produces the foundation for the vertical configuration, matched, isolated complementary transistors. The buried zones formed as described above provide complementary device isolation in conjunction with r -- -.
.
. .. .
~038968 uniquely low and very well-matched collector-associated - parasitics, namely, for example, collector series resistance and collector to isolation capacitance.
FIG. 6 depicts the formation of an N-type - conductivity epitaxial layer. This is typically done by conventional vapor deposition techniques to form an - N-type film between about eight and eleven microns thick and having a resistivity of about 0.7 to 1.2 ohms centimeter.
Other techniques are known for forming such epitaxial films including methods such as molecular beam techniques and the practice of this invention is not limited to any partic-ular method. During the formation of the epitaxial layer 13, the heat accompanying the process produces an out-diffusion from the substrate into the epitaxial layer so that the buried impurity zones expand generally in the manner depicted in FIG. 6. Referring to the chip portion 10 in which the PNP transistor is formed, it will be appreciated that the -buried collector zone 15 remains encompassed in the N-type isolation zone 14 which, in effect, constitutes a selective ~
20 extension of the epitaxial layer 13 into the substrate 12. -Advantageously, the phosphorus doped zone 14 has diffused ;
the same extent deeper into the substrate than the arsenic -doped collector zone 30.
The fabrication process continues as indicated in FIG. 7 by a predeposit and diffusion of phosphorus selectively to enable formation of the desired collector connection zone 34 of the NPN transistor and the N-type zone 19 of the PNP transistor. This phosphorus predeposit, .:
as indicated by FIG. 7A, is at 1040C. for a period of 55 to 60 minutes.
_ g _ ' .
.,,,,~ ,. ".
- r=
.. .
... . . . ; . ~ . ... ~ .. . ' .. . . .. ;.;.... ... ..
.. . - ~.. -~ . . ~ . .. .
11)38968 - An optional step, illustrated in FIG. 7B, may be used at this point for devices in which it is important to minimize collector series resistance. A selective predeposition of boron at about 1140C. for about 30 minutes is a preliminary step to forming the P-type zone 25 which provide deep connections to the collector of the PNP transistor. The inclusion of this optional step occasions no alteration in subsequent processing steps described hereinafter.
` 10 Then, as indicated in FIG. 8, there is a selective introduction of a P-type impurity such as boron or aluminum by ion implantation into the isolation zone 37 of chip portion 11 and into the epitaxial conversion zone 24 of chip portion 10. The epitaxial conversion zone 24 is a : significant aspect of this invention. In particular, as will be apparent likewise from the discussion of the, impurity profiles as shown in FIGS. 13 and 14, the formation of the P-type zone 24 by boron introduction to convert the original N-type epitaxial material is important to the prov-ision of substantially matching impurity profiles for the complementary devices.
Then, as described in FIG. 8A, following this introduction by means of ion implantation at a dosage of about 2 x 1013, there is a heat treatment at 1200C. for about 120 minutes in pure oxygen. This heat treatment has the effect of driving in both the ion-implanted boron and the predeposited phosphorus of the previous step (FIG. 7) and the predeposited boron illustrated in FIG. 7B.
The following steps constitute the unique process for the fabrication of the base and emitter zones. As ~0;~8968 shown in FIG. 9, the N-ty~e base zone of the PNP transistor is formed by a selective ion implantation of phosphorus in the zone 16 at a dosage of about 3 x 1014 per square centimeter followed by a thirty minute heat treatment in pure oxygen at 1200C.
Next, as shown in FIG. 10, the P-type base zone 32 of the NPN transistor is formed selectively by a predeposition of boron at 870C. for 85 minutes using boron nitride discs as a source, followed by a heat treatment at 1150C. for about thirty minutes in pure oxygen. Also formed selectively during this step is the contact enhancement zone 38 to the P-type isolation zone 37 of chip portion 11 and P-type zone 18 to the :
epitaxial conversion zone 24 of chip portion 10. :
Then, as shown in FIG. 11, a selective boron diffusion at 1100C. for 36 minutes produces the base contact enhancement zone 35 of the NPN transistor in chip . .. . .
portion 11 and, in the chip portion 10, the P-type emitter zone 17 and collector contact enhancement zone 18 of the 20 PNP transistor. As shown in FIG. 12, the final step in : the formation of the two complementary transistors is a - :
selective phosphorus diffusion at 1000C. for about 55 minutes to produce, in chip portion 11, the N-type emitter zone 33 of the NPN transistor and, in chip portion 10, the base contact enhancement zone 20 of the PNP transistor.
It will be noted that the heat treatment steps used to drive in the emitter and base diffusions occur at succeedingly lower temperatures so that a subsequent heat treatment has little effect on the previously emplaced - 11 - .~
:'-. ~ '.
.
' "~ .
- r -~
.. . .
.. . . . .
impurity.
The individual adjustment of the gain of the complementary transistor structures is a consequence both of the unique order of forming the emitter and base zones and also the level of impurities provided in the zones by the various impurity introduction processes. It should be noted in particular that these zones are emplaced in the order: N-type base, P-type base, P-type emitter and finally, N-type emitter. Thus the PNP transistor is completed upon the introduction of the P-type emitter by the step illustra-ted in FIGS. 11 and llA. This step involves the diffusion of boron at 1100C. In practice, the gain of this PNP
transistor type is measured following the arbitrary heat treatment which may ensue for thirty-six minutes. Further adjustment in the gain may be made by additional short heat treatments. Then finally the N-type emitter is formed by a phosphorus diffusion at 1000C. for a considerably longer period of time which again may be adjusted to produce the desired gain value. The treatment at 1000C. little affects the boron previously introduced for the P-type emitter.
The impurity profiles finally achieved in a typical embodiment in accordance with this invention are shown in FIGS. 13 and 14 for the NPN and PNP transistors, respectively. Referring to FIG. 13, for the NPN transiStQr the level of arsenic impurity is determined in the portion near the surface constituting the epitaxial layer, by the doping of that N-type layer. The rise in the arsenic level is of course representative of the buried N-type collector. The phosphorus and boron impurity profiles 0 which are determinative of the emitter and base zones are 1~)38968 of a conventional form, the deeper boron impurity being aconsequence of the substrate doping.
Turning to the PNP profile, which is the more difficult to achieve as a substantial match to that of the NPN, the boron impurity level is of particular significance.
In this type of device, the arsenic impurity is a background doping from the epitaxial layer. The phosphorus impurity level is conventional base impurity doping added to the deep N-type buried isolation zone. The boron is a consequence of the epitaxial conversion zone 24 which is, in part, determinative of base-to-collector doping - supplemented by the buried collector zone 15 and by the - -surface diffused P-emitter zone 17. In particular, it is significant that the net impurity profile of the PNP is a relatively close match, but of opposite conductivity type, -to that of the NPN transistor.
The final doping levels for the various zones ;
are significant to the achievement of these relative impurity doping profiles and thus to the complementary 20 characteristic achieved in accordance with this invention. -In particular, the N-type isolation zone 14 which is -characterized as lightly doped, preferably has a depth of ;~
the N-P junction from the top of the substrate of not less than 10 microns and typically 15 microns. The sheet resistivity is not less than 150 ohms per square and a typical value is 250 ohms per square. The N-type collector zone 30, characterized as heayily doped, has a depth from the top of the substrate of from about 5 to 10 microns and a sheet resistivity of less than about 25 ohms per square.
Typical values for this zone are about 7 microns deep and .. ' ~ .
. .
- , - ,, : , ,, 1~)38968 about 20 ohms per square.
The P-type collector zone 15 and P-type isolation zones 31, which are characterized as heavily doped, have depths from the top of the substrate in the range of from about 4 to 8 microns with a sheet resistivity of from about 40 to 100 ohms per square. Typical values for these zones are about 6 microns deep and about 50 ohms per square.
Following the implantation of the various conductivity type zones constituting the complementary transistor structures described above, the device structures are completed by the application of suitable metallization patterns constituting the device inter-connections as well as means for external connection.
Many such arrangements are available in the art utilizing the various combinations of metals. A particular technique suitable for use with the foregoing described processes and providing a beam lead type of structure is disclosed in U.S. Patent 3,808,108, granted April 30, 1974, to G.K. Herb and E.F. Labuda.
The foregoing embodiments are disclosed in terms of particular processing techniques. Although the diffusants and the concentrations of impurities and dimensions are relatively restrictivel-y defined in order to enable one to achieve this advantageous invention, it -will be appreciated that techniques other than those specifically disclosed may become available as equivalent processes which will likewise fall within the scope and spirit of this invention.
-: ~
- .,
Claims (8)
1. Method of making a monolithic integrated circuit in a body of semiconductor material including complementary vertical bipolar transistors comprising (a) preparing a high resistivity P-type substrate, (b) introducing phosphorus into a selected surface portion of said substrate, (c) next, introducing arsenic into another selected surface portion of said substrate, (d) next, introducing boron into a selected surface portion less than the whole of said phosphorus-doped portion, said boron-doped portion being wholly encompassed by said phosphorus-doped portion, and also at the same time introducing boron into a selected surface portion surrounding and spaced away from said arsenic-doped surface portion.
2. Method of making monolithic integrated circuit in a body of semiconductor material including complementary vertical bipolar transistors comprising (a) preparing a high resistivity P-type substrate, (b) introducing phosphorus into a selected surface portion of said substrate, (c) next, introducing arsenic into another selected surface portion of said substrate, (d) next, introducing boron into a selected surface portion less than the whole of said phosphorus-doped portion, said boron-doped portion being wholly en-compassed by said phosphorus-doped portion, and also at the same time introducing boron into a selected surface portion surrounding and spaced away from said arsenic doped surface portion, and (e) depositing on the surface of said substrate including said selected surface portions an epitaxial layer of N-type conductivity material containing arsenic as the significant impurity.
3. Method of making a monolithic integrated circuit in a body of semiconductor material including complementary vertical bipolar transistors comprising (a) preparing a high resistivity P-type substrate, (b) introducing phosphorus into a selected surface portion of said substrate, (c) next, introducing arsenic into another selected surface portion of said substrate, (d) next, introducing boron into a selected surface portion less than the whole of said phosphorus-doped portion, said boron-doped portion being wholly encompassed by said phosphorus-doped portion, and also at the same time introducing boron into a selected surface portion surrounding and spaced away from said arsenic-doped surface portion, (e) depositing on the surface of said substrate including said selected surface portions an epitaxial layer of N-type conductivity material containing arsenic as the significant impurity, and (f) introducing boron into a selected portion of said epitaxial layer adjacent the said boron-doped portion of said substrate the boron thereby to convert a portion of said N-type epitaxial layer to P-type.
4. Method of making a monolithic integrated circuit in a body of semiconductor material including complementary vertical bipolar transistors comprising (a) preparing a high resistivity P-type substrate, (b) introducing phosphorus into a selected surface portion of said substrate, (c) next, introducing arsenic into another selected surface portion of said substrate, (d) next, introducing boron into a selected surface portion less than the whole of said phosphorus-doped portion, said boron-doped portion being wholly encompassed by said phosphorus-doped portion, and also at the same time introducing boron into a selected surface portion surround-ing and spaced away from said arsenic-doped surface portion, (e) depositing on the surface of said substrate including said selected surface portions an epitaxial layer of N-type conductivity material containing arsenic as the significant impurity, (f) introducing boron into a selected portion of said epitaxial layer adjacent the said boron-doped portion of said substrate thereby to convert a portion of said N-type epitaxial layer to P-type, (g) forming within said boron-doped converted P-type portion of said epitaxial layer an N-type base zone, (h) next, forming within the portion of said N-type epitaxial layer adjoining said arsenic-doped portion of said substrate a P-type base zone, (l) next, forming within said N-type base zone a P-type emitter zone, and (m) next, forming within said P-type base zone an N-type emitter zone.
5. The method in accordance with claim 4 including the steps of (a) during step (i) heating the body at about 1100° C. for a period of time determined by first measured device parameters, and (b) during step (j) heating the body at about 1000° C. for a period of time determined by second measured device parameters.
6. The method in accordance with claim 5 including the step of introducing phosphorus into a selected surface portion of said epitaxial layer surrounding and spaced away from said boron-doped converted P-type zone and penetrating to said phosphorus-doped portion at said substrate surface.
7. The method in accordance with claim 3 wherein, in step (f), the selected portion of said epitaxial layer into which boron is introduced is substantially co-extensive with the boron doped portion of step (d), thereby converting all of the N-type epitaxial layer above said boron doped portion to p-type.
8. The method in accordance with claim 4, wherein the N-type base zone of step (g) is formed by reconverting the boron doped converted p-type portion of said epitaxial layer to N-type material.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US50757074A | 1974-09-19 | 1974-09-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1038968A true CA1038968A (en) | 1978-09-19 |
Family
ID=24019174
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA234,241A Expired CA1038968A (en) | 1974-09-19 | 1975-08-27 | Manufacture of complementary vertical transistors |
Country Status (10)
| Country | Link |
|---|---|
| JP (1) | JPS5157172A (en) |
| BE (1) | BE833455A (en) |
| CA (1) | CA1038968A (en) |
| DE (1) | DE2541161A1 (en) |
| ES (1) | ES440909A0 (en) |
| FR (1) | FR2285717A1 (en) |
| GB (1) | GB1525247A (en) |
| IT (1) | IT1042581B (en) |
| NL (1) | NL7510994A (en) |
| SE (1) | SE403214B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55143064A (en) * | 1979-04-24 | 1980-11-08 | Nec Corp | Semiconductor device |
| JPS57106046A (en) * | 1980-12-23 | 1982-07-01 | Toshiba Corp | Manufacture of semiconductor device |
| JPH0713969B2 (en) * | 1986-01-13 | 1995-02-15 | 三洋電機株式会社 | Vertical PNP transistor |
| GB2186117B (en) * | 1986-01-30 | 1989-11-01 | Sgs Microelettronica Spa | Monolithically integrated semiconductor device containing bipolar junction,cmosand dmos transistors and low leakage diodes and a method for its fabrication |
| EP0347550A3 (en) * | 1988-06-21 | 1991-08-28 | Texas Instruments Incorporated | Process for fabricating isolated vertical and super beta bipolar transistors |
-
1975
- 1975-08-27 CA CA234,241A patent/CA1038968A/en not_active Expired
- 1975-09-10 SE SE7510075A patent/SE403214B/en unknown
- 1975-09-16 BE BE160072A patent/BE833455A/en unknown
- 1975-09-16 IT IT27273/75A patent/IT1042581B/en active
- 1975-09-16 DE DE19752541161 patent/DE2541161A1/en not_active Withdrawn
- 1975-09-18 NL NL7510994A patent/NL7510994A/en not_active Application Discontinuation
- 1975-09-18 JP JP50112210A patent/JPS5157172A/ja active Pending
- 1975-09-18 FR FR7528624A patent/FR2285717A1/en active Granted
- 1975-09-19 GB GB38498/75A patent/GB1525247A/en not_active Expired
-
1976
- 1976-01-23 ES ES440909A patent/ES440909A0/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| NL7510994A (en) | 1976-03-23 |
| GB1525247A (en) | 1978-09-20 |
| SE7510075L (en) | 1976-03-22 |
| IT1042581B (en) | 1980-01-30 |
| DE2541161A1 (en) | 1976-04-01 |
| FR2285717B1 (en) | 1980-04-30 |
| FR2285717A1 (en) | 1976-04-16 |
| JPS5157172A (en) | 1976-05-19 |
| BE833455A (en) | 1976-01-16 |
| ES440909A0 (en) | 1977-03-16 |
| SE403214B (en) | 1978-07-31 |
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