CA1036679A - Frequency synthesizer using spectrum shift interpolation - Google Patents

Abstract

FREQUENCY SYNTHESIZER USING SPECTRUM SHIFT INTERPOLATION.
ABSTRACT OF THE DISCLOSURE.
According to a particular embodiment of the present invention, a frequency synthesizer system is provided for producing a signal having a frequency which is variable in discrete steps over a pre-determined frequency range. Each frequency step has a predetermined maximum size and means are provided for including interpolation frequencies between each step. The frequency synthesizer system comprises circuit means for combining a primary reference signal with a selected sub-harmonic of an externally generated interpolation signal frequency to produce a secondary reference signal frequency.
A harmonic selection system generates harmonics of the secondary reference signal frequency and in response to a programming system selects a harmonic of the secondary reference signal having the same harmonic number as the selected sub-harmonic of the interpolation frequency. The harmonic selection system generates a control sig-nal which controls the frequency of a controllable oscillator tuning and phaselocking the frequency of the controllable oscillator to a frequency equal to the frequency of the selected harmonic of the secondary reference signal frequency. Using the programming system the frequency of the controllable oscillator can be varied in steps, each having a maximum sizeequal to the primary reference frequency thereby generating a frequency which is displaced from the frequency of a harmonic of the primary reference signal by the interpolation frequency.

Description

1~36679 This invention relates to a frequency synthesizer which prbduces an output signal having a decimal adjustable frequency. The output frequency is derived from a stable frequency source such as a crystal controlled oscillator and may be varied over a prescribed frequency range.

In known systems of multi-decade frequency synthesis one of two basic techniques is generally employed. The first is a gated frequency divider system and the second a pulse synchronized system in combination with side chain arrangements which employ numerous oscillators generating frequencies slightly displaced from each other.

- In the gated frequency divider system a signal from a controllable oscillator is divided down in frequency by a chain of decade frequency dividers. Each divider, except the final one, is provided with a gate actuated programming system allowing it to absorb a number of cycles of the input signal, from a related divider only, for one complete cycle. This is done by using gated frequency divider circuits and gènerating a trigger signal from the output of the entire divider chain to reset the gating system. Consequently, depending on the programmed divider ratio, a number of pulses is added to the number which is required to cause an output pulse to be generated by the related dividcr. The last divider of the chain is a conventional programmable divider. The output signal frequency of the entire divider chain is compared with a precise, highly stable reference signal having a frequency equal to the smallest interpolation ~requency step in the system.

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Frequency comparison may be carried out by a phase discriminator having an output signal which is used to control the frequency of a controllable oscillator ~ until a phase-lock occurs between the divider chain output signal frequency and the reference signal frequency.
The controllable oscillator frequency then equals the reference frequency multiplied by the programmed digital figures of the successive dividers counting from the largest digital step as determined by the last frequency divider.

The advantages of this system include unambiguous frequency lock-in over a relatively wide frequency range and the abs,ence of a requirement for any form of tuned circuit or auxiliary oscillators.
~owever, when relative]y high output frequencies are re-quired high speed divider and gating circuits are necessary.
Such circuits are difficult to design and are relatively expensive. A further disadvantage occurs in a situation where multiple digits are concerned since the phase stability of the output oscillator is poor due to the large division ratio, unless special additional arrange-; ments are made. This in turn adds to the complexity of the system.

The second technique employs a pulse synchronizedsystem in which a signal from a controllable oscillator is mixed in a contrpllable pulse mixer circuit with a first frequency spe~trum which contains harmonics of a primary reference frequency used in the system. The output from the mixer provides a control signal for the controllable oscillator thereby synchronizing its output frequency with a selected harmonic frequency contained in the first , ., ~ ~, ~ . .

' ` 1~366q9 frequency spectrum. The selection of a specific harmonic frequency is controlled either by pretuning the controllable oscillator frequency to the vicinity of the desired output frequency or by means of a digital control system.

A second harmonic spectrum is generated and coupled into a second pulse mixer. The second harmonic spectrum contains harmonic frequencies of an auxiliary reference frequency. The harmonics in the second harmonic spectrum have frequencies which differ slightly from the harmonic frequencies contained in the first harmonic spectrum. The frequency difference is such that the output signal from the second pulse mixer can be used to operate the first pulse mixer and thereby inhibit a phase-lock on all harmonics in the first harmonic spectrum except for the desired one.
Alternatively, the auxiliary pulse mixer provides a signal which has a specific frequency which enabl~es a phase-lock on the desired harmonic of the reference pulse spectrum. Frequency selection i~ performed by shifting the fundamental frequency of the second frequency spectru~
and comparing the difference between the primary reference frequency and the auxiliary reference frequency with the output of a programmed frequency divider having a variable dividing ratio. The choice of the selected frequency is determined by selecting the dividing ratio.

Pulse synchronized systems have an advantage over gated divider systems because pulse mixing can be performed relatively simply at a considerably higher frequency than can be attained with a programmed gated divider system. Moreover, the phase stability of the .'' ~36679 pulse synchronized system is substantially greater since the maximum phase difference in the order of one radian is a practical limit. However, in order to convert a basic pulse synchronized system to a multi-decade system a number of phase-locked oscillators are usually required.
These oscillators are then phase-locked on frequency spectra with different interpolations steps as basic frequencie~s. The signals from these oscillators are intermixed and the difference frequencies are phase-locked to still another oscillator.

Consequently, this system requires oscillators on or near the output frequency which requires relatively , -accurate frequency tracking when a different output frequency is selected.

Several other methods of frequency synthesis are known and genèrally described in Frequency Synthesizers/
- A Survey of Techniques, by J. Noordanus IEEE Transactions on Communication Technology, Volume COM 17, No. 2, April, 1969. These techniques generally lead to an increased amount of complexity in the frequency synthesizer systems ' in which they are employed.

It is the purpose of the present invention to provide a frequency synthesizer which uses digital techniques and which provides a simplified frequency synthesizer employing pulse mixers while avoiding the use of side chain oscillators at high frequencies.
According to a particular prefe~red embodiment of the present invention a frequency synthesizer system is provided for producing an output signal having a frequency which is variable over a predetermined frequency range. The output signal may be varied in discrete fre-quency steps having a predetermined maximum size. Interpo-, , ~, , , :
.. . .

1~366q9 lation steps between each discrete frequency stepare also provided.

A crystal controlled oscillator is used to generate a primary reference signal frequency.
This frequency or a sub-harmonic of it corresponds to the largest discrete frequency step in the output signal. The interpolation steps are included by , generating a secondary reference signal frequency having a frequency equal to the primary reference signal frequency displaced by a selected sub-harmonic of an interpolation signal frequency. The interpo-lation signal is generated externally. A variable ratio frequency divider coup;ed to the interpolation signal is used for producing the selected sub-harmonic of the interpolation signal frequency. The secondary reference signal frequency may be produced by a con-trollable oscillator having a feedback control loop responsive to a signal derived from the primary reference signal and a signal derived from the sub-harmonic of the interpolation si~nal. The fe'edback control loop `
establishes the frequency of the controllable oscillator at a value equal to the secondary refe~ence signal frequency.

A programming system provides a control signal which has a unique value for each harmonic of the secondary reference signal frequency. The programming control signal is coupled to a harmonic selection system which generates a further control signal for controlling a controllable output oscillator which gencrates the variable frequency output s gnal. Depending on the . ~
,. ,, , , .:

i~3~6~,9 particular unique value of the programming control signal, the harmonic selection system causes the controllable oscillator to oscillate at a frequency equal to a selected harmonic of the secondary reference signal frequency. The harmonic selected has the same harmonic number as the selected sub-harmonic of the interpolation signal frequency. Consequently, the controllable output oscillator generates a signal having a frequency equal to the selected harmonic of the primary reference signal frequency displaced by a frequency equal to the interpolation signal frequency.

Further objects and advantages of the present invention will appear from the following descrip- !
tion taken together with the accompanying drawings, in ~
which: ¦
Fig. 1 is a block diagram of a frequency synthesis element;
Fig. 2 is a block diagram of a multi-decade frequency synthesizer based on successive repetitions of the frequency synthesis elemènt shown in Fig. l;
, Fig. 3 is a block diagram of an embodiment of the multi-decade frequency synthesizer shown in Fig. 2, employing a time sharing scheme;
` Fig. 4 is a block diagram of another embodi-ment of the multi-decade frequency synthesizer shown in Fig. 2;
Fig. 5 is a block diagram of a multi-decade frequency synthesizer comprising the basic frequency synthesis element shown in Fig. 1 used with a gated divider interpolation system;

, . ~ .

Fig. 6 is a partial block diagram of the multi-decade frequency synthesizer shown in Fig. 5 including additional components for increasing the phase stability of the multi-decade frequency synthesizer output frequency; and Fig. 7 is a partial block diagram of the multi-decade frequency synthesizer shown in Fig. 5, including further added components to increase phase stability.
Fig. 1 shows at reference numeral 10, a block diagram of a frequency synthesis element for use in a multi-decade frequency synthesizer. The frequency synthe-sis system shown is based on the use of a pulse synchronized system using digital techniques for harmonic selection.
The general operation of the frequency synthesis element 10 may be described as follows. The desired output signal is provided by a controllable oscillator having a variable output frequency fO which is phase-locked on a se~ected harmonic in a first harmonic spectra containing harmonics of a fundamental frequency equal~to a primary reference frequency fl. This establishes the largest decimal step in the system. Interpolation to lower decade steps is not accomplished by the use of side chain arrangements but rather the primary reference frequency from which the first harmonic spectra is generated is shifted by an amount required to provide the desired interpolation to lower decade steps.

The frequency shift requires shifting the frequency of the primary reference frequency by an amount equal to the required interpolation frequency divided by a factor n, where n is the harmonic number of the selected .. . . , . ~ ~ . . . . . .

366~9 harmonic of the primary reference frequency. As a result the controllable oscillator frequency fO is displaced with respect to the primary reference frequency of the system by an amount equal to the required interpolation frequency. Two similarly programmed frequency dividers are employed to produce the required interpolation frequency shift. One frequency divider determines the harmonic of the primary reference frequency on which the controllable oscillator is to be phase-locked and the other frequency divider divides the value of the interpo-lation frequency by an amount equal to the harmonic number of the selected harmonic in the first harmonic spectra.

The above method is explained in further detail by specific reference to the elements shown in Fig. 1.
A primary reference frequency fl is generated by a crystal controlled oscillator 12. The spacing between adjacent harmonics of the primary reference signal frequency represent the largest decade steps permitted.

The remainder of the system may be conveniently considered in two separate parts. The first part provides a method of phase-locking the output signal frequency fO on line 14 to a secondary reference signal frequency fl generated (to ~e described) by the second part. The secondary reference signal frequency is equal to the primary reference frequency signal displaced (in a manner to be described) by the required interpolation frequency - shift.

The output signal on line 14 is generated by a voltage controlled osciilator 16. Oscillator 16 is _ g _ 1~36679 phase-locked to the secondary reference signal frequency fl present on line 18.

The signal on line 18 is directed to a con-- ventional pulse generator 20, via line 22. The pulse generator 20 is preferably a multi-vibrator circuit or a schmitt-trigger followed by a pulse sharpening circuit, both of which are conventional in the art. Pulse generator 20 transforms the signal on line 18 into a harmonic rich pulse train having a fundamental frequency fl. The harmonics in this pulse train form a first harmonic spectrum The pulse train-signal from pulse generator 20 is fed to a first pulse mixer 24. The pulse mixer 24 also receives a signal from amplifier 28 via line 30. The signal from amplifier 28 is derived from the output signal of oscillator 16 via lines 32, 34. The primary purpose of amplifier 28 is to isolate oscillator 16 from ~`
pulse mixer 24 to prevent detuning the oscillator. In addition, pulse mixer 24 is controllable (in the sense of being enabled or inhibited) by a signal on line 36 generated by a frequency selective gate, generally indicated by numeral 38 (to be described). Vnless an appropriate signal is generated by gate 38 pulse mixer 24 remains inhibited.

Enabling or inhibiting pulse mixer 24 may be accomplished by conventional means familiar to those skilled in the art7 For example, pulse mixer 24 may be a balanced or unbalanced diode mixer in which the diodes are normally biased to an 'OFF' condition unless gate 38 generates an appropriate signal on line 36. Alternatively, the signal from gate 38 can be used to enable amplifier i6~79

2~ lViliC`~ irl -t~ls ce~e woul~l nor~ lly l)e inonera-tive tlereby prevell-tirlg ~t~le ~~opearance o: a signal on line 30.

~ hen the signal on line 36 enables pulse mixer 24, t'ne mixer output sig-nal i3 directed to a low pass filter 40 via line 42. The ou-tput signal frorn filter 40, resultirlg in a slowly varying ~C level is fed via line 4a to a hunting oscilla-tor 48 and then by means to be described via line 50 to a frequency control system 46 which is part of oscillator 16.
~requency control system 46 is conventional and knovm to those skilled in the art. ~or example, the frequency control system may be one of the known varactor diode control systems and may involve tuning of related circuits ~ not shown) as well as oscilla-tor 16.
A hlmting signal is also injected into frequency control system 46 via line 50. This signal is typically a 50 to 100 cycle per second periodic saw-tooth voltage generated by hunting oscillator 48. mhe hunting signal when applied -to the frequency control systern 46 of oscillator 16 causes this oscillator to sweep through i-ts frequency range.
~ he hunting action continues until the OU-tpllt frequency fO
of oscillator 16 is phase~ocked on the selected harmonic in the first harmonic spectrum generated by pulse generator 20~ Once a positive phaselock has occurred, hunting oscillator 48 is inhibited by the presence of the signal on line 44. While oscillator 16 is phase~ocked to the selected harmonic of f1, frequency selective ga-te 38 will produce an output signal on line 36 thereby enabling p~lse 366~9 mixer 24. If the phase-lock is lost or a different output frequency is seiected, the gate signal on line 36 temporarily disappears thereby inhibiting mixer 24 and allowing the hunting action to resume until a phase-lock is reacquired on the same harmonic of fl in the first case or on a new harmonic of fl in the latter case.
The rate at which hunting oscillator 48 sweeps the frequency of oscillator 16 across its frequency range must be controlled to allow sufficient time for a positive phase-lock to occur. The precise sweep rate depends on the overall control loop ~ ' characteristics of the frequency synthesis system since a finite capture time is required due primarily to the time constant of frequency selective gate 38 and filter 40. The circuit criteria required to design a stable phase-lock loop are well known to those skilled in the art.
In the system described thus far the conditions required for a positive phase-loc~ repeat for each , harmonic of the secondary reference frequency fl present in the first harmonic spectrum generated by pulse generator 18. The precise method employed to ensure that a phase-lock on the desired harmonic of fl will occur is now described.
Two signals, one derived in part from amplifier 54 and one from a second pulse generator 56 (to be des-cribed), are directed to gate 38 via line 52. Amplifier 54 is coupled to oscillator 16 via ]ines 34 and 58. The signals from amplifier 54 and a pulse generator 56 are coupled to pulse mixer 60 via ]ines 62 and 64 respectively.

An auxiliary controllable oscillator 66 is coupled to pulse generator 56 via line 68. The output signal from oscillator 66 has a frequency f2 which is controllable over a limited frequency range by means to be described. Like pulse generator 20, pulse generator 56 produces a pulse train signal having a high harmonic content. The harmonics in this pulse train form a second harmonic spectrum.

The output signal from pulse mixer 60 is a beat signal, between f0 and the nearest harmonic to f0 contained in the second harmonic spectrum on line 64.
The beat signal has a variable frequency fb and when the frequency fb lies within the passband of frequency selective gate 38, a control signal appears on line 36 enabling pulse mixer 24 as described.

- The frequency of the signal generated by oscillator 66 is controlled by a programming system described below. When f0 is coincident with the desired harmonic of fl the beat frequency fb from pulse mixer , 20 60 is a frequency f4 (f4 to be defined) which lies within the frequency passband of gate 38. When this condition ,' occurs pulse mixer 24 is enabled by the signal on line 36 generated by gate 38. ~i, Oscillator 66 is programmed by first mixing signals coupled from oscillator 94 and from oscillator 66 on lines 18, 70 and 72 respectively, in a conventional mixer 74. The output signal from mixer 74 appears on line 76 and has a frequency -(fl-f2)- It will be apparent to those skilled in the art that either difference frequency may be used in the present frequency synthesis system. Selection may be accomplished by suitably filtering ',.

1~3t~679 the output signal from mixer 74. In the discussion to follow the difference frequency (fl-f2) will be assumed.

The signal having a frequency (fl-f2) on line 76 is coupled to phase discriminator 78.
A crystal controlled programming oscillator 80 generates a programming frequency f3 which is directed via line 82 to a programmable frequency divider 84. Divider 84 divides the input frequency f3 by a factor n so that the signal on line 86 has a frequency f3 Phase dis-n criminator 78 compares the signals ~fl-f2) and f3 and ~ produces a slowly varying DC output signal on line 88.
This signal is proportional to the phase difference between (fl-f2)and f3. The signal on line 88 is directed into a second low pass filter 90 having an out-put on line 92 which provides a signal for a frequency control system 93 which is part of oscillator 6,6 . The control loop comprising elements 66, 74, 78, 80, 84 and 90 is designed to synchronize o~scillator 66 to a condition in which (fl-f2) = 3-To ensure a phase-lock condition for the various possible values of n, discriminator 78 may be a combination frequency and phase discriminator. In this case the frequency discriminator portion of discriminator 78 brings (fl-f2' to a value close to f3 thereby ensuring that both frequencies are within the lock-in range of the phase - discriminator portion of dlscriminator 78.

3f~679 To ensure an exclusive phase-lock on the nth harmonic of fl various combinations of f3 and division ratios can be used. In a simple configuration the programming frequency f3 is set equal to the frequency f4, and divider 84 is programmed for a division ratio n.
Thus, the condition required for synchronization of oscillator 66 is fl ~ f2 = f4. When this condition is met ~he beat n frequency fb is f4 and gate 38 enables pulse mixer 24.
An important consideration in this system is -to ensure that fO cannot be phase-locked on another harmonic of fl`within the control range of oscillator 16. In relation to the adjacent harmonics of fl, namely (n - l).fl it can be shown that fb will differ from f4 by by a value n4' Consequently, the passband of frequency selective gate 38 must be less than _~fa, for the largest value of n used in order to ensure that the system will not lock onto an adjacent harmonic of fl. ~ `

If the passband of gate 38 is designated as b.f4, this represents the frequency range within which fb must be located in order~ for gate 38 to enable pulse mixer 24 Assuming that this passband is located symetrically about f4 extending from a frequency f4-_ .f4 to a frequency , f4 + b .f4, the condition f4 ~ _ .f4 must be satisfied to ensure that a phase-lock cannot occur on adjacent harmonics of fl. In a practical case, taking into account ,~1 asy~étry of the passband and a tolerance factor in the frequencies involved the condition may be stated as i f4 ~ bf4, where the harmonic numher n relates to the highest harmonic of fl on which a phase-lock is required.

. : ~ . .. .

~03667~ 1 For this particular harmonic the ratio 4 has its lowest value. For example, if n equals 150 than -must be less than or equal to 1lO .

Another lock-in condition can occur for a substantially different value of fO. If the harmonic number for this alternate lock-in frequency is indicated by m for fl and by (m+p) for f2, then the condition for such a secondary locking point on an image frequency 4 , 1 f4 (mf+ P)f2. Considering also the relationsKip fl ~ f2 = 41eads to the result that, m = 1 - 1 - 1 or for p = 1, m = 1 - 1 - 1. This equat~on n p f4 p n n f4 n indicates that a secondary lock-in frequency will be more remote for higher values of fl which in turn implies f4 lower values of f4. However, decreasing f4 results in a narrower passband for gate 38 which in turn results in a relatively longer lock-in time and consequently requires a reduced hunting rate. For most practical applications a value of 1 lying in the range between ~ and 5 will be satisfactory. This provides protection -~
against a secondary lock-in f~r a frequency range of more than 3:1 which represents a practical goal.

The remaining elements shown in Fig. l,are employed to generate the secondary reference signal frequency fl. As described above this signal contains the required interpolation frequency shift. The secondary reference signal frequency is generated by a controllable oscillator 94. Signals having a frequency fl, generated by oscillator 12, and a frequency fl, generated by oscillator 94, are directed via lines 96 and 97 respectively to a conventional mixer 100. The difference frequency fl - fl generated by mixer 100 is directed to phase discri-minator 102 via line 104. Phase discriminator 102 compares ....

~36679 the signal on line 104 wit~l a signal on line 106 from aprogrammable frequency dividcr 108. The programmable frequency divider is programmed to divide by the factor n. The interpolation frequency fi is introduced on line 110. Phase discriminator 102 produces an output signal on line 112. The signal on line 112 has an amplitude and polarity related to the phase difference ~, *
between the signals on lines 104 and 106, fl - fl and fi respectlvely. The signal on line 112 is fed to a low pass filter 114 which suppresses unwanted harmonics and provides a control signal on line 116 to operate a frequency control system 95 in oscillator 94.

Thus, the frequency of oscillator 94 is brought to a phase-lock condition whereby fl - fl =

i or nf* = nf + f . The harmonic n of frequency n 1 1 fl on which fO is phase-locked is determined by frequency dividers 84 and 108 both of which are programmed to divide by the same factor. The interlock between each divider is indicated in Fig. 1 by switches 118 and 120 and dotted line 122. Thus, oscillator 16 is phase-locked on a frequency n~fl which is a combination of the selected harmonic of n fl plus the required interpolation frequency fi-- The functions of programmed frequency dividers 84 and 108 can be shared in a single frequency divider (not shown). I'o accomplish this, the input and output circuits of the single divider are periodically switched thereby enabling the divider to be shared. While the I input to the sihgle divi~Jer is connected to line 82, its output is connected to line 86. This provides a required , - :
:

- ~36~q9 input for phase discriminator 78. When the input of the single divider is connected to line 110 the output of the divider is connected to line 106 which is coupled _~ to phase discriminator 102. Using a single switched ~
frequency divider requires that phase discriminators 78 and 102 be of the sample-and-hold type.

The periodic switching rate is chosen to ensure a sufficient number of cycles of the divider out-put signal appear for each input-output connection. This is a necessary requirement for the proper operation of each phase discriminator when it is connected to the divider. -After each switch-over operation the single frequency divider is reset to its start condition.

The signal on line 18 may be generated in another manner which avoids the need for phase discriminator 102.
In this case a signal having a frequency fl is mixed in a conventional mixer with a signal having a frequency i.
The mixer output signal is then passed through a filter which rejects all of the frequencies except the upper image frequency fl + fi. This signal is then directed to line 18.
n In the system described above, in relation to Fig. 1, the interpolation frequency fi has a value which varies from relatively low values to values approaching fl. In practical terms this represents a relatively wide frequency range and as such can`lead to complications in a design of phase discriminator 102.
For this reason it is preferable to employ an inter-polation frequency fi + fl on line 110 instead of fi.

This being the case the only change required is program-ming programmable frequency dividers 108 and 84 to divide by a factor (n-l) rather than n. Thus, when fO
is phase-locked on the nth harmonic or fl, it is also ~3~6~9 phase-locked to the (n-l)th harmonic of fl. There-fore (n-l).fl = nfl + fi and fO = nfl + fi-is exactly the result previously expres~ed.

A number of alternate methods exist for generating the required interpolation frequencies which `;i being familiar to those skilled in the art are not described herein. In frequency synthesis systems employing pulse synchronized oscillators, it is advantageous to span a frequency range of 2 deca~es in addition to a frequency shift equal to one step of the largest step interval using a single phase-locked oscillator. Consequently, each interpolation oscillator must cover a range of 100 to 200 times its fundamental frequency or 99 to 199 times its fundamental frequency if the frequency shift produced by a further interpolation -~
system is included. While the interpolation oscillator concerned covers a range of approximately 100:1 for interpolation purposes the relating programming~section will still be in decade steps. Consequently, the overall frequency selection will appear as a multi-digit decimal number.

Reference is now made to Fig. 2 which shows at 130, in block diagram form, a multi-decade frequency synthesizer~ The frequency synthesizer is based on successive repetitions of the system shown in Fig. 1.
A signal having a frequency fl + fi is employed as an interpolation frequency and programmable dividers 108 and 84 set to divide by a factor of (n-l) rather than n.
Since each harmonic selection system A, B, and C is identical to the system shown in Fig. 1, the internal elements comprising each system are not shown and -~ . -~`f 1~3~679 identical external elements are identified by a letter subscripted form o a previously used reference numeral. In addition, it will be appreciated by those _ skilled in the art that each harmonic selection system and its associated elements, although identical in form and function may differ in the respect that each harmonic selection system can have differe~t input and output frequency since each con-tributes a specific interpolation shift. In this case filters and other frequency sensitive elements must be appropriately adjusted to operate over the required range of frequencies.

The output signal fO of the multi-decade synthesizer shown in Fig. 2 appears on line 14a. fO
is phase-locked to the (n-l~th harmonic of seconaary reference frequency fl which in turn is phase-locked on the nth harmonic of the primary reference frequency - fl (generated by oscillator 12) plus the interpolation frequency fi. Harmonic number n is determined by divider 84a which is programmed to divide the gàte enable frequency f4 on line 82a by a factor (n-l).
Harmonic selection is accomplished, as previously described, by comparing the output signal fla ~
from mixer lOOa with nll times the interpolation frequency (fl ~ fi) which is produced by frequency divider 108a. The control signal on line 116a phase-locks oscillator 94a to a frequency which satisfies the condition, fla ~ fl = fl fi. Consequently, n- - 1 (n-l)fla = nfl + fi-The interpolation frequency fl + fi is generated in a manner now described. Frequency f --~ is coupled via lines 132; 134, and line ,c to harmonic selection system C.
~armonic selection system C is programmed for an i~`~erpolation step (100 + p), where p (the harmonic number for the smallest interpolation step in the system) is an integer between 0 and 99, by means of divider 84c and gate enable frequency f3.
The gate enable frequency f3 is generated by oscillator 80 and is set-equal to the frequency f4 (previously defined). The signal from oscillator 80 is coupled to divider 84c via lines 82c, 138 and 140 Consequently, the output of oscillator 16c, foc is phase-locked to a frequency ~100 + p)-f The output signal from oscillator 16c is directed via line 14c to a fixed frequency divlder 144 which divides the output signal frequency by 100. The output of divider 144 is further divided in programmab]e ' divider 108b by a factor of (100 + m - 1), where m is the harmonic number of the next highest interpolation step and has a value between 1 and 99. Thus, the output signal on line 106b has a frequency (100 P) 1 , which lOO.(lOO+m-l) represents the shift in frequency of oscillator 94b.
This frequency is defined as flb In relation to primary reference frequency fl, the frequency f*lb is phase-locked, in the manner previously described, by mlxer lOOb, phase 102b and filter 114b to a condition where flb ~ fl =
(100 + p).fl lOO.(lOO+m-l) 1~3~6~9 For the second interpolation step m, harmonic selection system B is programmed by divider 84b , which divides f4 by the factor (lOO~m-l). As a result, oscillator 16b is phase-locked to a frequency (100~ .flb.
Upon simplification the frequency of oscillator 16b is equal to the frequency (lOO+m+ p ).fl. Frequency dividers 108b and 84b must always divide by the same factor, consequently they must be simultaneously programmed.
This is indicated by switches 118b and 120b and dotted line 122b in Fig. 2.

The output signal from oscillator 16b appears on line 14b and is coupled to a fixed frequency divlder 146 which divides by a factor of 100 resulting in a signal on line llOa haviny a frequency fl(l + m + p l. The signal on line llOa represents the interpolation frequency fl + f. described above. Thus, f. is equal to fl.(m p _).
100 + 10000 As previously discussed fO is produced y harmonic selection system A and is equal to nfl + fi.

Therefore fO equals (n + m ~ _ )fl-Frequency dividers llOa and 84a must be simultaneously programmed since both must divide by the same factor (n-l).
This is shown in Fig. 2 by switches 118a and 120a and line 122a. Switch 123 and line 125 are used to indicate that the output frequency produced by oscillator 16a can be varied. However, when this is done switches 118a and 120a must also be activated.

In the above system oscillators 94a and 94b operate over a relatively limited frequency range, the location of which is clearly defined in relation to the .
, 1~b36679 frequency fl,which results in a sing~le unambiguous phase-lock system. The output of oscillators 16b and 16c can be varied in frequency over a frequency range with a ratio in the order of 2 to 1. This can be accomplished by a hunting oscillator referred to with reference to Fig.
1.
Oscillators 16b and 16c cover an identical frequency range which is quite similar to that covered by oscillator 16a. -In some applications the frequencies employed must be relatively high due to circuit design considerations. If this is the case, the primary reference frequency supplied to harmonic selection systems B and C can be reduced by a factor of 10. This is accomplished by the fixed divider 136 which divides the output frequency of oscillator 12 by factor of 10.
Consequently, the interpolation system operates at a frequency lower by an order of magnitude than in the system described above. In accordance with this arrange-ment the gate frequency f4 supplied by oscillator 80 must be reduced by a factor of 10 by fixed divider 142.
Because the interpolation system is now operating at ten times reduced frequency, divider 146 must be changed to divide by a factor of 10 rather than 100 This results in signals being directed to programmable divider 108a which are identical to those in the original system. Employing a lower frequency in the interpolation system has the advantage of allowing a more economical design.
An even more practical arrangement in a multi-decade frequency synthesizer is to employ continuously ~:, ., . . ; .

f9 operating interpolation dividers for each harmonic selection system and time share one common divider for the programming function of each system. This is done by periodically connecting, in a predetermined scanning sequence, a common programmable frequency divider to each harmonic selection system. The time sharing concept is based on the realization that while the function of the interpolation frequency dividers is basically a continuous one the programming dividers are only required on a continuous basis until a phase-lock on the selected harmonic has occurred. Subsequent to a phase-lock, the programming dividers have no further function except to ensure that in case any change takes place it will be corrected or if the programming.is altered by the selection of a new output frequency that this change is actually performed. These operations can be performed adequately be a periodic sampling process instead of a continuous one. In addition, a time sharing scheme would preferably incorporate an arrangement which ensures that~when the programming of a harmonic selection system is changed, the programming divider immediately switches to that particular system until the change has been carried out after which repetitive scanning action is resumed.
Accordlngly, another embodiment of the present invention, shown in block diagram form in ~ig.

3 at reference numeral 270, involves the modification of a multi-decade frequency synthesis system shown in J Fig. 2 to include a time sharing arrangement for the programming frequency dividers. In practice both the time sharing and scanning functions would be performed ' ' : : ' '.: ,:

~LQ;3 ~6r~'9 electronically, however, for reasons of simplicity mechanical switches are shown.
Programming frequency dividers 84a, 84b and 84c (see Fig. 2) are replaced by a single common programming frequency divider 152. As was the case with the individual programming frequency dividerS,programming frequency divider 152 receives a signal from oscillator 80 via line 138.A scanning circuit 154 operates scanning switches 156, 158, 160 and 162 causing e-ach switch to move sequentially in synchronism so that the signal lines are repeatedly switched from connections relating to each of the harmonic selection systems A, B, and C.
In addition, programming iines 164 and 166 associated with divider 152 are successively interconnected~to programmers 168, 170 and 172 by switches 158 and 160 via lines 174 and 176, 178 and 180and 182 and 184 respectively.
The programmers change the dividing ratio of programming frequency divider 1~2 when it is switched to ea,ch harmonic selection system. At the same time the output of frequency divider 272 on line 186 is coupled by switch 156 to lines 86a, 86b and 86c.
Scanning circuit 154 is also coupled via line 189 to an element 190. Element 190 generates an enabling signal on line 192. This enabling signal is sequentially switched by switch 162 to lines 194, 196 and 198 which direct the enabling signal to the frequency selective gates 38a, 38b and 38c (see Fig. 1) in harmonic selection systems A, B, and C, respectively.

-~L~366~9 When the enabling signal is absent at the input of any particular gate 38a, 38b or 38c, the gate will generate a gate enable signal on lines 36a,36b or 36e (refer to Fig. 1). However, when an enabling signal is present, the gates are returned to their normal mode and will produce a gate enable signal on lines 36a, 36b or 36c ~nly when the input signal on lines 52a, 52b or 52e eorresponds to the required gate enable frequency f4.
If this is not the ease the gate will break the phase-lock and hunting will resume until a phase-lock on the proper harmonie frequency for the harmonie seleetion system concerned occurs. The time sharing frequency synthesizer provides circuitry (not shown) to interrupt the operation of the scanning system upon the initiation of hunting in any harmonic selection system. The scanning system remains interrupted until a phase-lock occurs in the harmonic selection system, at which time the scanning operation is resumed.

As previously described, the scanning system is arranged so that the scanning circuitry makes the neeessary connections to the particular harmonic selection system in which the programming has been ehanged. Hunting aetion in ~hat particular harmonic selection system will eontinue until a phase-lock on the required harmonic related to the newly programmed output frequency occurs at which time normal scanning is resumed.

It will be obvious to those skilled in the art that the time sharing scheme described can be extended to include 'che auxiliary controlled oscillator and related mixer and frequency discriminator circuits and may also include part of the pulse mixer circuit. In this system ~366~9 the input for the related interpolation frequency dividers and the output of the respective auxiliary frequency oscillators tG their respective pu]se generators are switched over by the scanning system.

In the above description it has been assumed that the frequency f4 is the same for all harmonic selection systems, however this is not always the case. The programming system may include a number of different programming frequencies which are switched between the various harmonic selection systems as required.

The dotted line 200 between the scanning circuit 154 and switches 156, 158, 160 and 162 indicates that all of these switches are switched in synchronism.
In addition, although not shown in Fig. 3, interpolation dividers 108a and 108b must be interlocked with pro-grammers 168 and 170 respectively in order to correctly program the related dividers when a new frequeney selection is made.

Reference is next màde to Fig. 4 which shows a multi-decade frequency synthesizer, indicated generally by numeral 210. This system is somewhat simpler than that shown in Fig. 2 inasmuch as one less programmed frequency divider is employed. Harmonic selection systems B and C are coupled to a common primary reference frequency having a frequency fl ;or fl as previously described)- As before, this frequency represents the basic step frequency in the system. Consequently, controlled osci lator 16c is phase-locked on the (lOO+p~th harmonic of the frequency fl while controlled oscillator 16b is phase-locked to the (lOO+m-l)th harmonic of the 1~366q9 frequency fl.

The output of oscillator 16c is coupled via line 14c to fixed frequency divider 144. Frequency divider 144 generates an output signal having a frequency (1 + p )fl. This signal is fed via line 212 to phase discriminator 214. The auxiliary controlled oscillator 216 tracks the output frequency of oscillator 16b but is offset to a slightly higher frequency. The output signalsfrom oscillator 16b and from oscillator 216 are fed via lines 14b and 218 respectively to mixer 220.
The difference frequency produced by mixer 220 is fed via line 222 to phase discriminator 214 where it is compared with the signal an line 212. The phase discriminator output signal on line 224 is fed to a low pass filter 226. The filter output signal on line 228 provides a control signal for a frequency control system 225 in oscillator 216 phase-locking oscillator 216 to a frequency tlOO t- m + p )fl.

The output from oscillator 216 is fed via line 230 to fixed frequency divider llOa where it is divided by a factor of 100 (or 10 as previously described).
Consequently, the output frequency of divider 146, appearing on line llOa has a frequency (1 + m + p )f , 100 100 1 which is the required interpolation frequency for harmonic selection system A. The remainder of the system is identical to that described with reference to~Fig. 2.

The output frequency fO on line 14a equals (n + m + p )fl.
00 1~000 The frequency of oscillator 216 is maintained at a value slightly higher than the frequency of oscillator 16b. This creates the possibility of oscillator 216 phase-locking on a lower image frequency of oscillator .

-6~;79 16b which differs only slightly in value from the desired upper image frequency. To avoid the compli-cations involved in closely tracking oscillators 16b and 216, phase discriminator 214 may be an image-selective phase discriminator. This type of phase discriminator is well known to those skilled in the art and permits a phase-lock on either the upper or lower image frequency as compared with the input reference frequency to the mixer.

A further modification (not shown) directs a signal derived from the control signal on line 46b to oscillator 216.
This signal is used for course tuning oscillator 216.
Thereafter, a hunting system (not shown) associated with oscillator 216 would provide hunting over a limited frequency range to ensure an ultimate phase-lock.

Reference is now made to Fig. 5 which shows at reference numeral 240 a multi-decade frequency synthesizer which combines the frequency synthesis system shown in Fig. 1 with interpolation means using a gated divider system as outlined in the introductory remarks concerning multi-decade frequency synthesizers.
As previously described the main disadvantages associated with the gated divider frequency synthesizer are the requirements for high speed counters and signal gates when hiah output signal frequencies are involved and reduced phase stability in the output signal frequency of the system. The latter disadvantage is particularly severe when high multiplication factors are required.
The use of a gated divider system in the interpolation portion of the frequency synthesis system shown in Fig. 1 can substantially reduce these disadvantages.

.

~.~3~i6~9 In Fig. 5 the output signal from controllable oscillator 242 is directed via line ~74 to four serially - connected gated decade frequency dividers. Frequency dividers 246 and 248 divide by factor p which represents the smallest interpolation step and frequency dividers 250 and 252 divide by a factor (100 + m) which represents the largest interpolation step. The frequency dividers are interconnected via lines 254, 256 and 258 respectively.
Each divider is provided with gating circuitry (not shown) which allows the frequency divider to absorb a fixed number of input pulses before being bypassed by the gating cir-cuitry. At the end of one complete cycle a trigger pulse generated by the appearance of a signal on line 262 is directed to each of the frequency dividers. The trigger pulse resets the entire frequency divider chain. The out-put of divider 252 feeds a phase discriminator 260 via line 262.
The primary reference frequency fl is~divided by a factor of lO,OOO by fixed frequency dividers 264 and 266. Divider 264 receives an i~nput signal of frequency fl via line 268 and is coupled to divider 266 via line 270.
This provides a signal on line 272 having a frequency equal to fl/10,000 which represents the smallest interpolation step.
The output from divider 266 feeds phase discriminator 260 via line 272 and the output signal from phase discriminator 260 on line 274 is directed to filter 276.
The output signal from filter 276 is coupled to oscillator 242 via line 278. The signal on line 278 operates the frequency control system 279 in oscillator 242 to establish the output frequency of this oscillator at a . . . ~ , .

~)36~9 frequency equal to fl.(l + lOOm ~ p ). As described above this frequency represents the required interpo-lation frequency. The remainder of the system operates identically to the system shown in Fig. 2.
Phase modulation of the output signal fO has a maximum value which is equal to the phase modulation which occurs in oscillator 242. This is 100 times less than a comparable gated divider frequency synthesizer with an output frequency comprising the full six decimal places.

The low frequency used in the interpolation system will result in a relatively long selection time when a new output frequency is selected. However, the selection time can be reduced by altering divider 266 to divide by 10 rather than 100. In this case, controlled oscillator 242 will vary over a frequency range of lO.f to 20.fl. Hence oscillator 242 must be followed by a fixed frequency divider which divides by a fact~or 10 (not shown) so that the signal on line llOa will have the proper frequency. Using this arrange~ent, the maximum frequency of oscillator 242 is still relatively low while the phase modulation in the output signal on line 14a is reduced by a factor of 1000 over a comparable full gated divider - frequency synthesizer.

It will be obvious to those skilled in the art that the aforementioned interpolation system represents only one of the possible systems that can be employed. Due to the flexibility of the basic frequency synthesis system provided by the present invention, a wide choice of division ratios and oscillator frequencies are available in order to maximize both the performance and the economy of the system.

366~9 The problem of phase modulation i~ the output signal frequency fO associated with the gated divider frequency synthesizer shown in Fig. 5 arises from the fact that the output signal from the gated frequency divider chain while having a relatively low frequency must have a relatively wide lock-in range for satisfactory operation. This requires a comparatively long time con-stant in the interpolation oscillator control loop which in turn results in a reduction in the output signal phase stability. The operation of the gated divider frequency synthesizer may be improved both in terms of increased phase stability and reduced lock-in time by the circuitry shown in Fig. 6 at reference numeral 300.
Because the additional circuitry will be described in relation to the gated divider frequency synthesizer shown in Fig. 5 parts of Fig. 5 are reproduced in Fig.
6 for convenience.
Referring now to Fig. 6, the frequency divider 252 is coupled to a pulse shaping circuit 302 and a fixed frequency discriminator 304 via lines 262, `~306 and 262, 308 respectively, Frequency discriminator 304 is tuned to a centre frequency equal to the required output frequency of the gated divider chain when oscillator 242 is in a phase-lock condition. In this case the centre ,frequency of the frequency discriminator is equal to fl/10,000. Pulse shaper 302 transforms the signal on line 262 to a harmonic rich pulse train having the same frequency as the signal on line 262. The pulse train from pulse shaper 302 is directed via line 310 to a pulse mixer 312.

, .

~66~

The primary reference frequency fl is divided by a factor of 1000 by fixed frequency dividers 264 and 314 and is d~rected to pulse mixer 312 via line 316.

. In pulse mixer 312 the frequency spectra contained in the pulse train on line 310 is mixed with the signal on line 316 which has a 10 times higher fundamental frequency than the signal on line 316. The resulting difference frequency signals are directed via lines~318 and 274 to filter 276.

Frequency discriminator 304 generates a dual polarity DC output signal on line 320 which is combined with the mixer output sign-al on line 318 and directed along line 274 to filter 276. The portion of the control signal on line 278 which is derived from the frequency discriminator 304.causes the frequency of oscillator 242 to vary so that the output frequency of frequency divider 252 approaches the centre frequency of ~he frequency discriminator 304. As this frequency is approached the frequency of the signal generated by ~ixer 312 drops to a value low enough to allow the signal to pass through filter 276 to the frequency control circuitry 279 in oscillator 242. The portion of the control signal on line 278 produced by mixer 312 ultimately causes oscillator 242 to phase-lock on the required inter-polation frequency, The reduction in lock-in time is a result of the characteristics of the feed back control loop ~, including frequency discriminator 304. The use of a frequency discriminator in the control loop permits faster frequency control and hence a reduced lock-in time.

66~9 Increased phase stability i,n the output signal frequency fO is due to the use of pulse mixer 312 in the control loop. Because the control signal generated by pulse mixer 312 is derived from the 10th harmonic of the gated divider output signal frequency erratic phase modulation in the output of oscillator 242 is reduced by a substantial amount approaching a factor of 10. Furthermore, because the critial phase shift for loop instability is 180 for frequency discriminator feedback and only 90 for phase modulation feedback the use of a frequency dis-criminator in the feedback control loop allows the cancellation of higher frequency phase modulated signal components than would be possible by using a phase discriminator in the feedback loop.
The phase stability of the gated divider frequency synthesizer may be further improved by increasing the phase stability of the interpolation frequency oscillator. Referring to reference numeral 330 in Fig. 7 (which includes portion of Fig. 5 for clarity) circuitry, in block-schematic diagram form, for improving the phase stability of interpolation oscillator ~4~ is shown.
To increase the phase stability of inter-polation oscillator 242 an additional negative feedback control loop employing a frequency discriminator 332 is employed. The frequency discriminator input signal may be derived from oscillator 242. However, it is preferable that the frequency discriminator input signal have a higher frequency than the frequency of the output signal from the gated frequency divider chain on line 262 (see Fig. 5).

1~3~;679 In Fig. 7 the input signal for frequency discriminator 332 is derived from the output signal of fixed frequency divider 108a via line 332. The ~utput of the frequeney discriminator on line 336 is direeted via a eapaeitor 338, lines 340 and 342, and a low pass filter`344 (to be described) to oscillator 242.
The signal polarity eoupled baek to oseillator 242 is seleeted to provide negative feedbaek. Frequeney diseriminator 332 is designed to have a linear transfer eharaeteristie between its input and output over a frequeney range whieh ineludes the frequeney range of the output signal from frequeney divider 108a.

Referring again to Fig. 5, if we assume that the faetor (100 + m + p) is eonsiderably greater than the faetor ~n-l) the output signal frequeney on lines 334 and 106a will be eonsiderably greater than the frequeney of the signal on line 262. As a result, the negative feedbaek provided by frequency discriminator 33~ is operational at considerably higher frequeneies than the feedback generated by a phase discriminator 260. The effect is a substantial improvement in the reduction of phase modulating disturbances at the higher frequeneies.

The additional feedback circuitry shown in , Fig. 7 results in a reduction in the speed of the frequency control loop associated with interpolation oscillator 242. The speed of the frequency control loop is determined by the value of capacitor 338. Capacitor 338 also establishes a lower frequency limit for the feedback from frequency discriminator 322. Consequently, the value of capacitor 338 must be selected to compromise between increased phase stability for oscillator 242 and reduced control loop response and hence reduced locking time. The additional circuitry shown in Fig. 7 can ~ result in a significant reduction in phase modulation in the output signal frequency fO, particularly in relation to phase modulation distrubances at a frequency beyond the cut-off frequency of filter 276.
Filter 344 is a low pass filter having a high frequency~cut-off considerably higher than that of filter 276;. The purpose of filter 340 is to surpress the spurious frequency components in the output signal from frequency divider 108a.
In order to better illustrate the practical potential of the frequency synthesis system according to the present invention, the following numerical example based on the system illustrated in Fig. 4 is provided.
The example is then applied to the multi-decade fre-quency synthesizer shown in Fig. 5.
In this example the frequency synthesizer is to have an output frequency range from lO MHz to 150 MHz.
with frequency selection at intervals of 100 Hz. The primary reference frequency fl is 1 MHz. This frequency represents the basic step frequency of the frequency synthesizer in this example. The range 10 MHz to 150 MHz can be conveniently divided into 4 sub-ranges of 10 MHz to 20 MHz, 20 MHz to 40 MHz, 40 MHz to 80 MHz and 80 MHz to 150 MHz. Each of these sub-ranges has a frequency range of 2 to 1 with the exception of the highest range which is less than 2 to 1. The selection of the sub-ranges can be effected by a 1 MHz step programming divider which involves frequency dividers 108a and 84a.

,.

~.
- ' : ' ~ '-:' , - .: : .

66~9 - The harmonic number n will have values between 11 and 151. This corresponds to (n-l) having values r~ from 10 to 150. Consequently, oscillator 16a covers the range of 10 to 150 MHz in basic steps of 1 MHz.
Programming for dividers 84a and 108a is provided by means of an external decade switch which covers the range of 10 to 150 although internally n equals 11 to 151.
~ The reference frequency used to generate each basic step is supplied by oscillator 12. The output frequency fO is phase-locked on the required harmonic of a secondary primary reference frequency os-cillator-94a which equals the frequency fl shifted by the required interpolation frequency divided by a factor of (n-l). For interpolation, the 1 MHz signal generated by oscillator 12 is divided by frequency divider 136 - by a factor of 10 resulting in a 100 KHz signal on line 134. This signal is used as the input frequency for harmonic selection systems B and C, each of which covers two decades in frequency. Harmonic selection ~` system- C is ultimately responsible for producing the 100 Hz steps and consequently covers the 100th to 200th harmonics of 100 KHZ. Thus, oscillator 16c covers a range of 10 to 20 MHz in 100 KHZ steps.
The external numerical indicator which programs divider 84c displays two decimal places each varying from 0 to 9. Internally the programming system associated with harmonic selection system C is programmed for division ratios of 100 to 199. The out-put of oscillator 16c is coupled to frequency divider 144.

1~)36ti79 . . .
Frequency divider 144 divides by a factor of 100 thereby providing an output signal on line 212 varying in frequency from 100 KHz to 200 KHz in 1 KHz steps. Pro-grammable frequency divider 84b in association with harmonic selection system B covers division ratios of 99 to 199. As a result, the output frequency of oscillator 16b covers a range of 9.9 MHz to 19.9 MHz in 100 KHz steps. The external programmer for fre-quency divider 84b will indicate two decades of frequency using the numerals 0 to 9.

Oscillator 216 provides a signal whose fre-quency is equal to the sum of the frequencies produced by oscillator 16b and frequency divider 144, covering a frequency range of 10 to 20 MHz in 1000 steps. Briefly reiterating, this is accomplished by mixing signals from oscillators 16b and 216 in mixer 220 and feeding the difference frequency on line 222 to a phase dis-criminator 214. The output of the phase discriminator is fed to filter 226. The filter output signal is used to control the frequency of oscillator 216 to a phase-lock condition in which the output signal frequency from mixer 220 is equal to the output signal frequency from divider 144. If phase discriminator 214 is an image-selective phase discriminator, a phase-lock will occur only when the frequency of oscillator 216 is higher than the frequency of oscillator 16b.

The output signal of oscillator 216 is coupled to frequency divider 146 which divides by a factor of - 10 rather than 100 since dividers 136 and 142 have already divided by a factor of 10. Therefore, the output signal from frequency divider 146 covers a frequency range of : : , - ~ , . ~ , :

~ 36~9 1 to 2 ~\1hz in 100 Mz stepsO lhe output of divider 146 is directed to divider 108a which is programmed to divide by the same factor as frequency di~ider 84aO
Consequently the output signal from frequency divider 108a is a frequency in the range 6.7114 KHz to 222.222 ~Hz. ~or proper coincidence between frequency dividers 108a and 84a this results in a variation of the output frequency fO over a range of 1 MHz in 100 Hz steps for each basic step of 1 MvTHZ in the frequency range o~ 10 to 150 lilHzo If the desired output frequency is ~1.6542 MHz, and frequency dividers 10~a and 84a are programmed for a division factor of 30, the output of divider 146 will be a -~
signal having a frequency of 1.6542 MHz. Consequen-tly, the output from frequency divider 108a is a signal having a frequency 55.14 kHz and the output from oscilla-tor 94a is phase-locked to a signal having a frequency of 1005514 MHz.
dscillator 16a is phase-locked to the 30th harrnonic of this frequency or 31O7542 MHzo In order to obtain a frequency of 1O65A2 MHz from frequency divider 146, the output signal of oscillator 216 must be a signal having a frequency of 16.542 MHzo Therefore, -the outpu-t signal from oscillator 16c must havt a frequency of 1402 M~Iz, and tlle ou-tput frorn frequency divider 144 must be a signal having a frequency of 142 KHzo ~rhe output from oscillator 16b is then 16.4 MHz o 'rhe sum of the frequencies of the signals frorn frequency divider 144 and oscillator 16b equals the OlltpUt signal frequer~cy from oscillator 216, which, as sta-ted above9 is 16.532 MHz. ~he external decade swi-tch programming . .

1~)36~79 frequency divider 84c is set at 42 and for frequency divider 84b it is set at 64. Internally the frequency dividers are programmed for division ratios 142 and 164 respectively. Frequency dividers 108a and 84a are both programmed internally at 30 while the external programmer reads 31.
Applying the above example to the frequer.cy synthesizer shown in Fig. 5, oscillator 242 must oscillate at a frequency of 1.6542 MHz in order to provide the required signal frequency for interpolation frequency divider 108a. The basic step frequency fl generated by oscillator 12 is 1 MHz an~ after division by 10,000 appears on line 272 as 100 l~z. Serially connected gated frequency dividers 246, 248, 250 and 252 must therefore divide by a factor of 16,542 so that the signal on line 262 has a frequency equal to 100 Hz. This condition is assured by the phase-lock loop associated with oscillator 242. For this condition m = 65 and p = 42 J
as above.

In electronic systems, including radio and tele-vision receivers and the like there often occurs a need for signals having a frequency which differ from a selected harmonic of a reference frequency by a fixed offset frequency. The frequency synthesis element shown in Fig. 1 may be employed to generate such signals. The frequency f3 generated by oscillator 80 (see Fig. 1) may be used as the fixed offset frequency. The output signal frequency generated by oscillator 16 is phase-locked on a harmonic of the auxiliary reference frequency f2 con-tained in the second harmonic spectrum rather than being - 40 ~

.

1~ 9 phase-locked on a harmonic of the primary reference frequency fl contained in the first harmonic spectrum.
The gate 38 is coupled to a signal having a frequency equal to the beat frequency between the frequency fO
generated by oscillator 16 and the harmonics contained in the first harmonic spectrum.

Referring now directly to Fig. 1, the afore-mentioned requirements may be met by making the following alterations to the system in Fig. 1. The output signal frequency generated by oscillator 94 is set equal to a frequency fl. Alternatively, the output signal from oscillator 12 could be coupled directly to line 18. The frequency f3 generated by a.scillator 80 is set equal to the desired offset frequency. Those portions of Fig. 1 used to inject the interpolation frequency fi are made in-operative. Line 26 from pulse generator 20 is connected to pulse mixer 60 instead of to pulse mixer 24 and line 64 from pulse generator 56 is connected to pulse mixer 24 instead of to pulse mixer 60. The programmable frequency divider 84 is programmed in the same manner as described above with reference to the unmodified system in Fig. 1.
Programming divider 84 provides the means for selecting the various harmonics in the second harmonic spectrum to which oscillator 16 is phase-locked.

Due to the cross-over connections in relation to pulse generators 20 and 56 and pulse mixers 24 and 60, the frequency of oscillator 16 continues to be controlled by pulse mixer 24 and hunting circuit 48 as described above in relation to Fig. 1. The beat frequency signal generated by pulse mixer 60 has a frequency equal to the offset fre--: - .
, 1()36679 quency when the frequency of oscillator 16 is phase-locked to the required harmonic in the second harmonic spectrum. The signal from pulse mixer 60 is coupled to gate 38. As previously described, gate 38 generates an enabling signal on line 36 thereby operating pulse mixer 24 and phase-locking oscillator 16 to a frequency equal to a selected harmonic in the second harmonic spectra displaced by a desired offset frequency.

I

- ~2 -~ , . .... .... . . . . . . .
...

Claims (15)

WHAT I CLAIM IS:
1. Claim 1. A frequency synthesizer for generating an output signal having a frequency which is variable in discrete steps over a prescribed frequency range, each step having a pre-determined maximum size and including intermediate inter-polation steps, said frequency synthesizer comprising:
   (i) means for generating a signal having a frequency equal to the primary reference frequency;
   (ii) means for generating an interpolation signal frequency;
   (iii) frequency dividing means having a variable dividing ratio n, including means for coupling said frequency dividing means to said means (ii), said frequency dividing means being responsive to said interpolation signal for generating a first output signal having a frequency equal to said interpolation signal frequency divided by said variable dividing ratio n;
   (iv) frequency generating means coupled to said means (i) and said means (iii) for generating a secondary reference signal having a frequency equal to said primary reference signal fre-quency displaced by the frequency of said first output signal;
   (v) a controllable oscillator for producing said output signal and including a frequency control means for tuning said controllable across a predetermined frequency range and for locking said output signal frequency to a predetermined frequency within said predetermined frequency range;
   (vi) programmable signal generator means for genera-ting a programming signal having a frequency equal to a unique value when said controllable oscillator output signal has a frequency equal to said predetermined frequency;
   (vii) harmonic selection means for phaselocking said output signal frequency to a harmonic of said secondary reference signal frequency including means for coupling said harmonic se-lection means to said secondary reference signal and to said programming signal, said harmonic selection means being respon-sive to said programming signal for producing a control signal for operating said frequency control means so that said output signal is phase-locked on the selected harmonic of said -43a-secondary reference signal frequency; and (viii) said frequency control means being connected to said harmonic selection means and responsive to said control signal for establishing the frequency of said output signal at said predetermined frequency when said programming signal frequency is equal to said unique value.
2. Claim 2. A frequency synthesizer as claimed in Claim 1, in which said interpolation signal frequency is equal to a multiple or a subharmonic of said primary reference signal frequency.
3. Claim 3. A frequency synthesizer as claimed in Claim 2, in which said subharmonic of said primary reference signal frequency has a value formed by raising the number 10 to an integral power, thereby providing an interpolation signal frequen-cy which is decimally related to said primary reference signal frequency.
4. Claim 4. A frequency synthesizer as claimed in Claim 1, in which said output signal frequency is variable in discrete steps which have a maximum size equal to an integral multiple of said primary reference signal frequency.
5. Claim 5. A frequency synthesizer as claimed in Claim 1, in which the frequency of said output signal is displaced in frequency by an amount equal to the frequency of said interpol-ation signal from the selected harmonic of said primary reference signal frequency, said selected harmonic having a harmonic number equal to said variable dividing ratio n.
6. Claim 6. A frequency synthesizer according to Claim 1, in which said secondary reference signal is generated by a mixing means coupled to said primary reference signal and to said first output signal, said mixing means being operable for comparing the frequency of said primary reference signal and the frequency of said first output signal to produce a second output signal, said second output signal containing a plurality of frequencies including said primary reference signal frequency, said first output signal frequency, and the difference frequencies between said primary reference signal frequency and said first output signal frequency, and further including filter means coupled to said second output signal, said filter means being used for generating a signal having a frequency equal to said primary reference signal frequency displaced by the frequency of said first output signal.
7. Claim 7. A frequency synthesizer as claimed in Claim 1, in which said frequency generating means for generating said secondary reference signal frequency includes:
   (i) an auxiliary controllable oscillator for gene-rating a second output signal including a second frequency control means for tuning said auxiliary controllable oscillator across a predetermined frequency range and for locking said second output signal to said secondary reference signal frequency;
   (ii) first mixing means coupled to said auxiliary controllable oscillator and coupled to said primary reference signal for producing a third output signal having a frequency equal to the difference between the frequency of said primary reference signal frequency and said second output signal frequency;
   (iii) second comparing means being coupled to said first output signal and to said third output signal for produ-cing a second control signal; and (iv) said second frequency controlling means being connected to said second comparing means and being responsive to said second control signal for establishing the frequency of said second output signal at a value so that the frequency of said third output signal equals the frequency of said first output signal.
8. Claim 8. A frequency synthesizer as claimed in Claim 1, in which the interpolation signal frequency is equal to the sum of a sub-harmonic of said primary reference frequency plus a frequency equal to an integer multiple of the primary reference signal frequency.
9. Claim 9. A frequency synthesis system as claimed in Claim 1, comprising in combination a first frequency synthesizer system as claimed in Claim 1 and a second similar frequency synthesizer system in which said means for generating said in-terpolation signal frequency for said first first frequency synthesizer system includes: said second frequency synthesizer system, means for coupling the means for generating said primary reference frequency and said programmable signal generating means for said first frequency synthesizer system to said second frequency synthesizer system, means for coupling said output signal generated by said controllable oscillator and second fre-quency synthesizer system to a second frequency dividing means being operable for generating a second output signal having a frequency equal to a submultiple of the frequency of said output signal generated by said controllable oscillator in said second frequency synthesizer system said second output signal being the interpolation signal for said first frequency synthesizer system, thereby establishing the frequency of said interpolation signal for said first frequency synthesizer system at a frequency which is harmonically related to said primary reference signal frequency.
10. Claim 10. A frequency synthesizer system as claimed in Claim 9, in which said second predetermined dividing ratio is equal to an integer which is an integral multiple of the number 10, said integral multiple having a vlaue equal to the number of complete frequency decades covered by said predeter-mined frequency range for said controllable oscillator in said second frequency synthesizer system, thereby providing an interpolation signal frequency which is a decimal harmonic of said primary reference signal frequency.
    
    -46a-
11. Claim 11. A frequency synthesizer system as claimed in Claim 9, wherein said means for coupling the means for generating said primary reference frequency and said programmable signal generator means for said first frequency synthesizer sys-tem to said second frequency synthesizer system include third and fourth frequency divider means respectively, each having the same predetermined dividing ratio for generating output signals having a frequency equal to a submultiple of said primary reference frequency and of said programming signal frequency respectively for said first frequency synthesizer system, thereby establishing the primary reference signal frequency and the programming signal frequency for said second frequency synthe-sizer system at a subharmonic of the primary reference signal frequency and the programming signal frequency respectively for said first frequency synthesizer system.
12. Claim 12. A frequency synthesizer system as claimed in Claim 11, in which said third and fourth predetermined dividing ratios are equal to an integer which is an integral mul-tiple of the number 10, said integral multiple having a value equal to the number of complete frequency decades covered by said predetermined frequency range for said controllable oscilla-tor in said second frequency synthesizer system thereby providing an interpolation signal frequency which is a desired harmonic of said primary reference signal frequency.
13. Claim 13. A frequency synthesizer as claimed in Claim 1, in which said means for generating said interpolation signal includes:
    (i) a controllable interpolation oscillator for producing a second output signal having a variable frequency, said interpo-lation oscillator including a second frequency control means for tuning said interpolation oscillator over a prescribed frequency range and locking the frequency of said second output signal to said interpolation signal frequency;
    (ii) gated frequency divider means coupled to said interpolation oscillator and having a variable dividing ratio -47a-programmed to divide the frequency of said second output signal by a factor decimally related to said required interpolation frequency for producing a third output signal having a frequency equal to a selected sub-harmonic of said interpolation signal frequency;
    (iii) fixed frequency dividing means coupled to said primary reference signal frequency for producing a fourth output signal having a frequency equal to a sub-harmonic of said primary reference signal frequency equal to said selected sub-harmonic;
    (iv) comparing means coupled to said gated frequency divider means and said fixed frequency dividing means, said comparing means being responsive to said third and fourth output signals for generating a second control signal; and (v) means for coupling said second frequency control means to said comparing means, said second frequency controlling means being responsive to said second control signal for esta-blishing the frequency of said second output signal at a fre-quency equal to said interpolation signal frequency.
14. Claim 14. A frequency synthesizer as claimed in Claim 13, in which the smallest incremental decimal step in the interpolation signal frequency corresponds to said sub-harmonic of said primary reference frequency.
15. Claim 15. A frequency synthesizer system for gene-rating a signal having a frequency which differs from a selected harmonic of a reference frequency by a fixed offset frequency which includes:
    (i) means for producing a first harmonic spectrum containing harmonics of a primary reference frequency;
    
    (ii) controllable signal generator means for producing a second harmonic spectrum containing harmonics of an auxiliary reference frequency;
    (iii) a controllable oscillator for generating a first output signal of variable frequency f1 and including a first frequency control means for tuning said controllable -48a-oscillator over a predetermined frequency range and for locking said first output signal to a predetermined frequency, said frequency range including a selected portion of said second har-monic spectrum;
    (iv) first circuit means coupled to said controllable oscillator and to said means (ii) for comparing the phase of said first output signal with the signal generated by said means (ii) and operable to produce a first control signal having an amplitude dependent on the relative phase difference between the first output signal and the signal generated by said means (ii), said amplitude having a unique value when the frequency difference between the first output signal and a selected harmonic in the second harmonic spectrum has a desired value;
    (v) said first frequency control means being connec-ted to said first circuit means and being responsive to said first control signal for establishing the frequency of said first output signal at said predetermined frequency when said first control signal has said unique value;
    (vi) sweeping means coupled to said first frequency control means and operable by said first control signal for swee-ping the frequency of said first output signal across said second harmonic spectrum when said first output signal frequency is dif-ferent from said predetermined frequency;
    (vii) a second frequency control means having a first and second signal inputs connected to said means(i) and to said means (ii) for comparing the frequency difference between the output signal frequency of said means (i) and (ii) with sub-harmo-nics of a programmed reference signal having a frequency equal to a first selected fixed frequency and for generating a second control signal; said second control signal being coupled to said means (ii) for controlling said second harmonic spectrum so that the harmonics in said second harmonic spectrum have a predetermined relationship with the harmonics in said first harmonic spectrum and one specific harmonic in said second harmonic spectrum differs in frequency from said selected harmonic in said first harmonic spectrum by said first selected fixed frequency;
    
    -49a-(viii) second circuit means coupled to said controllable oscillator and to said means (i) for mixing said first output signal with frequencies in said first harmonic spectrum to produce a second output signal having a frequency equal to a second selected fixed frequency when said specific harmonic in said first harmonic spectrum differs in frequency from the frequency of said first output signal by an amount equal to said second selected fixed frequency; and (ix) gate means coupled to said means (viii) and res-ponsive to said second output signal and coupled to said means (iv) for producing a third control signal to enable said means (iv) when the frequency of said second output signal is within a predetermined frequency range centered about a frequency equal to said second selected frequency, wherein said means (iv) is enabled and generates said first control signal thereby establishing the frequency of said first output signal at said predetermined fre-quency which is equal to said selected harmonic in said first harmonic spectrum plus said first selected fixed frequency.