CA1036678A - Electrical digital fade in and fade out circuit - Google Patents

Abstract

ELECTRICAL DIGITAL FADE IN AND FADE OUT CIRCUIT
ABSTRACT OF THE DISCLOSURE
An analog signal amplifier is connected in series in a control signal path of a control system. The feedback resistance which controls the gain of the amplifier is regulated in a digital manner and in response thereto the output of the amplifier is varied in a plurality of discrete steps in order to fade in or fade out the control signal. The control for the feedback resistance utilizes a quad analog switch which responds to the output from a digital counter. The circuit is applicable to aircraft control systems to provide smooth transitions during the switching of signal gain paths.

Description

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BACKGROUND OF THE INVENTION
Field of the Invention - This invention relates to an electronic circuit for providing fade in and fade out of electrical signals in a digital manner, and more specifically to an electronic amplifier circuit in which the feedback resistance and hence the gain of the ~ ~
amplifier is varied in a series of discrete digital steps ~ -in response to the output from a digital counter. The circuit is particularly adapted to provide smooth transi-tions during the switching of signal gain paths in control systems.
Description of the Prior Art - Electronic fader circuits which may be used to fade in and fade out a control signal are well known in the art. Such circuits are found to be desirable in control systems when switch-ing from one signal path to another signal path, and are used commonly to prevent transients in the controlled , .. . ..
device. For example, when switching the control of an aircraft from manual control to autopilot control, or vice versa, it is possible that the resulting actuating signal for the aircraft control surfaces produced by the autopilot will be of a much different value from that produced in the manual control system. Instantaneous switching from one to the other may cause a violent excursion of the control surfaces which may be not only uncomfortable for the passengers but dangerous as well.
Consequently, it is common, when switching from one ;

-2-:1~366r~g3 control mode to another, to employ fader circuits which cause the control signal to be changed from one level to the other in a gradual manner.
It has been found that using the prior art circuits for fade in and fade out often produces nonlinear or erratic response. For example, a device known as a "rayzistor" has been used in conjunction with a timing circuit to vary the gain of a signal amplifier, but in this device each signal gain path requires a separate timing circuit, and the gain change produced by the ray-zistor is nonlinear.
The present invention overcomes the deficiencies of the prior art fader circuits by providing for fade in and fade out of the electrical signal in a controlled digital manner. The gain of a signal amplifier is varied from zero to steady state, or from steady state to zero, in a plurality of discrete equal steps. Fur~hermore, a plurality of the digitally controlled amplifier circuits may be controlled by one common clock for various portions of the control system.
SUMMARY OF THE INVENTION
A control signal is fed as an input to an analog signal amplifier, and a plurality of feedback resistors is connected in series from the output of the signal amplifier to its input. An analog switch is connected in parallel with each of the plurality of feedback resistors, and the switches are selectively opened or closed in

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response to the output from a digital counter in order to vary the feedback resistance around the signal amplifier in a digital manner. Varying the feedback resistance will vary the gain of the signal amplifier. By varying the output from the digital counter between zero and a maximum value, the gain of the signal amplifier may be varied in a series of controlled digital steps.
In accordance with a particular embodiment, an apparatus for varying the gain of an amplifier in a series of discrete steps comprises an amplifier having an input and an output, a feedback circuit connected between said amplifier output and said amplifier input, said feedback circuit comprising a plurality of series connected resistors whose respective resistance values vary in a binary progression, a plurality of electronic switches, -each directly connected in parallel with a corresponding one of said resistors, closure of each switch causing the resistor to which it is connected to be bypassed and removed from said feedback circuit during the time that the switch means is closed, a binary up/down counter having a plurality of output lines, each of said output lines being connected to one of said switch means, and means for actuating said binary counter to produce a signal on each of said output lines which causes said plurality of switch means to open and close sequentially to thereby vary the ~;
total resistance of said feedback circuit in a .series of discrete steps.
BRIE_ DESCRIPTION OF THE DRAWI~GS
Fig. 1 is a schematic block diagram of a typical control system which utilizes the fader circuit of the present invention.
Fig. 2 is a schematic diagram of the fade in and fade out circuit of the present invention.
Fig 3 is a timing chart showing the input and output signals for the apparatus of Fig. 2. -~
Fig. 4 is a graph showing the operation of the present ~ - 4 -':

1C;~36~78 invention in contrast to that of the prior art.
Fig. 5 is a schematic block diagram showing a logic system incorporating a plurality of fader circuits.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The novel electrical digital fade in and fade out circuit of the present invention will be referred to as "DIGO-FADE". Fig. 1 shows a representative aircraft control system in which the novel DIGO-FADE eircuit may be used.
Present-day aireraft utilize autopilot systems which regulate the aireraft eontrol surfaces to maintain a desired flight attitude automatically. The autopilot _ 4a -6f~r7~
is generally not used for certain flight conditions such as takeoff and landing since at these times the pilot desires to retain complete command of the aircraft. To achieve smoothness of operation in the aircraft control system during switching between one control mode and the i-other, the signals from each of the input sources are faded in and out instead of being abruptly switched on and off.
As shown in Fig. 1, the command signals produced by an autopilot 10 are fed through~,a DIGO-FADE circuit 12 to command the position of the aircraft control surfaces shown schematically at 14. During manual operation the pilot commands 16 are also fed through a DIGO-FADE circuit 18 to regulate the aircraft control surfaces 14. Assuming that the aircraft is being operated in its automatic control mode, DIGO-FADE circuit 12 will be maintained at its maximum gain while DIGO-FADE circuit 18 is main-tained at zero gain so that only the autopilot c~mmands are fed to the aircraft control surfaces. When the pilot desires to switch from the autopilot control system to a manual control, logic block 20 will respond to the pilot's input such as by a switch in the cockpit and cause DIGO-FADE circuit 12 to gradually reduce its gain thereby fading out the autopilot command signal, and will cause DIG0-FADE
circuit 18 to gradually increase its gain thereby fading in the pilot's manual commands. DIG0-FADE circuit 12 will ultimately reach a zero gain condition, while DIGO-FADE circuit 18 will reach its maximum gain condition, -the transition from autopilot to manual control thus being :,.. '' '' ' : ' ' : '. '.................. ' ,.
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achieved smoothly as a result of the control of DIG0-FADE
circuits 12 and 18 by logic block 20.
The operation of the DIGO-FADE circuits 12 and 1`8 of Fig. 1 is shown in detail in Fig. 2. The DIG0-FADE cir-cuit is essentially an analog signal amplifier shown at 22 with a digitally controlled variable gain. An input signal ei, which may be an AC or a DC signal, is fed as an input to amplifier 22 through a summing resistance Rs.
The other input of the amplifier 22 may be grounded through a resistor 24. The output from amplifier 22 is shown as eO. Connected from the output to the input of the amplifier is a feedback resistance shown schematically -as RFB which comprLses four resistors, R, 2R, 4R and 8R. Any number of resistors may be used as long as these resistance values vary in a binary progression. Also connected in the feedback path is a capacitance C. The gain of the signal amplifier 22 is equal to eO/ei which is approximately equal to RFB/RS. By switching in and out of the circuit different combinations of the feedback resistors, the gain of the amplifier 22 may be varied in a digital manner. The summing resistor RS is chosen for the desired steady state gain and then held constant.
Shown in parallel with each of the feedback resistors are single pole, single throw switches denoted A, B, C
and D which can be turned on and off electrically by a digital signal from a counter 26. The analog switches A, B, C and D are formed by an integrated circuit chip known ~?3~678 as a quad analog switch,for example part number DG201 manufactured by Siliconix.
Counter 26 is a straight four bit binary up/down counter such as part number MC14516 manufactured by ~ -Motorola. As shown in Fig. 2, the counter 26 has an up/down input controlled by a signal F and a RESET input.
The counter also has an inverted carry out (CO) output.
Stepping of the counter 26 is regulated by a control pulse (CP) input produced by control block 28 which consists of a Nand gate having two inputs, one being the CO output from counter 26 and the other being a train of pulses supplied via line 31 by a clock 30. The output from the control 28 is a train of control pulses CP which will cause the counter to stop at its maximum or minimum `
count. The control 28 will either pass or inhibit the ' -pulses from clock 30 to the counter 26. Clock 30 generates a periodic square pulse train. The clock may be a MC14011 quad Nand gate integrated circuit with an RC timing network. One advantage of the present DIGO-FADE
circuit over the prior art fader networks is that only one clock is required regardless of the number of DIGO-FADE
circuits in a control system.
The operation of the DIGO-FADE circuit of Fig. 2 will be explained with reference to the pulses shown in Fig. 3. Waveform 32 of Fig. 3 is a plot of the gain of ~;
signal amplifier 22 as a function of time and shows both a fade in where the gain is increasing and a fade out ... " . . .. .

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where the gain is decreasing. Also shown in conjunction with Fig. 3 are the four outputs from counter 26, Ql' Q2~ Q3 and Q4, the inverted carry out signal from counter 26 CO, the up/down input F to counter 26, the control pulse input GP to counter 26, the output pulses from clock 30 and the RESET input to counter 26.
The up/down input F to counter 26 determines the status of the DIGO-FADE circuit, a digital one on this line causing a fade in with the gain of the signal amplifier going from zero to maximum in 16 digital steps, and a digital zero on this line causing a fade out wherein the gain of the signal amplifier proceeds from a maximum value to zero also in 16 steps. A digital one on the RESET input to counter 26 produces a direct reset func-tion that instantly resets the counter to zero and thus causes the gain of the signal amplifier to become zero.
A digital zero on the reset line will permit fade in or fade out depending on the state of the up/down input F.
Assume initially that the signal on line F is a digital zero and that the RESET input is a digital zero. At this time the outputs Ql through Q4 of counter 26 will all be zeros, and the carry out C0 output from counter 26 will be equal to zero. The Nand gate of control block 28 will receive the CO output from counter 26 which is a digital zero so that the output from the Nand gate will be a digital one, that is, there will be no input pulses to counter 26 appearing on line CP and the outputs from the - . ~ . ~ .. . . .

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counter will all be a digital zero. With the outputs Ql through Q4 from the counter all at zero, all switches A - -through D will be closed producing zero feedback resis-tance around signal amplifier 22 and thus zero gain.
This condition is shown in Fig. 3 in conjunction with -clock pulse number one.
During clock pulse number two the input F is switched to a digital one which will produce a fade in.
Output C0 from counter 26 instantly changes from a digital zero to a digital one thereby permitting the Nand gate in control block 28 to pass therethrough and also -~
invert the clock pulses from clock 30. The inverted clock pulses are shown at CP and cause the counter to count up in a digital manner from 0000 to 1111. ~uring clock pulse number three the counter output Ql switches from a digital zero to a digital one thereby opening switch A and placing the resistance value R in the feed-:
back path of signal amplifier 22. The feedback resis-tance RFB is now approximately 1/16 of its maximum value, and the gain of the signal amplifier 22 will vary accordingly as shown at line 32 of Fig. 3. During the next clock pulse, pulse number four, output Ql from counter 26 will become a digital zero and output Q2 will become a digital one, thereby opening switch B and closing switch A. At this time a resistance value equal to 2R is in the feedback path of signal amplifier 22 and the feedback resistance and the gain of the signal _g_ .. . . : : , . . .

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~ 3~ ~r~8 amplifier are now approximately 2/16 of the maximum value.
The counter proceeds in this manner until outputs Ql through Q4 are all a digital one, all switches A through D are open and all resistances of values R, 2R, 4R and 8R
are in the feedback path of the signal amplifier. At this time the feedback resistance RFB is a maximum and likewise the gain of the signal amplifier 22 is a maximum.
At this time shown at clock pulse 17 the CO output of counter 26 becomes a digital zero and the output from the Nand gate in control 28 switches to and remains a digital one which inhibits any further clock pulses from appearing on line CP of counter 26. The DIG0-FADE circuit is now held at its maximum gain.
The fade out function is achieved as shown in Fig. 3 when the F input to counter 26 is switched from a digital one ~o a digital zero as illustrated during clock pulse 23. At this time the C0 output from counter 26 immediately switches from a digital zero to a digital one, thereby permitting clock pulses from clock 30 to pass through the Nand gate of control 28 while being inverted and appear on input line CP of counter 26. However, since the input on line F is now a digital zero, the counter 26 will start counting down, that is, the outputs Ql through Q4 will proceed from a digital 1111 state to a digital 0000 state, and the gain of the signal amplifier 22 will decrease in a serles of discrete steps from the maximum value to zero. When the outputs Ql through Q4 from ''~. ~ .

1~366~8 counter 26 reach zero as shown at clock pulse 38, the CO
output from counter 26 now becomes a digital zero and -the output from the Nand gate of control 28 is held at a digital one~ and counter 26 receives no more clock pulses on line CP thereby holding the gain of signal amplifier 22 to zero.
The operation of the RESET input to counter 26 is shown in conjunction with reference numeral 34 of Fig. 3.
A fade in has been signalled during clock pulse 42 and has proceeded in a normal fashion until clock pulse 45 when a reset pulse is generated such as by logic block 20 of Fig. 1. At this time all the outpups from counter 26 ;
Ql through Q4 become a digital zero and r~main that way until the termination of the reset pulse during clock ~ ~-pulse 47. However, at clock pulse 48 with no reset ~ulse appearing on the reset line, the DIG0-FADE circuit is in a condition with the F input being a digital one to begin another fade in as illustrated at reference numeral 36 of Fig. 3. Thus, with a digital one appearing on the reset line, the counter is reset instantly to zero and the gain of the signal amplifier 22 is reduced to zero.
When the reset line is returned to a digital zero, the signal is automatically faded back in. If during the reset time the F input to counter 26 contains a digital zero, the counter will remain in its zero condition. `~
The time required for a signal to be completely faded in or out is shown on Fig. 3 as TF and is detenmined ~ r~
by the rate of the clock pulses. For a representative control system, TF, is approximately 3.5 seconds. TF
can be varied by the RC network of clock 30.
The capacitor C of Fig. 2 in the feedback path is provided in order to avoid high frequency oscillations.
The resistor 24 between the positive terminal of the signal amplifier 22 and ground is used to minimize offset current.
Fig. 4 shows graphically the gain of the DIGO-FADE
circuit of this invention with respect to time as compared with the gain of a prior art fader circuit utilizing a rayzistor. The rayzistor gain is extremely nonlinear and is considerably delayed in its response. The initial response of the rayzistor fader circuit is quite slow and then increases rapidly to the maximum gain. The DIGO-FADE
circuit of this invention is completely linear and predictable from zero gain through maximum gain.
Fig. 5 shows a typical logic circuit which may be used to determine if all DIGO-FADE circuits used in a particular aircraft channel such as pitch or roll have been appropriately faded in or out. As shown in Fig. 5 AND circuit 40 will produce an output signal which is a digital one only if the input signals thereto indicate that two DIGO-FADE circuits have been completely faded out. The C0 output from the counter 26 and the F input to counter 26 for each DIGO-FADE circuit are fed to corresponding NOR circuits 42 and 44. Only if both ~ 36~rf8inputs to NOR circuit 42 are a digital zero will the NOR
circuit 42 produce a digital one. When all the inputs to -AND circuit 40 are a digital one, the output from AND
circuit 40 will be a digital one thereby indicating that all DIGO-FADES have been faded out. Corresponding logic may be designed for fade in. ~ --While the present invention has been described in terms of its preferred embodiment, it will be apparent to those skilled in the art, that modifications may be made to the details of construction and the combination of components without departing from the scope of the ~;
invention as hereinafter claimed. -:

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Claims

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:-

1. Apparatus for varying the gain of an amplifier in a series of discrete steps comprising:
an amplifier having an input and an output, a feedback circuit connected between said amplifier output and said amplifier input, said feedback circuit comprising a plurality of series connected resistors whose respective resistance values vary in a binary progression, a plurality of electronic switches, each directly connected in parallel with a corresponding one of said resistors, closure of each switch causing the resistor to which it is connected to by bypassed and removed from said feedback circuit during the time that the switch means is closed, a binary up/down counter having a plurality of output lines, each of said output lines being connected to one of said switch means, and means for actuating said binary counter to produce a signal on each of said output lines which causes said plurality of switch means to open and close sequentially to thereby vary the total resistance of said feedback circuit in a series of discrete steps.