BRPI0920229A2 - modelo de memória para atributos de hardware dentro de um sistema de memória transacional - Google Patents
modelo de memória para atributos de hardware dentro de um sistema de memória transacionalInfo
- Publication number
- BRPI0920229A2 BRPI0920229A2 BRPI0920229A BRPI0920229A BRPI0920229A2 BR PI0920229 A2 BRPI0920229 A2 BR PI0920229A2 BR PI0920229 A BRPI0920229 A BR PI0920229A BR PI0920229 A BRPI0920229 A BR PI0920229A BR PI0920229 A2 BRPI0920229 A2 BR PI0920229A2
- Authority
- BR
- Brazil
- Prior art keywords
- memory
- hardware attributes
- model
- transactional
- memory system
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/3834—Maintaining memory consistency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0715—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a system implementing multitasking
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
- G06F11/0724—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU] in a multiprocessor or a multi-core unit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3017—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system is implementing multitasking
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3037—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a memory, e.g. virtual memory, cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3089—Monitoring arrangements determined by the means or processing involved in sensing the monitored data, e.g. interfaces, connectors, sensors, probes, agents
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3466—Performance evaluation by tracing or monitoring
- G06F11/3471—Address tracing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
- G06F2201/885—Monitoring specific for caches
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Software Systems (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- Computer Hardware Design (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/346,539 US8627014B2 (en) | 2008-12-30 | 2008-12-30 | Memory model for hardware attributes within a transactional memory system |
PCT/US2009/068114 WO2010077884A2 (en) | 2008-12-30 | 2009-12-15 | Memory model for hardware attributes within a transactional memory system |
Publications (1)
Publication Number | Publication Date |
---|---|
BRPI0920229A2 true BRPI0920229A2 (pt) | 2015-12-29 |
Family
ID=42286303
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BRPI0920229A BRPI0920229A2 (pt) | 2008-12-30 | 2009-12-15 | modelo de memória para atributos de hardware dentro de um sistema de memória transacional |
Country Status (6)
Country | Link |
---|---|
US (2) | US8627014B2 (pt) |
JP (1) | JP5416223B2 (pt) |
CN (1) | CN101814017B (pt) |
BR (1) | BRPI0920229A2 (pt) |
TW (1) | TWI461912B (pt) |
WO (1) | WO2010077884A2 (pt) |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
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US8627014B2 (en) | 2008-12-30 | 2014-01-07 | Intel Corporation | Memory model for hardware attributes within a transactional memory system |
US9785462B2 (en) | 2008-12-30 | 2017-10-10 | Intel Corporation | Registering a user-handler in hardware for transactional memory event handling |
US8812796B2 (en) * | 2009-06-26 | 2014-08-19 | Microsoft Corporation | Private memory regions and coherence optimizations |
US8489864B2 (en) * | 2009-06-26 | 2013-07-16 | Microsoft Corporation | Performing escape actions in transactions |
US8356166B2 (en) * | 2009-06-26 | 2013-01-15 | Microsoft Corporation | Minimizing code duplication in an unbounded transactional memory system by using mode agnostic transactional read and write barriers |
US20100332768A1 (en) * | 2009-06-26 | 2010-12-30 | Microsoft Corporation | Flexible read- and write-monitored and buffered memory blocks |
US8250331B2 (en) * | 2009-06-26 | 2012-08-21 | Microsoft Corporation | Operating system virtual memory management for hardware transactional memory |
US8370577B2 (en) | 2009-06-26 | 2013-02-05 | Microsoft Corporation | Metaphysically addressed cache metadata |
US8229907B2 (en) * | 2009-06-30 | 2012-07-24 | Microsoft Corporation | Hardware accelerated transactional memory system with open nested transactions |
US8402218B2 (en) | 2009-12-15 | 2013-03-19 | Microsoft Corporation | Efficient garbage collection and exception handling in a hardware accelerated transactional memory system |
US9092253B2 (en) * | 2009-12-15 | 2015-07-28 | Microsoft Technology Licensing, Llc | Instrumentation of hardware assisted transactional memory system |
US8539465B2 (en) * | 2009-12-15 | 2013-09-17 | Microsoft Corporation | Accelerating unbounded memory transactions using nested cache resident transactions |
US8533440B2 (en) | 2009-12-15 | 2013-09-10 | Microsoft Corporation | Accelerating parallel transactions using cache resident transactions |
US20120059971A1 (en) * | 2010-09-07 | 2012-03-08 | David Kaplan | Method and apparatus for handling critical blocking of store-to-load forwarding |
US9104690B2 (en) * | 2011-01-27 | 2015-08-11 | Micron Technology, Inc. | Transactional memory |
CN104137060B (zh) * | 2011-12-30 | 2018-03-06 | 英特尔公司 | 高速缓存协处理单元 |
EP2831721B1 (en) | 2012-03-30 | 2020-08-26 | Intel Corporation | Context switching mechanism for a processing core having a general purpose cpu core and a tightly coupled accelerator |
US10120809B2 (en) * | 2015-09-26 | 2018-11-06 | Intel Corporation | Method, apparatus, and system for allocating cache using traffic class |
TWI587218B (zh) | 2016-09-10 | 2017-06-11 | 財團法人工業技術研究院 | 記憶體事務層級模型模擬方法及系統 |
US10620971B2 (en) | 2017-02-22 | 2020-04-14 | International Business Machines Corporation | Accelerating reference count processing in object deletion |
CN110647663B (zh) * | 2019-09-09 | 2021-12-17 | 中国人民解放军国防科技大学 | 面向最短路径问题的图结点属性存储器实现方法和装置 |
CN111047187B (zh) * | 2019-12-12 | 2023-10-17 | 浙江大搜车软件技术有限公司 | 信息匹配处理方法、装置、计算机设备和存储介质 |
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JP2651037B2 (ja) * | 1990-04-23 | 1997-09-10 | 株式会社日立製作所 | アドレスバス制御装置 |
US6216200B1 (en) * | 1994-10-14 | 2001-04-10 | Mips Technologies, Inc. | Address queue |
US6192452B1 (en) * | 1999-02-26 | 2001-02-20 | International Business Machines Corporation | Method and system for avoiding data loss due to cancelled transactions within a non-uniform memory access system |
US6549996B1 (en) * | 1999-07-02 | 2003-04-15 | Oracle Corporation | Scalable multiple address space server |
US6490668B2 (en) | 2000-12-15 | 2002-12-03 | Hewlett-Packard Company | System and method for dynamically moving checksums to different memory locations |
US7035963B2 (en) * | 2000-12-27 | 2006-04-25 | Intel Corporation | Method for resolving address space conflicts between a virtual machine monitor and a guest operating system |
US7565687B2 (en) * | 2002-02-08 | 2009-07-21 | International Business Machines Corporation | Transmission control system, server, terminal station, transmission control method, program and storage medium |
JP2004005710A (ja) * | 2003-06-23 | 2004-01-08 | Hitachi Ltd | 情報処置装置 |
FR2859307A1 (fr) * | 2003-08-27 | 2005-03-04 | St Microelectronics Sa | Memoire cache a lecture asynchrone et dispositif de controle de l'acces a une memoire de donnees comprenant une telle memoire cache |
US20050091459A1 (en) * | 2003-10-23 | 2005-04-28 | Nhon Quach | Flexible mechanism for enforcing coherency among caching structures |
US7237131B2 (en) * | 2003-12-30 | 2007-06-26 | Intel Corporation | Transaction-based power management in a computer system |
US7395374B2 (en) * | 2004-01-20 | 2008-07-01 | Hewlett-Packard Company, L.P. | System and method for conflict responses in a cache coherency protocol with ordering point migration |
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EP1735983B1 (en) * | 2004-04-14 | 2008-02-06 | Telecom Italia S.p.A. | Method and system for handling content delivery in communication networks |
US7644239B2 (en) * | 2004-05-03 | 2010-01-05 | Microsoft Corporation | Non-volatile memory cache performance improvement |
JP4431022B2 (ja) | 2004-10-18 | 2010-03-10 | 株式会社日立製作所 | コンピュータシステム及びその制御方法 |
US7490199B2 (en) * | 2005-05-09 | 2009-02-10 | Noam Camiel | System and method for safe removal of a removable device from a digital appliance |
WO2007015925A1 (en) * | 2005-08-01 | 2007-02-08 | Sun Microsystems, Inc. | Avoiding locks by transactionally executing critical sections |
US8180977B2 (en) * | 2006-03-30 | 2012-05-15 | Intel Corporation | Transactional memory in out-of-order processors |
US8180967B2 (en) * | 2006-03-30 | 2012-05-15 | Intel Corporation | Transactional memory virtualization |
US20080005504A1 (en) * | 2006-06-30 | 2008-01-03 | Jesse Barnes | Global overflow method for virtualized transactional memory |
TWI317065B (en) * | 2006-08-11 | 2009-11-11 | Shiwu Lo | Method of accessing cache memory for parallel processing processors |
US7783805B2 (en) * | 2006-11-29 | 2010-08-24 | Cisco Technology, Inc. | Interlocking input/outputs on a virtual logic unit number |
US7937535B2 (en) * | 2007-02-22 | 2011-05-03 | Arm Limited | Managing cache coherency in a data processing apparatus |
US7917701B2 (en) * | 2007-03-12 | 2011-03-29 | Arm Limited | Cache circuitry, data processing apparatus and method for prefetching data by selecting one of a first prefetch linefill operation and a second prefetch linefill operation |
US8751859B2 (en) | 2007-05-10 | 2014-06-10 | International Business Machines Corporation | Monitoring lost data in a storage system |
JP4973730B2 (ja) * | 2007-06-20 | 2012-07-11 | 富士通株式会社 | 演算処理装置及び演算処理装置の制御方法 |
US8195832B2 (en) * | 2007-12-12 | 2012-06-05 | Alcatel Lucent | Facilitating management of layer 2 hardware address table based on packet priority information |
US8078807B2 (en) * | 2007-12-27 | 2011-12-13 | Intel Corporation | Accelerating software lookups by using buffered or ephemeral stores |
US8627014B2 (en) | 2008-12-30 | 2014-01-07 | Intel Corporation | Memory model for hardware attributes within a transactional memory system |
-
2008
- 2008-12-30 US US12/346,539 patent/US8627014B2/en not_active Expired - Fee Related
-
2009
- 2009-12-15 BR BRPI0920229A patent/BRPI0920229A2/pt not_active Application Discontinuation
- 2009-12-15 JP JP2011543575A patent/JP5416223B2/ja not_active Expired - Fee Related
- 2009-12-15 WO PCT/US2009/068114 patent/WO2010077884A2/en active Application Filing
- 2009-12-17 TW TW098143379A patent/TWI461912B/zh not_active IP Right Cessation
- 2009-12-28 CN CN200910216935.2A patent/CN101814017B/zh not_active Expired - Fee Related
-
2012
- 2012-01-26 US US13/359,238 patent/US8769212B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2012514254A (ja) | 2012-06-21 |
CN101814017B (zh) | 2015-02-11 |
TWI461912B (zh) | 2014-11-21 |
JP5416223B2 (ja) | 2014-02-12 |
US20120159079A1 (en) | 2012-06-21 |
US8769212B2 (en) | 2014-07-01 |
TW201037517A (en) | 2010-10-16 |
WO2010077884A2 (en) | 2010-07-08 |
US20100169580A1 (en) | 2010-07-01 |
US8627014B2 (en) | 2014-01-07 |
CN101814017A (zh) | 2010-08-25 |
WO2010077884A3 (en) | 2010-09-30 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
B15I | Others concerning applications: loss of priority |
Free format text: PERDA DA PRIORIDADE US 12/346,539 DE 30/12/2008, CONFORME AS DISPOSICOES PREVISTAS NA LEI 9.279 DE 14/05/1996 (LPI) ART. 16 7O E NO ART. 28 DO ATO NORMATIVO 128/1997, POR NAO ATENDER AO DISPOSTO NO ART. 27 DO ATO NORMATIVO 128/1997, POIS NAO FOI APRESENTADA CESSAO DA REFERIDA PRIORIDADE, QUE POSSUI DEPOSITANTE DIFERENTE DO DEPOSITANTE DA FASE NACIONAL. |
|
B12F | Other appeals [chapter 12.6 patent gazette] | ||
B06T | Formal requirements before examination [chapter 6.20 patent gazette] | ||
B11E | Dismissal acc. art. 34 of ipl - requirements for examination incomplete | ||
B11T | Dismissal of application maintained [chapter 11.20 patent gazette] |