BRPI0919772A2 - dispositivo de resconstituição de um sinal de relógio de um sinal série em banda de base e sistema de transmissão de dados digitais - Google Patents

dispositivo de resconstituição de um sinal de relógio de um sinal série em banda de base e sistema de transmissão de dados digitais

Info

Publication number
BRPI0919772A2
BRPI0919772A2 BRPI0919772A BRPI0919772A BRPI0919772A2 BR PI0919772 A2 BRPI0919772 A2 BR PI0919772A2 BR PI0919772 A BRPI0919772 A BR PI0919772A BR PI0919772 A BRPI0919772 A BR PI0919772A BR PI0919772 A2 BRPI0919772 A2 BR PI0919772A2
Authority
BR
Brazil
Prior art keywords
data transmission
transmission system
digital data
serial signal
signal clock
Prior art date
Application number
BRPI0919772A
Other languages
English (en)
Inventor
François Guillot
Original Assignee
Sagem Defense Securite
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sagem Defense Securite filed Critical Sagem Defense Securite
Publication of BRPI0919772A2 publication Critical patent/BRPI0919772A2/pt

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
BRPI0919772A 2008-10-13 2009-10-13 dispositivo de resconstituição de um sinal de relógio de um sinal série em banda de base e sistema de transmissão de dados digitais BRPI0919772A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0856916A FR2937203B1 (fr) 2008-10-13 2008-10-13 Dispositif de reconstitution de l'horloge d'un signal nrz et systeme de transmissoin associe.
PCT/EP2009/063345 WO2010043614A1 (fr) 2008-10-13 2009-10-13 Dispositif de reconstitution de l'horloge d'un signal nrz, et systeme de transmission associe

Publications (1)

Publication Number Publication Date
BRPI0919772A2 true BRPI0919772A2 (pt) 2015-12-08

Family

ID=40677532

Family Applications (1)

Application Number Title Priority Date Filing Date
BRPI0919772A BRPI0919772A2 (pt) 2008-10-13 2009-10-13 dispositivo de resconstituição de um sinal de relógio de um sinal série em banda de base e sistema de transmissão de dados digitais

Country Status (8)

Country Link
US (1) US8781046B2 (pt)
EP (1) EP2345161B1 (pt)
CN (1) CN102187580B (pt)
BR (1) BRPI0919772A2 (pt)
CA (1) CA2740251A1 (pt)
FR (1) FR2937203B1 (pt)
RU (1) RU2011117100A (pt)
WO (1) WO2010043614A1 (pt)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2481695C1 (ru) * 2011-12-28 2013-05-10 Российская Федерация, от имени которой выступает Государственная корпорация по атомной энергии "Росатом" - Госкорпорация "Росатом" Устройство термокомпенсации кварцевого генератора
US9363071B2 (en) 2013-03-07 2016-06-07 Qualcomm Incorporated Circuit to recover a clock signal from multiple wire data signals that changes state every state cycle and is immune to data inter-lane skew as well as data state transition glitches
US9374216B2 (en) 2013-03-20 2016-06-21 Qualcomm Incorporated Multi-wire open-drain link with data symbol transition based clocking
US9313058B2 (en) * 2013-03-07 2016-04-12 Qualcomm Incorporated Compact and fast N-factorial single data rate clock and data recovery circuits
US9735948B2 (en) 2013-10-03 2017-08-15 Qualcomm Incorporated Multi-lane N-factorial (N!) and other multi-wire communication systems
US9755818B2 (en) 2013-10-03 2017-09-05 Qualcomm Incorporated Method to enhance MIPI D-PHY link rate with minimal PHY changes and no protocol changes
US9203599B2 (en) 2014-04-10 2015-12-01 Qualcomm Incorporated Multi-lane N-factorial (N!) and other multi-wire communication systems
US9490964B2 (en) * 2014-11-26 2016-11-08 Qualcomm Incorporated Symbol transition clocking clock and data recovery to suppress excess clock caused by symbol glitch during stable symbol period
US10044358B2 (en) * 2015-12-21 2018-08-07 Texas Instruments Incorporated Loop filter with active discrete-level loop filter capacitor in a voltage controlled oscillator
CN116743158B (zh) * 2023-08-15 2023-11-07 慷智集成电路(上海)有限公司 提取输入信号频率相位的方法及数字信号传输系统

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5895430A (ja) * 1981-12-02 1983-06-07 Matsushita Electric Ind Co Ltd フェ−ズ・ロックド・ル−プ回路
JP2669059B2 (ja) * 1989-06-16 1997-10-27 松下電器産業株式会社 フェーズ・ロックド・ループ回路
US5127026A (en) 1990-04-05 1992-06-30 Gazelle Microcircuits, Inc. Circuit and method for extracting clock signal from a serial data stream
JPH04260239A (ja) * 1991-02-15 1992-09-16 Nec Corp タイミング抽出回路
US5164966A (en) 1991-03-07 1992-11-17 The Grass Valley Group, Inc. Nrz clock and data recovery system employing phase lock loop
JP3141760B2 (ja) * 1995-12-06 2001-03-05 ヤマハ株式会社 デジタルｐｌｌ回路
US20030179842A1 (en) * 2002-03-22 2003-09-25 Kane Michael G. Digital pattern sequence generator
US7102447B2 (en) * 2004-05-04 2006-09-05 Telefonaktiebolaget L M Ericsson (Publ) XO-buffer robust to interference
US7362185B1 (en) * 2005-01-27 2008-04-22 Cypress Semiconductor Corporation Analog based, state machine controlled, frequency smooth switching method for frequency timing generators
JP2007006307A (ja) * 2005-06-27 2007-01-11 Oki Electric Ind Co Ltd 無線装置
JP2009207035A (ja) * 2008-02-29 2009-09-10 Oki Electric Ind Co Ltd 符号分割多重通信システム

Also Published As

Publication number Publication date
FR2937203A1 (fr) 2010-04-16
CN102187580A (zh) 2011-09-14
RU2011117100A (ru) 2012-11-20
US20110249781A1 (en) 2011-10-13
EP2345161A1 (fr) 2011-07-20
CN102187580B (zh) 2015-03-18
CA2740251A1 (fr) 2010-04-22
EP2345161B1 (fr) 2019-02-20
FR2937203B1 (fr) 2011-03-18
WO2010043614A1 (fr) 2010-04-22
US8781046B2 (en) 2014-07-15

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Legal Events

Date Code Title Description
B11A Dismissal acc. art.33 of ipl - examination not requested within 36 months of filing
B11Y Definitive dismissal - extension of time limit for request of examination expired [chapter 11.1.1 patent gazette]