BRPI0608750A2 - método e sistema emitir e processar instruções superescalar e vliw misturadas - Google Patents

método e sistema emitir e processar instruções superescalar e vliw misturadas

Info

Publication number
BRPI0608750A2
BRPI0608750A2 BRPI0608750-7A BRPI0608750A BRPI0608750A2 BR PI0608750 A2 BRPI0608750 A2 BR PI0608750A2 BR PI0608750 A BRPI0608750 A BR PI0608750A BR PI0608750 A2 BRPI0608750 A2 BR PI0608750A2
Authority
BR
Brazil
Prior art keywords
instructions
mixed
executable
parallel
instruction
Prior art date
Application number
BRPI0608750-7A
Other languages
English (en)
Inventor
Muhammad Ahmed
Erich Plondke
Lucian Codrescu
William C Anderson
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BRPI0608750A2 publication Critical patent/BRPI0608750A2/pt
Publication of BRPI0608750B1 publication Critical patent/BRPI0608750B1/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Image Processing (AREA)
  • Multi Processors (AREA)

Abstract

MéTODO E SISTEMA PARA EMITIR E PROCESSAR INSTRUçõES SUPERESCALAR E VLIW MISTURADAS. São descritas técnicas para processar transmissões em um sistema de comunicação (por exemplo, CDMA). Um método e um sistema para emitir e executar instruções de estrutura misturadas em um processador de sinais digitais de múltipla emissão que recebe, em uma listagem de instruções misturadas, uma pluralidade de instruções de processador de sinais digitais. A pluralidade de instruções de processador de sinais digitais inclui uma pluralidade de instruções executáveis em paralelo (por exemplo, instruções VLIW ou pacotes de instruções) misturadas entre uma pluralidade de instruções executáveis em série (por exemplo, instruções superescalares) . As instruções executáveis em série estão associadas por meio de várias dependências de instruções. O método e o sistema adicionalmente identificam na listagem de instruções misturadas a pluralidade de instruções executáveis em paralelo. Uma vez identificadas, as instruções executáveis em paralelo são inicialmente executadas em paralelo desprezando-se qualquer ordem relativa de tais instruções na listagem de instruções misturadas. Então, as instruções executáveis em série são executadas serialmente de acordo com as várias dependências de instruções.
BRPI0608750-7A 2005-03-29 2006-03-28 "método e sistema para emitir e processar instruções superescalar e vliw misturadas" BRPI0608750B1 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/093,375 US7590824B2 (en) 2005-03-29 2005-03-29 Mixed superscalar and VLIW instruction issuing and processing method and system
US11/093,375 2005-03-29
PCT/US2006/011646 WO2006105295A2 (en) 2005-03-29 2006-03-28 Mixed superscalar and vliw instruction issuing and processing method and system

Publications (2)

Publication Number Publication Date
BRPI0608750A2 true BRPI0608750A2 (pt) 2010-01-26
BRPI0608750B1 BRPI0608750B1 (pt) 2018-01-16

Family

ID=36607594

Family Applications (1)

Application Number Title Priority Date Filing Date
BRPI0608750-7A BRPI0608750B1 (pt) 2005-03-29 2006-03-28 "método e sistema para emitir e processar instruções superescalar e vliw misturadas"

Country Status (5)

Country Link
US (1) US7590824B2 (pt)
KR (2) KR101253155B1 (pt)
BR (1) BRPI0608750B1 (pt)
IL (1) IL186137A0 (pt)
WO (1) WO2006105295A2 (pt)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8713286B2 (en) * 2005-04-26 2014-04-29 Qualcomm Incorporated Register files for a digital signal processor operating in an interleaved multi-threaded environment
US7370176B2 (en) * 2005-08-16 2008-05-06 International Business Machines Corporation System and method for high frequency stall design
GB2430773A (en) * 2005-10-03 2007-04-04 Advanced Risc Mach Ltd Alignment of variable length program instructions
US7725690B2 (en) * 2007-02-13 2010-05-25 Advanced Micro Devices, Inc. Distributed dispatch with concurrent, out-of-order dispatch
US8578387B1 (en) 2007-07-31 2013-11-05 Nvidia Corporation Dynamic load balancing of instructions for execution by heterogeneous processing engines
US9304775B1 (en) * 2007-11-05 2016-04-05 Nvidia Corporation Dispatching of instructions for execution by heterogeneous processing engines
EP2335149A1 (en) 2008-09-08 2011-06-22 Bridgeco, Inc. Very long instruction word processor with multiple data queues
US20110022821A1 (en) * 2009-03-09 2011-01-27 Yunsi Fei System and Methods to Improve Efficiency of VLIW Processors
JP2010257199A (ja) * 2009-04-24 2010-11-11 Renesas Electronics Corp プロセッサ及びプロセッサにおける命令発行の制御方法
JP2011138308A (ja) * 2009-12-28 2011-07-14 Sony Corp プロセッサ、コプロセッサ、情報処理システムおよびそれらにおける制御方法
US9678754B2 (en) * 2010-03-03 2017-06-13 Qualcomm Incorporated System and method of processing hierarchical very long instruction packets
US8804764B2 (en) 2010-12-21 2014-08-12 International Business Machines Corporation Data path for data extraction from streaming data
US20120198213A1 (en) * 2011-01-31 2012-08-02 International Business Machines Corporation Packet handler including plurality of parallel action machines
KR102210997B1 (ko) 2014-03-12 2021-02-02 삼성전자주식회사 Vliw 명령어를 처리하는 방법 및 장치와 vliw 명령어를 처리하기 위한 명령어를 생성하는 방법 및 장치
EP4243374A4 (en) * 2020-12-04 2024-04-10 Samsung Electronics Co., Ltd. METHOD AND APPARATUS FOR PERFORMING A RADIO ACCESS NETWORK FUNCTION
US11855831B1 (en) 2022-06-10 2023-12-26 T-Mobile Usa, Inc. Enabling an operator to resolve an issue associated with a 5G wireless telecommunication network using AR glasses

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4901307A (en) * 1986-10-17 1990-02-13 Qualcomm, Inc. Spread spectrum multiple access communication system using satellite or terrestrial repeaters
EP0454985B1 (en) * 1990-05-04 1996-12-18 International Business Machines Corporation Scalable compound instruction set machine architecture
US5295249A (en) * 1990-05-04 1994-03-15 International Business Machines Corporation Compounding preprocessor for cache for identifying multiple instructions which may be executed in parallel
US5103459B1 (en) * 1990-06-25 1999-07-06 Qualcomm Inc System and method for generating signal waveforms in a cdma cellular telephone system
JPH10232779A (ja) 1997-01-24 1998-09-02 Texas Instr Inc <Ti> 命令並列処理方法及び装置
US6453407B1 (en) * 1999-02-10 2002-09-17 Infineon Technologies Ag Configurable long instruction word architecture and instruction set
JP2004355845A (ja) * 2003-05-27 2004-12-16 Mitsuba Corp 電磁継電器
US20060206902A1 (en) * 2005-03-14 2006-09-14 Sujat Jamil Variable interleaved multithreaded processor method and system
US7917907B2 (en) * 2005-03-23 2011-03-29 Qualcomm Incorporated Method and system for variable thread allocation and switching in a multithreaded processor
US7526633B2 (en) * 2005-03-23 2009-04-28 Qualcomm Incorporated Method and system for encoding variable length packets with variable instruction sizes

Also Published As

Publication number Publication date
US20060224862A1 (en) 2006-10-05
WO2006105295A3 (en) 2007-02-08
WO2006105295A2 (en) 2006-10-05
IL186137A0 (en) 2008-01-20
US7590824B2 (en) 2009-09-15
KR20100087409A (ko) 2010-08-04
KR101253155B1 (ko) 2013-04-10
BRPI0608750B1 (pt) 2018-01-16
KR20070116924A (ko) 2007-12-11

Similar Documents

Publication Publication Date Title
BRPI0608750A2 (pt) método e sistema emitir e processar instruções superescalar e vliw misturadas
ATE511674T1 (de) Verfahren und system zur auflösung gleichzeitig vorgegebener verzweigungsinstruktionen
TW200713036A (en) Selecting multiple threads for substantially concurrent processing
BR0311175A (pt) Processo e sistema de reagente com complexo de enzima-coenzima não regenerável
TW200636581A (en) Methods and apparatus for instruction set emulation
SG193006A1 (en) Interrogatory cell-based assays and uses thereof
BRPI0509110A8 (pt) Método e dispositivo para processar um sinal estéreo, aparelhos codificador e decodificador, e, sistema de áudio
ATE517192T1 (de) Verfahren zur isolierung von zellen
ATE512228T1 (de) Induzierbare expressionssysteme
TW200602971A (en) A method and system to provide user-level multithreading
WO2008093098A3 (en) Methods for indexing samples and sequencing multiple nucleotide templates
MX2009004986A (es) Metodos de tratamiento de anemia hemolitica.
BR112016016916A8 (pt) uso de um anticorpo que se liga à calicreína plasmática ativa para tratamento de angiodema hereditário (hae)
EA201791850A1 (ru) Борсодержащие малые молекулы
WO2006113420A3 (en) System and method wherein conditional instructions unconditionally provide output
BR112017018365A2 (pt) uso de lavagens alcalinas durante cromatografia para remoção de impurezas
BR112014027819A2 (pt) processo e aparelho de granulação de ureia com sistema de depuração
NO20076391L (no) Sammensetninger og metoder for behandling av tilstander relatert til efrinsignaler med cupredoxin
BR112016006312A2 (pt) método e kit para determinar a presença ou ausência de staphylococcus aureus resistente à meticilina em uma amostra biológica
WO2011086473A3 (en) Hardware virtualization for media processing
NO20084320L (no) Antistoffer mot EGFL7 og fremgangsmater for anvendelse av disse
WO2006083046A3 (en) Methods and apparatus for providing a task change application programming interface
TW200506718A (en) Multi-pipe dispatch and execution of complex instructions in a superscalar processor
JP2012521047A5 (pt)
BRPI0604502A (pt) controles de ensino de metilação de gene

Legal Events

Date Code Title Description
B07A Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]