BR8603483A - Processo para minimizar a distorcao em substratos de ceramica com camadas multiplas e substrato resultante - Google Patents

Processo para minimizar a distorcao em substratos de ceramica com camadas multiplas e substrato resultante

Info

Publication number
BR8603483A
BR8603483A BR8603483A BR8603483A BR8603483A BR 8603483 A BR8603483 A BR 8603483A BR 8603483 A BR8603483 A BR 8603483A BR 8603483 A BR8603483 A BR 8603483A BR 8603483 A BR8603483 A BR 8603483A
Authority
BR
Brazil
Prior art keywords
multiple layers
ceramic substrates
resulting substrate
minimize distortion
distortion
Prior art date
Application number
BR8603483A
Other languages
English (en)
Inventor
David W Boss
Derry Jay Dubetsky
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of BR8603483A publication Critical patent/BR8603483A/pt

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H01L21/4807—Ceramic parts
    • C—CHEMISTRY; METALLURGY
    • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B35/00—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products
    • C04B35/622—Forming processes; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products
    • C04B35/64—Burning or sintering processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0191—Dielectric layers wherein the thickness of the dielectric plays an important role
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09036—Recesses or grooves in insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/063—Lamination of preperforated insulating layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Inorganic Chemistry (AREA)
  • Materials Engineering (AREA)
  • Structural Engineering (AREA)
  • Organic Chemistry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
BR8603483A 1985-08-07 1986-07-24 Processo para minimizar a distorcao em substratos de ceramica com camadas multiplas e substrato resultante BR8603483A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/763,389 US4677254A (en) 1985-08-07 1985-08-07 Process for minimizing distortion in multilayer ceramic substrates and the intermediate unsintered green ceramic substrate produced thereby

Publications (1)

Publication Number Publication Date
BR8603483A true BR8603483A (pt) 1987-03-04

Family

ID=25067720

Family Applications (1)

Application Number Title Priority Date Filing Date
BR8603483A BR8603483A (pt) 1985-08-07 1986-07-24 Processo para minimizar a distorcao em substratos de ceramica com camadas multiplas e substrato resultante

Country Status (7)

Country Link
US (1) US4677254A (pt)
EP (1) EP0212124B1 (pt)
JP (1) JPS6235659A (pt)
KR (1) KR900001088B1 (pt)
BR (1) BR8603483A (pt)
CA (1) CA1232978A (pt)
DE (1) DE3671580D1 (pt)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63240096A (ja) * 1987-03-27 1988-10-05 富士通株式会社 グリ−ンシ−ト多層法
JPH065656B2 (ja) * 1988-02-19 1994-01-19 株式会社村田製作所 セラミック積層体の製造方法
DE68929020T2 (de) 1989-04-04 1999-11-25 Murata Mfg. Co., Ltd. Herstellungsprozess für ein keramisches mehrschichtiges Substrat
DE69106345T2 (de) * 1990-01-18 1995-05-18 Du Pont Verfahren zur verminderung des schrumpfens beim brennen von keramischen grünkörpern.
US5283104A (en) * 1991-03-20 1994-02-01 International Business Machines Corporation Via paste compositions and use thereof to form conductive vias in circuitized ceramic substrates
US5153050A (en) * 1991-08-27 1992-10-06 Johnston James A Component of printed circuit boards
US5282312A (en) * 1991-12-31 1994-02-01 Tessera, Inc. Multi-layer circuit construction methods with customization features
JPH05219729A (ja) * 1992-02-07 1993-08-27 Sony Corp 直流電源装置
US5315485A (en) * 1992-09-29 1994-05-24 Mcnc Variable size capture pads for multilayer ceramic substrates and connectors therefor
TW276356B (pt) * 1994-06-24 1996-05-21 Ibm
US5671116A (en) * 1995-03-10 1997-09-23 Lam Research Corporation Multilayered electrostatic chuck and method of manufacture thereof
US6288347B1 (en) * 1997-05-30 2001-09-11 Kyocera Corporation Wiring board for flip-chip-mounting
US6129998A (en) * 1998-04-10 2000-10-10 R.E. Service Company, Inc. Copper/steel laminated sheet for use in manufacturing printed circuit boards
US6129990A (en) * 1998-04-10 2000-10-10 R. E. Service Company, Inc. Copper/steel laminated sheet for use in manufacturing printed circuit boards
US6355360B1 (en) 1998-04-10 2002-03-12 R.E. Service Company, Inc. Separator sheet laminate for use in the manufacture of printed circuit boards
US6127051A (en) * 1998-04-10 2000-10-03 R. E. Service Company, Inc. Copper/steel laminated sheet for use in manufacturing printed circuit boards
JP3758442B2 (ja) * 1999-02-23 2006-03-22 株式会社村田製作所 積層セラミックコンデンサの製造方法
KR100711008B1 (ko) * 1999-12-15 2007-04-24 고등기술연구원연구조합 혼합형 세라믹 모듈 패키지 제작방법
US6607620B2 (en) * 2001-01-08 2003-08-19 International Business Machines Corporation Greensheet carriers and processing thereof
US6562169B2 (en) * 2001-01-17 2003-05-13 International Business Machines Corporation Multi-level web structure in use for thin sheet processing
US6783860B1 (en) 2001-05-11 2004-08-31 R. E. Service Company, Inc. Laminated entry and exit material for drilling printed circuit boards
US6483690B1 (en) 2001-06-28 2002-11-19 Lam Research Corporation Ceramic electrostatic chuck assembly and method of making
US6627020B2 (en) * 2001-08-31 2003-09-30 International Business Machines Corporation Method for sinter distortion control
KR20050012916A (ko) * 2003-07-25 2005-02-02 삼성전기주식회사 절연기판의 제조방법
TWI247551B (en) 2003-08-12 2006-01-11 Ngk Insulators Ltd Method of manufacturing electrical resistance heating element
JP4421910B2 (ja) * 2004-01-29 2010-02-24 日本碍子株式会社 熱処理用トレー及びそれを用いたセラミック製品の製造方法
US20070227641A1 (en) * 2006-04-04 2007-10-04 Skamser Daniel J Flowable compensation layer for multilayer devices
EP2191701B1 (en) 2007-09-28 2013-03-20 Tri-Star Laminates, Inc. Entry sheet, method of manufacturing thereof and methods for drilling holes in printed circuit boards

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3770529A (en) * 1970-08-25 1973-11-06 Ibm Method of fabricating multilayer circuits
US3879509A (en) * 1971-09-07 1975-04-22 Gilbert James Elderbaum Method of producing thin ceramic sheets with minimal distortion
JPS5328266A (en) * 1976-08-13 1978-03-16 Fujitsu Ltd Method of producing multilayer ceramic substrate
US4336088A (en) * 1980-06-30 1982-06-22 International Business Machines Corp. Method of fabricating an improved multi-layer ceramic substrate

Also Published As

Publication number Publication date
EP0212124B1 (en) 1990-05-23
KR870002751A (ko) 1987-04-06
JPH0142155B2 (pt) 1989-09-11
US4677254A (en) 1987-06-30
JPS6235659A (ja) 1987-02-16
CA1232978A (en) 1988-02-16
KR900001088B1 (en) 1990-02-26
EP0212124A1 (en) 1987-03-04
DE3671580D1 (de) 1990-06-28

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