BR112023024495A2 - Avaliação e deslocamento do envelhecimento de dispositivo de circuito - Google Patents

Avaliação e deslocamento do envelhecimento de dispositivo de circuito

Info

Publication number
BR112023024495A2
BR112023024495A2 BR112023024495A BR112023024495A BR112023024495A2 BR 112023024495 A2 BR112023024495 A2 BR 112023024495A2 BR 112023024495 A BR112023024495 A BR 112023024495A BR 112023024495 A BR112023024495 A BR 112023024495A BR 112023024495 A2 BR112023024495 A2 BR 112023024495A2
Authority
BR
Brazil
Prior art keywords
replica
output
circuit
receivers
displacement
Prior art date
Application number
BR112023024495A
Other languages
English (en)
Inventor
Patrick Isakanian
Satish Krishnamoorthy
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112023024495A2 publication Critical patent/BR112023024495A2/pt

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
    • G01R31/2836—Fault-finding or characterising
    • G01R31/2849—Environmental or reliability testing, e.g. burn-in or validation tests
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2642—Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Environmental & Geological Engineering (AREA)
  • Logic Circuits (AREA)
  • Monitoring And Testing Of Transmission In General (AREA)
  • Length Measuring Devices With Unspecified Measuring Means (AREA)
  • Measurement Of Length, Angles, Or The Like Using Electric Or Magnetic Means (AREA)

Abstract

avaliação e deslocamento do envelhecimento de dispositivo de circuito. um aspecto se refere a um aparelho que inclui um conjunto de um ou mais receptores; um primeiro circuito de réplica é uma réplica substancial de pelo menos uma parte de um dos conjuntos de um ou mais receptores; um primeiro circuito de controle gera um sinal de saída seletivamente acoplado a uma entrada do primeiro circuito de réplica; um segundo circuito de réplica é uma réplica substancial de pelo menos uma parte de um dos conjuntos de um ou mais receptores; um comparador que inclui uma primeira entrada acoplada a uma primeira saída do primeiro circuito de réplica, uma segunda entrada acoplada a uma segunda saída do segundo circuito de réplica e uma saída; e um segundo circuito de controle que inclui uma entrada acoplada à saída do comparador e uma saída acoplada ao primeiro circuito de réplica e ao conjunto de um ou mais receptores.
BR112023024495A 2021-06-04 2022-04-28 Avaliação e deslocamento do envelhecimento de dispositivo de circuito BR112023024495A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US17/339,195 US11381238B1 (en) 2021-06-04 2021-06-04 Circuit device aging assessment and compensation
PCT/US2022/026804 WO2022256100A1 (en) 2021-06-04 2022-04-28 Circuit device aging assessment and compensation

Publications (1)

Publication Number Publication Date
BR112023024495A2 true BR112023024495A2 (pt) 2024-02-15

Family

ID=82020974

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112023024495A BR112023024495A2 (pt) 2021-06-04 2022-04-28 Avaliação e deslocamento do envelhecimento de dispositivo de circuito

Country Status (7)

Country Link
US (2) US11381238B1 (pt)
EP (1) EP4348832A1 (pt)
KR (1) KR20230169387A (pt)
CN (1) CN117223219A (pt)
BR (1) BR112023024495A2 (pt)
TW (1) TW202322562A (pt)
WO (1) WO2022256100A1 (pt)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11381238B1 (en) 2021-06-04 2022-07-05 Qualcomm Incorporated Circuit device aging assessment and compensation

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3953041B2 (ja) * 2004-03-31 2007-08-01 日本電気株式会社 出力バッファ回路および半導体集積回路
US7338817B2 (en) * 2005-03-31 2008-03-04 Intel Corporation Body bias compensation for aged transistors
US7437620B2 (en) 2005-11-30 2008-10-14 International Business Machines Corporation Method and system for extending the useful life of another system
US8081003B2 (en) 2009-02-02 2011-12-20 Infineon Technologies Ag Circuit arrangement with a test circuit and a reference circuit and corresponding method
JP2011040983A (ja) * 2009-08-11 2011-02-24 Renesas Electronics Corp 半導体集積回路、半導体記憶装置、及びインピーダンス調整方法
US20110181315A1 (en) * 2010-01-25 2011-07-28 Broadcom Corporation Adaptive Device Aging Monitoring and Compensation
US8762804B2 (en) * 2012-08-06 2014-06-24 Texas Instruments Incorporated Error prediction in logic and memory devices
WO2014072769A1 (en) 2012-11-07 2014-05-15 Freescale Semiconductor, Inc. Method and Apparatus for Maintaining an Accurate I/O Calibration cell
US9647618B1 (en) * 2016-03-30 2017-05-09 Qualcomm Incorporated System and method for controlling common mode voltage via replica circuit and feedback control
FR3054885B1 (fr) 2016-08-03 2018-09-07 Stmicroelectronics (Crolles 2) Sas Procede d'estimation d'un profil d'exploitation d'un circuit integre d'un systeme sur puce, et systeme sur puce correspondant
WO2018090334A1 (en) * 2016-11-18 2018-05-24 Texas Instruments Incorporated High voltage level shifter with short propagation delay
US10554209B2 (en) 2018-03-22 2020-02-04 Intel Corporation Adaptive aging tolerant apparatus
CN110456256B (zh) * 2019-09-06 2021-07-13 电子科技大学 基于备份电路的原位老化传感器及老化监测方法
US11381238B1 (en) 2021-06-04 2022-07-05 Qualcomm Incorporated Circuit device aging assessment and compensation

Also Published As

Publication number Publication date
US20220393679A1 (en) 2022-12-08
US11381238B1 (en) 2022-07-05
EP4348832A1 (en) 2024-04-10
KR20230169387A (ko) 2023-12-15
TW202322562A (zh) 2023-06-01
CN117223219A (zh) 2023-12-12
WO2022256100A1 (en) 2022-12-08
US11637553B2 (en) 2023-04-25

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