BR112023013647A2 - Célula de bits de computação em memória com operação de gravação capacitivamente acoplada - Google Patents

Célula de bits de computação em memória com operação de gravação capacitivamente acoplada

Info

Publication number
BR112023013647A2
BR112023013647A2 BR112023013647A BR112023013647A BR112023013647A2 BR 112023013647 A2 BR112023013647 A2 BR 112023013647A2 BR 112023013647 A BR112023013647 A BR 112023013647A BR 112023013647 A BR112023013647 A BR 112023013647A BR 112023013647 A2 BR112023013647 A2 BR 112023013647A2
Authority
BR
Brazil
Prior art keywords
bit
memory computing
bit cell
write operation
cross
Prior art date
Application number
BR112023013647A
Other languages
English (en)
Inventor
Ankit Srivastava
Sameer Wadhwa
Arash MIRHAJ Seyed
Xiaonan Chen
Zhongze Wang
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112023013647A2 publication Critical patent/BR112023013647A2/pt

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • General Health & Medical Sciences (AREA)
  • Molecular Biology (AREA)
  • Neurology (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)

Abstract

célula de bits de computação em memória com operação de gravação capacitivamente acoplada. é fornecida uma célula de bits de computação em memória que inclui um par de inversores de acoplamento cruzado para armazenar um bit armazenado. a célula de bits de computação em memória inclui uma porta lógica para multiplicar o bit armazenado com um bit de vetor de entrada. um nó de saída para a porta lógica se conecta a uma segunda placa de um capacitor. uma primeira placa do capacitor se conecta a uma linha de leitura de bit. um driver de gravação controla uma tensão de fonte de alimentação para os inversores de acoplamento cruzado, o primeiro comutador, e o segundo comutador para gravar capacitivamente o bit armazenado no par de inversores de acoplamento cruzado.
BR112023013647A 2021-01-19 2022-01-05 Célula de bits de computação em memória com operação de gravação capacitivamente acoplada BR112023013647A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US17/152,564 US11631455B2 (en) 2021-01-19 2021-01-19 Compute-in-memory bitcell with capacitively-coupled write operation
PCT/US2022/011345 WO2022159272A1 (en) 2021-01-19 2022-01-05 Compute-in-memory bitcell with capacitively-coupled write operation

Publications (1)

Publication Number Publication Date
BR112023013647A2 true BR112023013647A2 (pt) 2023-12-05

Family

ID=80445570

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112023013647A BR112023013647A2 (pt) 2021-01-19 2022-01-05 Célula de bits de computação em memória com operação de gravação capacitivamente acoplada

Country Status (8)

Country Link
US (1) US11631455B2 (pt)
EP (1) EP4281969A1 (pt)
JP (1) JP7408022B1 (pt)
KR (1) KR20230109787A (pt)
CN (1) CN116670763A (pt)
BR (1) BR112023013647A2 (pt)
TW (1) TW202234398A (pt)
WO (1) WO2022159272A1 (pt)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11538509B2 (en) 2021-03-17 2022-12-27 Qualcomm Incorporated Compute-in-memory with ternary activation

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4753534B2 (ja) 2003-12-26 2011-08-24 ルネサスエレクトロニクス株式会社 半導体記憶装置
US20060195631A1 (en) 2005-01-31 2006-08-31 Ramasubramanian Rajamani Memory buffers for merging local data from memory modules
US20140075091A1 (en) 2012-09-10 2014-03-13 Texas Instruments Incorporated Processing Device With Restricted Power Domain Wakeup Restore From Nonvolatile Logic Array
US9153314B2 (en) 2013-03-15 2015-10-06 Nvidia Corporation Ground-referenced single-ended memory interconnect
US9722828B2 (en) * 2015-09-23 2017-08-01 Qualcomm Incorporated Switch capacitor decision feedback equalizer with internal charge summation
JP2018129046A (ja) 2017-02-08 2018-08-16 株式会社半導体エネルギー研究所 Ａｉシステム
US11263522B2 (en) 2017-09-08 2022-03-01 Analog Devices, Inc. Analog switched-capacitor neural network
WO2019246064A1 (en) 2018-06-18 2019-12-26 The Trustees Of Princeton University Configurable in-memory computing engine, platform, bit cells and layouts therefore
US10642922B2 (en) 2018-09-28 2020-05-05 Intel Corporation Binary, ternary and bit serial compute-in-memory circuits
US11061646B2 (en) 2018-09-28 2021-07-13 Intel Corporation Compute in memory circuits with multi-Vdd arrays and/or analog multipliers
FR3086788B1 (fr) 2018-10-01 2020-11-20 Commissariat Energie Atomique Circuit memoire imc a cellules 6t
WO2020139895A1 (en) * 2018-12-24 2020-07-02 The Trustees Of Columbia University In The City Of New York Circuits and methods for in-memory computing
US10825510B2 (en) 2019-02-09 2020-11-03 Purdue Research Foundation Multi-bit dot product engine
US11755894B2 (en) 2019-04-09 2023-09-12 Cirrus Logic Inc. Computing circuitry for configuration and operation of cells and arrays comprising memristor elements
GB2583121B (en) 2019-04-17 2021-09-08 Surecore Ltd In memory computation
US10964356B2 (en) 2019-07-03 2021-03-30 Qualcomm Incorporated Compute-in-memory bit cell
US11758707B2 (en) * 2019-12-19 2023-09-12 Stmicroelectronics International N.V. SRAM cell layout including arrangement of multiple active regions and multiple gate regions
US11538509B2 (en) 2021-03-17 2022-12-27 Qualcomm Incorporated Compute-in-memory with ternary activation
CN113255904B (zh) * 2021-06-22 2021-09-24 中科院微电子研究所南京智能技术研究院 电压裕度增强型电容耦合存算一体单元、子阵列及装置

Also Published As

Publication number Publication date
JP7408022B1 (ja) 2024-01-04
US20220230679A1 (en) 2022-07-21
EP4281969A1 (en) 2023-11-29
US11631455B2 (en) 2023-04-18
CN116670763A (zh) 2023-08-29
JP2024504094A (ja) 2024-01-30
WO2022159272A1 (en) 2022-07-28
KR20230109787A (ko) 2023-07-20
TW202234398A (zh) 2022-09-01

Similar Documents

Publication Publication Date Title
US10355676B2 (en) Electronic circuit
BR112023013647A2 (pt) Célula de bits de computação em memória com operação de gravação capacitivamente acoplada
Agarwal et al. A 128× 128b high-speed wide-and match-line content addressable memory in 32nm CMOS
Islam et al. Variability aware low leakage reliable SRAM cell design technique
ES2540651R1 (es) Regulación de tensión de sub-dominio de procesador de gráficos
EP2118717A4 (en) MEMORY DEVICE WITH DIVIDED POWER SWITCH AND CORRESPONDING METHOD
Sachdeva et al. A Schmitt-trigger based low read power 12T SRAM cell
Vanama et al. Design of low power stable SRAM cell
Saini A stable and power efficient SRAM cell
Suthar et al. Leakage reduction in DT8T SRAM cell using body biasing technique
BR112023018130A2 (pt) Computação em memória com ativação ternária
Sreelakshmi et al. SRAM cell with improved stability and reduced leakage current for subthreshold region of operation
KR20090110551A (ko) 액티브 차지 펌프 회로, 이를 포함하는 고전원전압발생회로 및 반도체 장치
Kumar et al. A novel adiabatic SRAM cell implementation using split level charge recovery logic
Chaudhary et al. Design of low power stacked inverter based sram cell with improved write ability
US20150146470A1 (en) Write assist circuit for write disturbed memory cell
Tiwari et al. Highly robust asymmetrical 9T SRAM with trimode MTCOS technique
Kushwah et al. Reduction of leakage power & noise for DRAM design using sleep transistor technique
Nag et al. A novel NOR gate-based dynamic power gating technique in SRAM
Bhuvana et al. Content Addressable Memory performance Analysis using NAND Structure FinFET
Zackriya et al. Selective match-line energizer content addressable memory (SMLE-CAM)
Yu et al. Single-port 5t sram cell with improved write-ability and reduced standby leakage current
Irin et al. Process Variation's Effect on Various Threshold Voltage Assignments in 6T SRAM Designs Using 12nm FinFET Technology
Shedge et al. Different types of SRAM chips for power reduction: A survey
Akashe et al. Enhancement of Parameters for 7T SRAM Cell in Nanometer Era