BR112022025581A2 - Redução de demanda de potência para geração de imagem para visores - Google Patents

Redução de demanda de potência para geração de imagem para visores

Info

Publication number
BR112022025581A2
BR112022025581A2 BR112022025581A BR112022025581A BR112022025581A2 BR 112022025581 A2 BR112022025581 A2 BR 112022025581A2 BR 112022025581 A BR112022025581 A BR 112022025581A BR 112022025581 A BR112022025581 A BR 112022025581A BR 112022025581 A2 BR112022025581 A2 BR 112022025581A2
Authority
BR
Brazil
Prior art keywords
cpu
draw calls
power demand
circuit
calls
Prior art date
Application number
BR112022025581A
Other languages
English (en)
Inventor
Li Yunzhen
Wen Yanshan
Wang Hailong
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112022025581A2 publication Critical patent/BR112022025581A2/pt

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • A—HUMAN NECESSITIES
    • A63—SPORTS; GAMES; AMUSEMENTS
    • A63F—CARD, BOARD, OR ROULETTE GAMES; INDOOR GAMES USING SMALL MOVING PLAYING BODIES; VIDEO GAMES; GAMES NOT OTHERWISE PROVIDED FOR
    • A63F13/00—Video games, i.e. games using an electronically generated display having two or more dimensions
    • A63F13/50—Controlling the output signals based on the game progress
    • A63F13/52—Controlling the output signals based on the game progress involving aspects of the displayed game scene
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V10/00—Arrangements for image or video recognition or understanding
    • G06V10/70—Arrangements for image or video recognition or understanding using pattern recognition or machine learning
    • G06V10/74—Image or video pattern matching; Proximity measures in feature spaces
    • G06V10/761—Proximity, similarity or dissimilarity measures
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/399—Control of the bit-mapped memory using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/10—Special adaptations of display systems for operation with variable images
    • G09G2320/103—Detection of image changes, e.g. determination of an index representative of the image change
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/16—Determination of a pixel data signal depending on the signal applied in the previous frame
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/06—Use of more than one graphics processor to process data before displaying to one or more screens
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/08—Power processing, i.e. workload management for processors involved in display operations, such as CPUs or GPUs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/16—Calculation or use of calculated indices related to luminance levels in display data
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/18—Use of a frame buffer in a display terminal, inclusive of the display panel

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Multimedia (AREA)
  • Computer Graphics (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Computing Systems (AREA)
  • Artificial Intelligence (AREA)
  • Databases & Information Systems (AREA)
  • Evolutionary Computation (AREA)
  • General Health & Medical Sciences (AREA)
  • Medical Informatics (AREA)
  • Software Systems (AREA)
  • Health & Medical Sciences (AREA)
  • Human Computer Interaction (AREA)
  • General Engineering & Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Processing Or Creating Images (AREA)

Abstract

REDUÇÃO DE DEMANDA DE POTÊNCIA PARA GERAÇÃO DE IMAGEM PARA VISORES. Trata-se de redução de demanda de potência para geração de imagem para visores que saltam a renderização de quadros que são altamente similares com base em uma comparação de certos parâmetros associados a chamadas de desenho. Um primeiro conjunto de chamadas de desenho é recebido de um mecanismo de jogo por um circuito de unidade de processamento central (CPU) e, então, um segundo conjunto de chamadas de desenho é fornecido para o circuito de CPU. O circuito de CPU compara o segundo conjunto de chamadas de desenho ao primeiro conjunto de chamadas de desenho. Se houver uma alteração em pelo menos um parâmetro que excede um limite, então, o circuito de CPU envia o segundo conjunto de chamadas de desenho para um circuito de unidade de processamento gráfico (GPU) para renderização. Se, entretanto, a alteração nos parâmetros selecionados estiver abaixo do limite, então, o circuito de CPU envia uma imagem renderizada anterior para o visor para apresentação para o usuário, o que omite eficazmente o uso do circuito de GPU para aquele quadro.
BR112022025581A 2020-06-23 2020-06-23 Redução de demanda de potência para geração de imagem para visores BR112022025581A2 (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/097588 WO2021258274A1 (en) 2020-06-23 2020-06-23 Power demand reduction for image generation for displays

Publications (1)

Publication Number Publication Date
BR112022025581A2 true BR112022025581A2 (pt) 2023-01-03

Family

ID=79282638

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112022025581A BR112022025581A2 (pt) 2020-06-23 2020-06-23 Redução de demanda de potência para geração de imagem para visores

Country Status (7)

Country Link
US (1) US20230186872A1 (pt)
EP (1) EP4169012A4 (pt)
KR (1) KR20230025666A (pt)
CN (1) CN115699158A (pt)
BR (1) BR112022025581A2 (pt)
TW (1) TW202203003A (pt)
WO (1) WO2021258274A1 (pt)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115350479B (zh) * 2022-10-21 2023-01-31 腾讯科技（深圳）有限公司 渲染处理方法、装置、设备及介质
CN118038780A (zh) * 2022-11-01 2024-05-14 联发科技（新加坡）私人有限公司 改善图形性能的方法及其装置
CN115834874B (zh) * 2023-02-06 2023-04-28 武汉凌久微电子有限公司 一种用于gpu的显示带宽错误的实时监测方法及装置

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US6128026A (en) * 1998-05-04 2000-10-03 S3 Incorporated Double buffered graphics and video accelerator having a write blocking memory interface and method of doing the same
US8922565B2 (en) * 2007-11-30 2014-12-30 Qualcomm Incorporated System and method for using a secondary processor in a graphics system
US7861013B2 (en) * 2007-12-13 2010-12-28 Ati Technologies Ulc Display system with frame reuse using divided multi-connector element differential bus connector
US20110134120A1 (en) * 2009-12-07 2011-06-09 Smart Technologies Ulc Method and computing device for capturing screen images and for identifying screen image changes using a gpu
US8643658B2 (en) * 2009-12-30 2014-02-04 Intel Corporation Techniques for aligning frame data
US8941675B2 (en) * 2011-04-05 2015-01-27 Blackberry Limited Backing store memory management for rendering scrollable webpage subregions
CN103401941B (zh) * 2013-08-09 2017-02-08 广东威创视讯科技股份有限公司 一种gis场景信息处理方法、系统、节点机和服务端
US9760967B2 (en) * 2013-11-13 2017-09-12 Qualcomm Incorporated System and method of dynamically throttling CPU frequency for gaming workloads
US9934547B2 (en) * 2014-10-09 2018-04-03 Qualcomm Incorporated Method and system for reducing the number of draw commands issued to a graphics processing unit (GPU)
US9916634B2 (en) * 2015-06-12 2018-03-13 Intel Corporation Facilitating efficient graphics command generation and execution for improved graphics performance at computing devices
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Also Published As

Publication number Publication date
EP4169012A4 (en) 2024-01-17
TW202203003A (zh) 2022-01-16
US20230186872A1 (en) 2023-06-15
CN115699158A (zh) 2023-02-03
EP4169012A1 (en) 2023-04-26
KR20230025666A (ko) 2023-02-22
WO2021258274A1 (en) 2021-12-30

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