BR112019008074A2 - teste automatizado universal de sistemas integrados - Google Patents

teste automatizado universal de sistemas integrados

Info

Publication number
BR112019008074A2
BR112019008074A2 BR112019008074A BR112019008074A BR112019008074A2 BR 112019008074 A2 BR112019008074 A2 BR 112019008074A2 BR 112019008074 A BR112019008074 A BR 112019008074A BR 112019008074 A BR112019008074 A BR 112019008074A BR 112019008074 A2 BR112019008074 A2 BR 112019008074A2
Authority
BR
Brazil
Prior art keywords
test
interface
receive
computing device
corresponds
Prior art date
Application number
BR112019008074A
Other languages
English (en)
Other versions
BR112019008074B1 (pt
Inventor
Pernikár Ale?
Pavlák Jakub
Kyzlink Jiri
Krajicek Ondrej
Novotný Václav
Original Assignee
Y Soft Corp A S
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Y Soft Corp A S filed Critical Y Soft Corp A S
Publication of BR112019008074A2 publication Critical patent/BR112019008074A2/pt
Publication of BR112019008074B1 publication Critical patent/BR112019008074B1/pt

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31907—Modular tester, e.g. controlling and coordinating instruments in a bus based architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2273—Test methods
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
    • G01R31/2829—Testing of circuits in sensor or actuator systems
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
    • G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
    • G01R31/2836—Fault-finding or characterising
    • G01R31/2846—Fault-finding or characterising using hard- or software simulation or using knowledge-based systems, e.g. expert systems, artificial intelligence or interactive algorithms
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
    • G06F11/2635—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers using a storage for the test inputs, e.g. test ROM, script files

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Artificial Intelligence (AREA)
  • Health & Medical Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
  • Evolutionary Computation (AREA)
  • Medical Informatics (AREA)
  • User Interface Of Digital Computer (AREA)
  • Manipulator (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Debugging And Monitoring (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Analysing Materials By The Use Of Radiation (AREA)

Abstract

trata-se de um sistema e método para testar recursos de um sistema integrado. o sistema inclui um dispositivo de computação de baixa potência comunicativamente acoplado a uma interface de aplicativo de controle, uma interface de sensor e uma interface robótica. o dispositivo de computação de baixa potência pode receber sinais de sensor gerados durante um teste, fornecer dados de sensor que correspondem aos sinais de sensor, receber comandos para o teste, e fornecer instruções para movimento de um manipulador robótico que corresponde a pelo menos um dentre os comandos para o teste. o sistema também inclui um dispositivo de computação comunicativamente acoplado à interface de aplicativo de controle, uma interface de processamento de imagem e uma interface de banco de dados. o dispositivo de computação pode receber dados de sensor, receber dados de imagem que correspondem a imagens do sistema integrado capturado durante o teste, receber testes que podem ser realizados e fornecer comandos para o teste.
BR112019008074-0A 2016-10-20 2017-10-19 Sistema e método para testar um recurso de um sistema integrado BR112019008074B1 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201662410666P 2016-10-20 2016-10-20
US62/410,666 2016-10-20
PCT/EP2017/076802 WO2018073395A1 (en) 2016-10-20 2017-10-19 Universal automated testing of embedded systems

Publications (2)

Publication Number Publication Date
BR112019008074A2 true BR112019008074A2 (pt) 2019-07-02
BR112019008074B1 BR112019008074B1 (pt) 2023-08-15

Family

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Also Published As

Publication number Publication date
AU2017347687A1 (en) 2019-05-23
AU2023229503A1 (en) 2023-09-28
CN110226095A (zh) 2019-09-10
US20180113774A1 (en) 2018-04-26
WO2018073395A8 (en) 2019-06-20
RU2719474C1 (ru) 2020-04-17
US10997045B2 (en) 2021-05-04
EP3529626A1 (en) 2019-08-28
JP6845928B2 (ja) 2021-03-24
JP2023082189A (ja) 2023-06-13
WO2018073395A1 (en) 2018-04-26
JP2021108130A (ja) 2021-07-29
CN110226095B (zh) 2022-06-17
JP2020501221A (ja) 2020-01-16

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Legal Events

Date Code Title Description
B350 Update of information on the portal [chapter 15.35 patent gazette]
B06W Patent application suspended after preliminary examination (for patents with searches from other patent authorities) chapter 6.23 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 19/10/2017, OBSERVADAS AS CONDICOES LEGAIS