BR112018076404A8 - Mitigação de efeito de comprimento de difusão para células lógicas e posicionamento das mesmas - Google Patents

Mitigação de efeito de comprimento de difusão para células lógicas e posicionamento das mesmas

Info

Publication number
BR112018076404A8
BR112018076404A8 BR112018076404A BR112018076404A BR112018076404A8 BR 112018076404 A8 BR112018076404 A8 BR 112018076404A8 BR 112018076404 A BR112018076404 A BR 112018076404A BR 112018076404 A BR112018076404 A BR 112018076404A BR 112018076404 A8 BR112018076404 A8 BR 112018076404A8
Authority
BR
Brazil
Prior art keywords
diffusion
mitigation
transistor
positioning
diffusion length
Prior art date
Application number
BR112018076404A
Other languages
English (en)
Other versions
BR112018076404A2 (pt
Inventor
John Bowers Benjamin
Correale Anthony Jr
Della Rova Tracey
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112018076404A2 publication Critical patent/BR112018076404A2/pt
Publication of BR112018076404A8 publication Critical patent/BR112018076404A8/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/20—Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Architecture (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

Trata-se de sistemas e métodos relacionados às metodologias de posicionamento de célula para aprimorar o comprimento de difusão de transistores. Por exemplo, um primeiro transistor com um primeiro nó de difusão que é ligado por um primeiro corte de difusão é identificado em um layout de nível de transistor. O primeiro corte de difusão é substituído por uma primeira porta flutuante, e uma primeira célula de carga com uma primeira região de difusão de carga é adicionada para estender um comprimento de difusão do primeiro nó de difusão. Aumenta-se o comprimento de fios condutores de difusão para aprimorar a resistência de acionamento e desempenho do primeiro transistor.
BR112018076404A 2016-06-25 2017-06-05 Mitigação de efeito de comprimento de difusão para células lógicas e posicionamento das mesmas BR112018076404A8 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/193,003 2016-06-25
US15/193,003 US10282503B2 (en) 2016-06-25 2016-06-25 Mitigating length-of-diffusion effect for logic cells and placement thereof
PCT/US2017/035934 WO2017222795A1 (en) 2016-06-25 2017-06-05 Mitigating length-of-diffusion effect for logic cells and placement thereof

Publications (2)

Publication Number Publication Date
BR112018076404A2 BR112018076404A2 (pt) 2019-04-09
BR112018076404A8 true BR112018076404A8 (pt) 2023-01-31

Family

ID=59078193

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112018076404A BR112018076404A8 (pt) 2016-06-25 2017-06-05 Mitigação de efeito de comprimento de difusão para células lógicas e posicionamento das mesmas

Country Status (7)

Country Link
US (1) US10282503B2 (pt)
EP (1) EP3475855B1 (pt)
JP (1) JP6605764B2 (pt)
KR (1) KR102052145B1 (pt)
CN (1) CN109313671B (pt)
BR (1) BR112018076404A8 (pt)
WO (1) WO2017222795A1 (pt)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9761712B1 (en) * 2016-10-31 2017-09-12 International Business Machines Corporation Vertical transistors with merged active area regions
US10050028B2 (en) * 2016-11-28 2018-08-14 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device with reduced leakage current
US10331838B2 (en) * 2016-12-12 2019-06-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with fill cells
KR102285790B1 (ko) * 2017-07-04 2021-08-04 삼성전자 주식회사 필러 셀을 포함하는 집적 회로
US10741539B2 (en) * 2017-08-30 2020-08-11 Taiwan Semiconductor Manufacturing Co., Ltd. Standard cells and variations thereof within a standard cell library
KR102439861B1 (ko) * 2018-02-14 2022-09-02 삼성전자주식회사 반도체 칩을 제조하기 위한 전자 장치 및 방법
US10276554B1 (en) * 2018-06-14 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated standard cell structure
US11138360B2 (en) 2018-10-31 2021-10-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with filler cell region, method of generating layout diagram and system for same
US11030381B2 (en) * 2019-01-16 2021-06-08 Taiwan Semiconductor Manufacturing Co., Ltd. Leakage analysis on semiconductor device
US10885260B1 (en) * 2019-09-04 2021-01-05 International Business Machines Corporation Fin-based fill cell optimization

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6839882B2 (en) * 2001-06-01 2005-01-04 Virtual Silicon Technology, Inc. Method and apparatus for design of integrated circuits
US9035359B2 (en) * 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
JP2008118004A (ja) * 2006-11-07 2008-05-22 Nec Electronics Corp 半導体集積回路
US7895548B2 (en) 2007-10-26 2011-02-22 Synopsys, Inc. Filler cells for design optimization in a place-and-route system
JP5599395B2 (ja) * 2008-07-16 2014-10-01 テラ イノヴェイションズ インコーポレイテッド 動的アレイアーキテクチャにおけるセル位相整合及び配置の方法及びその実施
US8650020B1 (en) 2009-01-30 2014-02-11 Xilinx, Inc. Modeling second order effects for simulating transistor behavior
US8321828B2 (en) 2009-02-27 2012-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy fill to reduce shallow trench isolation (STI) stress variation on transistor performance
US8631366B2 (en) 2009-04-30 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit design using DFM-enhanced architecture
US9093995B2 (en) * 2013-05-29 2015-07-28 Qualcomm Incorporated Length-of-diffusion protected circuit and method of design
US9070551B2 (en) * 2013-06-18 2015-06-30 Qualcomm Incorporated Method and apparatus for a diffusion bridged cell library
US9570288B2 (en) * 2014-03-19 2017-02-14 Ecole Polytechnique Federale De Lausanne (Epfl) Method to fabricate FinFET sensors, in particular, FinFET sensors for ionic, chemical and biological applications on Si-Bulk

Also Published As

Publication number Publication date
EP3475855B1 (en) 2020-08-05
BR112018076404A2 (pt) 2019-04-09
JP6605764B2 (ja) 2019-11-13
KR20190021256A (ko) 2019-03-05
WO2017222795A1 (en) 2017-12-28
EP3475855A1 (en) 2019-05-01
CN109313671A (zh) 2019-02-05
KR102052145B1 (ko) 2019-12-04
CN109313671B (zh) 2023-08-18
JP2019519112A (ja) 2019-07-04
US10282503B2 (en) 2019-05-07
US20170371994A1 (en) 2017-12-28

Similar Documents

Publication Publication Date Title
BR112018076404A8 (pt) Mitigação de efeito de comprimento de difusão para células lógicas e posicionamento das mesmas
ECSP19090538A (es) Moléculas de anticuerpo que se unen a cd73 y usos de las mismas
CL2020001637A1 (es) Anticuerpos para lilrb2
BR112016024319A2 (pt) métodos para aumentar os níveis de hemácias e tratar anemia falciforme
SV2017005461A (es) Benzamidas sustituidas con 1,3-tiazol-2-ilo
BR112018001015A2 (pt) dispositivo e método para conectar regiões de porta separadas usando um corte de porta
UY35417A (es) Anticuerpos dirigidos contra il-33 y sus usos.
CL2016001636A1 (es) Mezclas fungicidas sinérgicas para el control fúngico en cereales
DE112017002457T8 (de) Konfigurierbarer und leistungsoptimierter integrierter Gate-Treiber für USB-Stromlieferung und SoCs vom Typ C
CR20150376A (es) Compuestos sustituidos de pirrolopirimidina, compuestos de los mismos y metodos de tratamiento con los mismos
BR112017027332A2 (pt) composições tópicas que compreendem um corticosteróide e um retinóide para tratar psoríase.
NI201600071A (es) Compuestos de inhibidor de autotaxina
BR112017005522A2 (pt) abas de aplicação heterogênea
BR112017003660A2 (pt) conjuntos de armazenamento de dados escaláveis
BR112017017345A2 (pt) camadas de metal para uma célula de bit de três portas
CL2017002521A1 (es) Paginación de sistema de procesamiento de eventos.
BR112017028287A2 (pt) Combinação do inibidor hdac e anticorpido anti-pd- l1 para o tratamento do câncer
DK3908988T3 (da) Kvantecomputerarkitektur baseret på multiqubit-gates
BR112017019352A2 (pt) composições tópicas comprimidas a corticosteróide aplicações relacionadas
MX2020003783A (es) Moleculas de anticuerpo de cd138 y sus usos.
NI201600070A (es) Inhibidores tetracíclicos de autotaxina
CO2019006911A2 (es) Composiciones cannabinoides novedosas y métodos para tratar la epilepsia infantil.
BR112015016671A2 (pt) dispositivo semicondutor que tem recursos para evitar engenharia reversa
BR112016021066A2 (pt) anticorpos humanizados com estabilidade aumentada
CL2018000882A1 (es) Puertas estilo shaker con núcleo sólido y métodos para la fabricación de las mismas

Legal Events

Date Code Title Description
B350 Update of information on the portal [chapter 15.35 patent gazette]
B06W Patent application suspended after preliminary examination (for patents with searches from other patent authorities) chapter 6.23 patent gazette]
B15K Others concerning applications: alteration of classification

Free format text: A CLASSIFICACAO ANTERIOR ERA: G06F 17/50

Ipc: G06F 30/392 (2020.01), G06F 30/398 (2020.01), H01L

B07A Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]