BR112018070131A2 - colapso de energia gerenciado por hardware e ativação de clock para unidades de gerenciamento de memória e redes de memória virtual distribuídas - Google Patents

colapso de energia gerenciado por hardware e ativação de clock para unidades de gerenciamento de memória e redes de memória virtual distribuídas

Info

Publication number
BR112018070131A2
BR112018070131A2 BR112018070131A BR112018070131A BR112018070131A2 BR 112018070131 A2 BR112018070131 A2 BR 112018070131A2 BR 112018070131 A BR112018070131 A BR 112018070131A BR 112018070131 A BR112018070131 A BR 112018070131A BR 112018070131 A2 BR112018070131 A2 BR 112018070131A2
Authority
BR
Brazil
Prior art keywords
dvm
network
hardware
target
distributed virtual
Prior art date
Application number
BR112018070131A
Other languages
English (en)
Inventor
Rychlik Bohuslav
Denis Bernard Avoinne Christophe
Ranjan Pal Dipti
Edward Podaima Jason
Prakash Subramaniam Ganasan Jaya
Somasundaram Manokanthan
Ramkumar Myil
Christopher John Wiercienski Paul
Dena Sina
John Halter Steven
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112018070131A2 publication Critical patent/BR112018070131A2/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3275—Power saving in memory, e.g. RAM, cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1028—Power efficiency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/657—Virtual address space management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/683—Invalidation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Power Sources (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

métodos e sistemas são apresentados para hardware completo de gerenciamento de energia e domínios de clock relacionados a uma rede de memória virtual distribuída (dvm). um aspecto inclui transmitir, de um iniciador dvm para uma rede dvm, uma operação dvm, transmissão, pela rede dvm para uma série de alvos dvm, a operação dvm e, com base na operação dvm sendo transmitida para a série de alvos dvm pela rede dvm, executando uma ou mais otimizações de hardware incluindo: ligar um domínio de clock acoplado à rede dvm ou um alvo dvm da série de alvos dvm que é um objetivo da operação dvm, aumentando a frequência do domínio do clock, ligar um domínio de energia acoplado ao alvo do dvm com base no domínio de energia desligado ou terminar a operação do dvm para o alvo do dvm com base no destino do dvm que está sendo desligado.
BR112018070131A 2016-03-31 2017-03-13 colapso de energia gerenciado por hardware e ativação de clock para unidades de gerenciamento de memória e redes de memória virtual distribuídas BR112018070131A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/086,054 US10386904B2 (en) 2016-03-31 2016-03-31 Hardware managed power collapse and clock wake-up for memory management units and distributed virtual memory networks
PCT/US2017/022158 WO2017172342A1 (en) 2016-03-31 2017-03-13 Hardware managed power collapse and clock wake-up for memory management units and distributed virtual memory networks

Publications (1)

Publication Number Publication Date
BR112018070131A2 true BR112018070131A2 (pt) 2019-02-05

Family

ID=58448615

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112018070131A BR112018070131A2 (pt) 2016-03-31 2017-03-13 colapso de energia gerenciado por hardware e ativação de clock para unidades de gerenciamento de memória e redes de memória virtual distribuídas

Country Status (9)

Country Link
US (2) US10386904B2 (pt)
EP (1) EP3436895B1 (pt)
JP (1) JP6640374B2 (pt)
KR (1) KR102048399B1 (pt)
CN (1) CN108780350B (pt)
BR (1) BR112018070131A2 (pt)
CA (1) CA3015929A1 (pt)
TW (1) TWI698746B (pt)
WO (1) WO2017172342A1 (pt)

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US10719452B2 (en) * 2018-06-22 2020-07-21 Xilinx, Inc. Hardware-based virtual-to-physical address translation for programmable logic masters in a system on chip
US10983851B1 (en) * 2019-12-04 2021-04-20 Cirrus Logic, Inc. Protecting against memory corruption and system freeze during power state transitions in a multi-power domain system
CN116830093A (zh) * 2021-04-30 2023-09-29 华为技术有限公司 虚拟化系统以及虚拟化系统中内存一致性维护方法

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JP3696901B2 (ja) * 1994-07-19 2005-09-21 キヤノン株式会社 負荷分散方法
US5884100A (en) 1996-06-06 1999-03-16 Sun Microsystems, Inc. Low-latency, high-throughput, integrated cache coherent I/O system for a single-chip processor
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FR2808904A1 (fr) * 2000-05-12 2001-11-16 Ibm Systeme d'acces a des memoires redondantes
US6990594B2 (en) * 2001-05-02 2006-01-24 Portalplayer, Inc. Dynamic power management of devices in computer system by selecting clock generator output based on a current state and programmable policies
US7725742B2 (en) * 2006-08-15 2010-05-25 Mitac International Corp. Remote monitor module for power initialization of computer system
US7853928B2 (en) * 2007-04-19 2010-12-14 International Business Machines Corporation Creating a physical trace from a virtual trace
US8775839B2 (en) 2008-02-08 2014-07-08 Texas Instruments Incorporated Global hardware supervised power transition management circuits, processes and systems
US8732700B2 (en) * 2008-12-18 2014-05-20 Vmware, Inc. Virtualization system with a remote proxy
US8244978B2 (en) 2010-02-17 2012-08-14 Advanced Micro Devices, Inc. IOMMU architected TLB support
EP2652623B1 (en) * 2010-12-13 2018-08-01 SanDisk Technologies LLC Apparatus, system, and method for auto-commit memory
US9177615B2 (en) * 2011-07-06 2015-11-03 Qualcomm Technologies, Inc. Power disconnect unit for use in data transport topology of network on chip design having asynchronous clock domain adapter sender and receiver each at a separate power domain
US9916257B2 (en) 2011-07-26 2018-03-13 Intel Corporation Method and apparatus for TLB shoot-down in a heterogeneous computing system supporting shared virtual memory
US9298621B2 (en) 2011-11-04 2016-03-29 Hewlett Packard Enterprise Development Lp Managing chip multi-processors through virtual domains
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TWI609282B (zh) 2012-12-18 2017-12-21 新思科技股份有限公司 用於低功率設計之階層式功率地圖
US9330026B2 (en) * 2013-03-05 2016-05-03 Qualcomm Incorporated Method and apparatus for preventing unauthorized access to contents of a register under certain conditions when performing a hardware table walk (HWTW)
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Also Published As

Publication number Publication date
CN108780350B (zh) 2021-08-06
KR102048399B1 (ko) 2020-01-09
EP3436895A1 (en) 2019-02-06
EP3436895C0 (en) 2023-08-02
TW201737093A (zh) 2017-10-16
JP6640374B2 (ja) 2020-02-05
JP2019517052A (ja) 2019-06-20
WO2017172342A1 (en) 2017-10-05
CN108780350A (zh) 2018-11-09
TWI698746B (zh) 2020-07-11
EP3436895B1 (en) 2023-08-02
US10386904B2 (en) 2019-08-20
US20170285705A1 (en) 2017-10-05
US20190324512A1 (en) 2019-10-24
CA3015929A1 (en) 2017-10-05
KR20180125978A (ko) 2018-11-26

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B06W Patent application suspended after preliminary examination (for patents with searches from other patent authorities) chapter 6.23 patent gazette]