BR112018069770A2 - método e dispositivo para configurar um circuito integrado a um conjunto de recursos solicitados - Google Patents

método e dispositivo para configurar um circuito integrado a um conjunto de recursos solicitados

Info

Publication number
BR112018069770A2
BR112018069770A2 BR112018069770A BR112018069770A BR112018069770A2 BR 112018069770 A2 BR112018069770 A2 BR 112018069770A2 BR 112018069770 A BR112018069770 A BR 112018069770A BR 112018069770 A BR112018069770 A BR 112018069770A BR 112018069770 A2 BR112018069770 A2 BR 112018069770A2
Authority
BR
Brazil
Prior art keywords
integrated circuit
configuring
resource
feature set
requested feature
Prior art date
Application number
BR112018069770A
Other languages
English (en)
Portuguese (pt)
Inventor
Campbell Bryan
Mclean Ivan
Dragicevich Mark
Moskovics Stuart
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112018069770A2 publication Critical patent/BR112018069770A2/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/57—Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/76—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Software Systems (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Semiconductor Integrated Circuits (AREA)
BR112018069770A 2016-03-29 2017-03-09 método e dispositivo para configurar um circuito integrado a um conjunto de recursos solicitados BR112018069770A2 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201662314928P 2016-03-29 2016-03-29
US15/234,879 US10534882B2 (en) 2016-03-29 2016-08-11 Method and apparatus for configuring an integrated circuit with a requested feature set
PCT/US2017/021611 WO2017172322A1 (en) 2016-03-29 2017-03-09 Method and apparatus for configuring an integrated circuit with a requested feature set

Publications (1)

Publication Number Publication Date
BR112018069770A2 true BR112018069770A2 (pt) 2019-02-05

Family

ID=59959404

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112018069770A BR112018069770A2 (pt) 2016-03-29 2017-03-09 método e dispositivo para configurar um circuito integrado a um conjunto de recursos solicitados

Country Status (7)

Country Link
US (1) US10534882B2 (enExample)
EP (1) EP3437009A1 (enExample)
JP (1) JP2019516276A (enExample)
KR (1) KR20180125974A (enExample)
CN (1) CN108780484A (enExample)
BR (1) BR112018069770A2 (enExample)
WO (1) WO2017172322A1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102621645B1 (ko) 2019-03-12 2024-01-05 삼성전자주식회사 보안 집적 회로를 포함하는 전자 장치
DE102020001199A1 (de) * 2020-02-25 2021-08-26 Daimler Ag Kommunikationsvorrichtung und Verfahren zur kryptografischen Absicherung der Kommunikation
US11886722B2 (en) * 2021-03-31 2024-01-30 Lenovo (Singapore) Pte. Ltd. Smart inclusion of technology at time of build

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0743602B1 (en) 1995-05-18 2002-08-14 Hewlett-Packard Company, A Delaware Corporation Circuit device for function usage control in an integrated circuit
JP2000215280A (ja) * 1999-01-26 2000-08-04 Hitachi Ltd 本人認証システム
US6678645B1 (en) * 1999-10-28 2004-01-13 Advantest Corp. Method and apparatus for SoC design validation
JP2002353083A (ja) * 2001-05-23 2002-12-06 Hitachi Ltd 半導体集積回路の製造方法
JP4145118B2 (ja) * 2001-11-26 2008-09-03 松下電器産業株式会社 アプリケーション認証システム
US7587607B2 (en) 2003-12-22 2009-09-08 Intel Corporation Attesting to platform configuration
US7693596B2 (en) 2005-12-14 2010-04-06 Dell Products L.P. System and method for configuring information handling system integrated circuits
US7512028B2 (en) 2007-04-17 2009-03-31 Agere Systems Inc. Integrated circuit feature definition using one-time-programmable (OTP) memory
US8752165B2 (en) 2008-05-29 2014-06-10 Apple Inc. Provisioning secrets in an unsecured environment
CN102648471B (zh) * 2008-11-24 2015-05-27 塞尔蒂卡姆公司 用于基于硬件的安全的系统和方法
DE102008044244A1 (de) * 2008-12-01 2010-06-02 Robert Bosch Gmbh Brennkraftmaschine
CN101487876B (zh) * 2009-02-23 2011-08-03 中国科学院计算技术研究所 验证向量的优化方法及装置
US20130086385A1 (en) 2011-09-30 2013-04-04 Yuri Poeluev System and Method for Providing Hardware-Based Security
US10771448B2 (en) * 2012-08-10 2020-09-08 Cryptography Research, Inc. Secure feature and key management in integrated circuits
US9436848B2 (en) 2013-05-30 2016-09-06 Cryptography Research, Inc. Configurator for secure feature and key manager
EP2911086A1 (en) 2014-02-19 2015-08-26 Renesas Electronics Europe GmbH Integrated circuit with parts activated based on intrinsic features
CN105279547B (zh) * 2015-11-12 2018-09-04 大唐微电子技术有限公司 一种生物识别ic卡及其控制方法

Also Published As

Publication number Publication date
EP3437009A1 (en) 2019-02-06
JP2019516276A (ja) 2019-06-13
WO2017172322A1 (en) 2017-10-05
US10534882B2 (en) 2020-01-14
CN108780484A (zh) 2018-11-09
KR20180125974A (ko) 2018-11-26
US20170286580A1 (en) 2017-10-05

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Legal Events

Date Code Title Description
B350 Update of information on the portal [chapter 15.35 patent gazette]
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 5A ANUIDADE.

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: EM VIRTUDE DO ARQUIVAMENTO PUBLICADO NA RPI 2661 DE 04-01-2022 E CONSIDERANDO AUSENCIA DE MANIFESTACAO DENTRO DOS PRAZOS LEGAIS, INFORMO QUE CABE SER MANTIDO O ARQUIVAMENTO DO PEDIDO DE PATENTE, CONFORME O DISPOSTO NO ARTIGO 12, DA RESOLUCAO 113/2013.