BR112018006100A2 - método e aparelho para deduplicação de linha de cache por meio de correspondência de dados - Google Patents

método e aparelho para deduplicação de linha de cache por meio de correspondência de dados

Info

Publication number
BR112018006100A2
BR112018006100A2 BR112018006100A BR112018006100A BR112018006100A2 BR 112018006100 A2 BR112018006100 A2 BR 112018006100A2 BR 112018006100 A BR112018006100 A BR 112018006100A BR 112018006100 A BR112018006100 A BR 112018006100A BR 112018006100 A2 BR112018006100 A2 BR 112018006100A2
Authority
BR
Brazil
Prior art keywords
cache
cache line
line
data matching
line data
Prior art date
Application number
BR112018006100A
Other languages
English (en)
Inventor
Robert Hower Derek
Wade Cain Harold Iii
Damodaran Raguram
Andrew Sartorius Thomas
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112018006100A2 publication Critical patent/BR112018006100A2/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0808—Multiuser, multiprocessor or multiprocessing cache systems with cache invalidating means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1041—Resource optimization
    • G06F2212/1044—Space efficiency improvement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/62—Details of cache specific to multiprocessor cache arrangements
    • G06F2212/621—Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

uma linha de preenchimento de cache é recebida, em que inclui um índice, um identificador de thread e dados de linha de preenchimento de cache. o cache é investigado com o uso do índice e um identificador de thread diferente para uma linha de cache duplicada potencial. a linha de cache duplicada potencial inclui dados de linha de cache e o identificador de thread diferente. mediante a correspondência dos dados de linha de preenchimento de cache aos dados de linha de cache, a duplicação é identificada. a linha de cache duplicada potencial é ajustada como uma linha de cache residente compartilhada e a etiqueta de permissão de compartilhamento de thread é ajustada para um estado de permissão.
BR112018006100A 2015-09-25 2016-09-12 método e aparelho para deduplicação de linha de cache por meio de correspondência de dados BR112018006100A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/865,049 US20170091117A1 (en) 2015-09-25 2015-09-25 Method and apparatus for cache line deduplication via data matching
PCT/US2016/051241 WO2017053109A1 (en) 2015-09-25 2016-09-12 Method and apparatus for cache line deduplication via data matching

Publications (1)

Publication Number Publication Date
BR112018006100A2 true BR112018006100A2 (pt) 2018-10-16

Family

ID=56940468

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112018006100A BR112018006100A2 (pt) 2015-09-25 2016-09-12 método e aparelho para deduplicação de linha de cache por meio de correspondência de dados

Country Status (7)

Country Link
US (1) US20170091117A1 (pt)
EP (1) EP3353662A1 (pt)
JP (1) JP2018533135A (pt)
KR (1) KR20180058797A (pt)
CN (1) CN108027777A (pt)
BR (1) BR112018006100A2 (pt)
WO (1) WO2017053109A1 (pt)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10152429B2 (en) * 2015-10-27 2018-12-11 Medallia, Inc. Predictive memory management
US10831664B2 (en) 2017-06-16 2020-11-10 International Business Machines Corporation Cache structure using a logical directory
US10606762B2 (en) * 2017-06-16 2020-03-31 International Business Machines Corporation Sharing virtual and real translations in a virtual cache
US10698836B2 (en) * 2017-06-16 2020-06-30 International Business Machines Corporation Translation support for a virtual cache
US10705969B2 (en) 2018-01-19 2020-07-07 Samsung Electronics Co., Ltd. Dedupe DRAM cache
JP2022540972A (ja) * 2019-05-31 2022-09-21 インテル・コーポレーション 高性能メモリ管理システムにおけるガーベジコレクションの回避
US11194730B2 (en) * 2020-02-09 2021-12-07 International Business Machines Corporation Application interface to depopulate data from cache
CN112565437B (zh) * 2020-12-07 2021-11-19 浙江大学 一种面向跨界服务网络的服务缓存方法
US11593109B2 (en) * 2021-06-07 2023-02-28 International Business Machines Corporation Sharing instruction cache lines between multiple threads
US11593108B2 (en) 2021-06-07 2023-02-28 International Business Machines Corporation Sharing instruction cache footprint between multiple threads

Family Cites Families (11)

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Publication number Priority date Publication date Assignee Title
US6542991B1 (en) * 1999-05-11 2003-04-01 Sun Microsystems, Inc. Multiple-thread processor with single-thread interface shared among threads
US6938252B2 (en) * 2000-12-14 2005-08-30 International Business Machines Corporation Hardware-assisted method for scheduling threads using data cache locality
US6901483B2 (en) * 2002-10-24 2005-05-31 International Business Machines Corporation Prioritizing and locking removed and subsequently reloaded cache lines
US20050210204A1 (en) * 2003-01-27 2005-09-22 Fujitsu Limited Memory control device, data cache control device, central processing device, storage device control method, data cache control method, and cache control method
US7136967B2 (en) * 2003-12-09 2006-11-14 International Business Machinces Corporation Multi-level cache having overlapping congruence groups of associativity sets in different cache levels
US7594236B2 (en) * 2004-06-28 2009-09-22 Intel Corporation Thread to thread communication
US7434000B1 (en) * 2004-06-30 2008-10-07 Sun Microsystems, Inc. Handling duplicate cache misses in a multithreaded/multi-core processor
US20060143384A1 (en) * 2004-12-27 2006-06-29 Hughes Christopher J System and method for non-uniform cache in a multi-core processor
US7318127B2 (en) * 2005-02-11 2008-01-08 International Business Machines Corporation Method, apparatus, and computer program product for sharing data in a cache among threads in an SMT processor
US8214602B2 (en) * 2008-06-23 2012-07-03 Advanced Micro Devices, Inc. Efficient load queue snooping
US8966232B2 (en) * 2012-02-10 2015-02-24 Freescale Semiconductor, Inc. Data processing system operable in single and multi-thread modes and having multiple caches and method of operation

Also Published As

Publication number Publication date
WO2017053109A1 (en) 2017-03-30
EP3353662A1 (en) 2018-08-01
KR20180058797A (ko) 2018-06-01
CN108027777A (zh) 2018-05-11
JP2018533135A (ja) 2018-11-08
US20170091117A1 (en) 2017-03-30

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Legal Events

Date Code Title Description
B11A Dismissal acc. art.33 of ipl - examination not requested within 36 months of filing
B11Y Definitive dismissal acc. article 33 of ipl - extension of time limit for request of examination expired