BR112017026563A2 - circuito de fecho de resposta - Google Patents

circuito de fecho de resposta

Info

Publication number
BR112017026563A2
BR112017026563A2 BR112017026563A BR112017026563A BR112017026563A2 BR 112017026563 A2 BR112017026563 A2 BR 112017026563A2 BR 112017026563 A BR112017026563 A BR 112017026563A BR 112017026563 A BR112017026563 A BR 112017026563A BR 112017026563 A2 BR112017026563 A2 BR 112017026563A2
Authority
BR
Brazil
Prior art keywords
lock
closure
response
result
transistors
Prior art date
Application number
BR112017026563A
Other languages
English (en)
Other versions
BR112017026563B1 (pt
Inventor
Datta Animesh
Ye Qi
James Dillen Steven
Duan Zhengyu
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112017026563A2 publication Critical patent/BR112017026563A2/pt
Publication of BR112017026563B1 publication Critical patent/BR112017026563B1/pt

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541—Scan latches or cell details
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3562—Bistable circuits of the master-slave type
    • H03K3/35625—Bistable circuits of the master-slave type using complementary field-effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Power-Operated Mechanisms For Wings (AREA)

Abstract

um dispositivo mos inclui um primeiro fecho configurado com uma resposta de fecho f e configurado para receber uma entrada de fecho i e um relógio de fecho c. o primeiro fecho é configurado para gerar o resultado q, onde o resultado q é uma função de cf, if, e , e a resposta de fecho f é uma função do resultado q. o primeiro fecho pode incluir um primeiro conjunto de transistores empilhados em série, no qual o primeiro conjunto de transistores inclui ao menos cinco transistores. o dispositivo mos pode ainda incluir um segundo fecho acoplado ao primeiro fecho. o segundo fecho pode ser configurado como um fecho em um modo de varredura e como um fecho de pulso em um modo funcional. o primeiro fecho pode operar como um fecho mestre e o segundo fecho pode operar como um servo durante o modo de varredura.
BR112017026563-0A 2015-06-10 2016-03-31 Circuito latch de realimentação BR112017026563B1 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/736,213 2015-06-10
US14/736,213 US9584121B2 (en) 2015-06-10 2015-06-10 Compact design of scan latch
PCT/US2016/025163 WO2016200468A1 (en) 2015-06-10 2016-03-31 Feedback latch circuit

Publications (2)

Publication Number Publication Date
BR112017026563A2 true BR112017026563A2 (pt) 2018-08-14
BR112017026563B1 BR112017026563B1 (pt) 2023-04-11

Family

ID=55754435

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112017026563-0A BR112017026563B1 (pt) 2015-06-10 2016-03-31 Circuito latch de realimentação

Country Status (8)

Country Link
US (1) US9584121B2 (pt)
EP (1) EP3308462B1 (pt)
JP (1) JP6430667B2 (pt)
KR (1) KR101861162B1 (pt)
CN (1) CN107743603B (pt)
BR (1) BR112017026563B1 (pt)
CA (1) CA2986231A1 (pt)
WO (1) WO2016200468A1 (pt)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10069486B1 (en) * 2016-06-29 2018-09-04 Xilinx, Inc. Multimode registers with pulse latches
KR102640502B1 (ko) * 2018-12-13 2024-02-26 삼성전자주식회사 반도체 회로 및 반도체 회로의 레이아웃 시스템
KR20210074429A (ko) 2019-12-11 2021-06-22 삼성전자주식회사 클럭 신호를 보상하기 위한 보상 회로 및 그것을 포함하는 메모리 장치
US11218137B2 (en) * 2020-04-14 2022-01-04 Globalfoundries U.S. Inc. Low clock load dynamic dual output latch circuit

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5242507B2 (pt) 1972-08-31 1977-10-25
US4677318A (en) * 1985-04-12 1987-06-30 Altera Corporation Programmable logic storage element for programmable logic devices
US6459331B1 (en) * 1997-09-02 2002-10-01 Kabushiki Kaisha Toshiba Noise suppression circuit, ASIC, navigation apparatus communication circuit, and communication apparatus having the same
US6191606B1 (en) * 1998-09-10 2001-02-20 Intel Corporation Method and apparatus for reducing standby leakage current using input vector activation
GB2368473A (en) * 2000-10-24 2002-05-01 Advanced Risc Mach Ltd Modified clock signal generator
TWI228349B (en) * 2003-04-21 2005-02-21 Univ Tsinghua Earle latch circuit and design method thereof
CN100576742C (zh) * 2003-09-03 2009-12-30 Nxp股份有限公司 静态锁存器
US7400555B2 (en) 2003-11-13 2008-07-15 International Business Machines Corporation Built in self test circuit for measuring total timing uncertainty in a digital data path
US7457998B1 (en) 2005-01-07 2008-11-25 Cadence Design Systems, Inc. Scan register and methods of using the same
US7495466B1 (en) 2006-06-30 2009-02-24 Transmeta Corporation Triple latch flip flop system and method
US7372305B1 (en) 2006-10-31 2008-05-13 International Business Machines Corporation Scannable dynamic logic latch circuit
KR101691568B1 (ko) 2009-12-11 2016-12-30 삼성전자주식회사 플립-플롭 회로
US7977976B1 (en) 2010-05-21 2011-07-12 Apple Inc. Self-gating synchronizer
US8943375B2 (en) * 2012-08-08 2015-01-27 Oracle International Corporation Combo static flop with full test

Also Published As

Publication number Publication date
CN107743603B (zh) 2018-12-04
EP3308462A1 (en) 2018-04-18
WO2016200468A1 (en) 2016-12-15
KR20170140421A (ko) 2017-12-20
US9584121B2 (en) 2017-02-28
KR101861162B1 (ko) 2018-05-25
CA2986231A1 (en) 2016-12-15
EP3308462B1 (en) 2020-12-23
JP2018523370A (ja) 2018-08-16
BR112017026563B1 (pt) 2023-04-11
JP6430667B2 (ja) 2018-11-28
US20160365856A1 (en) 2016-12-15
CN107743603A (zh) 2018-02-27

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Legal Events

Date Code Title Description
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B350 Update of information on the portal [chapter 15.35 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 31/03/2016, OBSERVADAS AS CONDICOES LEGAIS