BR112017017352A2 - pacote semicondutor lado a lado - Google Patents

pacote semicondutor lado a lado

Info

Publication number
BR112017017352A2
BR112017017352A2 BR112017017352A BR112017017352A BR112017017352A2 BR 112017017352 A2 BR112017017352 A2 BR 112017017352A2 BR 112017017352 A BR112017017352 A BR 112017017352A BR 112017017352 A BR112017017352 A BR 112017017352A BR 112017017352 A2 BR112017017352 A2 BR 112017017352A2
Authority
BR
Brazil
Prior art keywords
matrix
semiconductor package
cavity
active
interconnection
Prior art date
Application number
BR112017017352A
Other languages
English (en)
Other versions
BR112017017352B1 (pt
Inventor
Raza Syed Ahmer
Kim Chin-Kwan
Pravin Shah Milind
James Bchir Omar
David Lane Ryan
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112017017352A2 publication Critical patent/BR112017017352A2/pt
Publication of BR112017017352B1 publication Critical patent/BR112017017352B1/pt

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Classifications

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    • H01L2924/151—Die mounting substrate
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    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
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    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15333—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a land array, e.g. LGA

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Measuring And Recording Apparatus For Diagnosis (AREA)

Abstract

trata-se de um pacote semicondutor para uma configuração de matriz lado a lado que pode incluir um substrato que tem uma cavidade, um interposto de ponte posicionado no interior da cavidade e que tem um lado ativo voltado para os lados ativos de uma primeira matriz e de uma segunda matriz e sobreposto parcialmente de modo horizontal à primeira matriz e à segunda matriz a fim de fornecer uma interconexão entre a primeira matriz e a segunda matriz, sendo que um elemento térmico é fixado às partes posteriores da primeira matriz e da segunda matriz a fim de fornecer uma trajetória de calor e de armazenamento de calor para a primeira matriz e para a segunda matriz.
BR112017017352-2A 2015-02-13 2016-01-26 Pacote semicondutor lado a lado BR112017017352B1 (pt)

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US14/622,346 2015-02-13
US14/622,346 US9379090B1 (en) 2015-02-13 2015-02-13 System, apparatus, and method for split die interconnection
PCT/US2016/014913 WO2016130317A1 (en) 2015-02-13 2016-01-26 Side by side semiconductor package

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BR112017017352B1 (pt) 2022-12-13
KR102250743B1 (ko) 2021-05-10
US9379090B1 (en) 2016-06-28
JP2018508993A (ja) 2018-03-29
KR20180120809A (ko) 2018-11-06
CN111883519A (zh) 2020-11-03
CN107210288A (zh) 2017-09-26
EP3257078A1 (en) 2017-12-20
JP2019033297A (ja) 2019-02-28
SG11201705247YA (en) 2017-09-28
KR20170098320A (ko) 2017-08-29
EP3257078B1 (en) 2022-02-23
WO2016130317A1 (en) 2016-08-18

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