BR112017011803B1 - SOLID-STATE IMAGE SENSOR WITH IMPROVED LOAD CAPACITY AND DYNAMIC RANGE - Google Patents

Abstract

SOLID-STATE IMAGE SENSOR WITH IMPROVED LOAD CAPACITY AND DYNAMIC RANGE. Certain aspects relate to imaging systems and methods for manufacturing imaging systems and image sensors. The imaging system includes a set of pixels including a plurality of pixels, the pixels configured to generate a charge when exposed to light and arranged in a first layer. The imaging system further includes a plurality of pixel circuits for reading light integrated with the pixels coupled thereto, each of the plurality of pixel circuits comprising one or more transistors shared among a subset of the plurality of pixels, the one or more transistors arranged in a second layer different from the first layer. The imaging system further includes a plurality of floating diffusion nodes configured to couple each of the plurality of pixels to the plurality of pixel circuits.

Description

Technical Field

[0001] The systems and methods described here are directed to photographic sensors, and more particularly to sub-micron pixel and vertically integrated pixel sensors.

Fundamentals

[0002] The trend in digital cameras and digital image production is toward smaller pixels to drive the megapixel count upward or to allow for smaller sensor areas. At the same time, improvements in terms of speed, sensitivity and pixel numbers are desirable. However, reducing the size and increasing the number of pixels may not support the desired increase in speed and sensitivity. Smaller sized pixels can suffer from many challenges. For example, smaller pixels may have slower perception speeds or degraded resolution and color fidelity, and may have a limited dynamic range when compared to larger pixels. Particularly in mobile sensors, the trend toward shrinking pixel size and sensor area attempts to maintain performance through advanced processing. Reduced total capacity, reduced quantum efficiency, and reduced photosensitivity of the sub-micron pixel detector array greatly degrade the signal-to-noise ratio (SNR) and dynamic range of the image sensor. Additionally, increased interference from reduced pixel size results in problems with image quality, e.g., poor modulation transfer function (MTF) and color fidelity.

[0003] In digital imaging, the dynamic range of a complementary metal oxide semiconductor (CMOS) sensor may sometimes be insufficient to accurately represent external scenes. This can especially be the camera on a mobile phone. For example, a typical sensor used in a mobile device camera might have a dynamic range of approximately 60 to 70 dB. However, a typical natural outdoor scene can easily cover a 100 dB contrast range between bright areas and shadows. Since this dynamic range is greater than the dynamic range of a typical sensor used in a mobile device, detail may be lost in images captured by mobile devices.

summary

[0004] The systems, methods and devices of the invention each have several aspects, none of which is alone responsible for their desirable attributes. Without limiting the scope of this invention as expressed by the following claims, some features will now be briefly described. After considering this discussion, and particularly after reading the section entitled "Detailed Description", one will understand how the characteristics of the various embodiments of this invention provide advantages that include improved communications between access points and stations in a wireless network.

[0005] The embodiments described here each have several innovative aspects, none of which alone is responsible for the desirable attributes of the invention. Without limiting the scope as expressed by the claims that follow, the most prominent features will be briefly described here. After considering this discussion, one will understand how the characteristics of the various embodiments provide several advantages over current dynamic wireless charging systems.

[0006] One aspect of the description provides an image creation system. The imaging system includes a plurality of pixels configured to convert light into a charge. The imaging system further includes one or more amplifier transistors configured to convert a charge from a plurality of pixels, one or more selection transistors configured to select a row or column among the plurality of pixels to be read, and one or more more tuning transistors configured to reset at least one of the plurality of pixels. The imaging system also includes an array of pixels. The pixel array is arranged in a plurality of rows and columns and further includes a plurality of transfer gate transistors. Each of the plurality of transfer gate transistors corresponds to one of the plurality of pixels. The imaging system further includes a first silicon layer upon which the plurality of pixels are disposed and a second silicon layer upon which at least one of one or more amplifier transistors, selection transistors, and retuning transistors are arranged. are willing.

[0007] Another aspect described is another image creation system. The other imaging system includes a plurality of pixels, where the pixels are configured to generate a charge when exposed to light. The other imaging system also includes a plurality of pixel circuits, each pixel circuit comprising at least one of a reset transistor, a line selection transistor, or an amplification resistor. The other imaging system further includes a plurality of shared pixel architectures, the shared pixel architectures comprising one or more pixels among the plurality of pixels and pixel circuits among the plurality of pixel circuits. The other imaging system also includes an array of pixels including the plurality of shared pixel architectures. The pixel arrangement is arranged in a plurality of rows and columns. Finally, the other imaging system includes a first silicon layer and a second silicon layer located above the first silicon layer.

[0008] Another aspect described is another image creation system. The imaging system includes an array of pixels including a plurality of pixels, the pixels configured to generate a charge when exposed to light and arranged in a first layer. The imaging system further includes a plurality of pixel circuits for reading light integrated into the pixels coupled thereto, each of the plurality of pixel circuits comprising one or more transistors shared among a subset of the plurality of pixels, the one or more transistors arranged in a second layer different from the first layer. The imaging system further includes a plurality of floating diffusion nodes configured to couple each of the plurality of pixels to the plurality of pixel circuits.

[0009] Another aspect described is a method of manufacturing a three-dimensional (3D) stacked image sensor. The method includes forming a pixel array including a plurality of pixels arranged in one or more shared pixel architectures. The formed pixel array is arranged in a plurality of rows and columns and further includes a plurality of transfer gate transistors, where each of the plurality of transfer gate transistors corresponds to one of the plurality of pixels. The method also includes arranging the plurality of pixels on a first silicon layer and arranging at least one amplifier transistor, selection transistor, and reset transistor on a second silicon layer different from the first silicon layer. The method further includes electrically coupling the first silicon layer with the second silicon layer.

Brief Description of Drawings

[0010] The described aspects, however, will be described in conjunction with the attached drawings and appendices, provided to illustrate and not limit the described aspects, where similar designations denote similar elements.

[0011] Figure 1A illustrates an embodiment of a shared pixel architecture for use as a pixel of a pixel reading system, according to an illustrative embodiment.

[0012] Figure 1B illustrates an embodiment of an architecture with 4 shared pixels and four intertwined resistors, according to an illustrative embodiment.

[0013] Figure 1C illustrates an embodiment of two shared 4-pixel architectures and four resistors of Figure 1B in an interlaced pixel architecture set, according to an illustrative embodiment.

[0014] Figure 2 shows the architectures of 4 transistors and 4 shared pixels of Figures 1B and 1C in a set of interlaced pixel architectures, according to an illustrative embodiment.

[0015] Figure 3A illustrates a 4-color reading sequence per channel of a 1 x 4 interlaced 4 shared pixel architecture, according to an illustrative embodiment.

[0016] Figure 3B illustrates a 4-color reading sequence per channel of a 2 x 2 interlaced 4 shared pixel architecture, according to an illustrative embodiment.

[0017] Figure 4A illustrates an embodiment of an architecture of 8 shared image sensor pixels and four interlaced transistors 400 having a pixel reading system, according to an illustrative embodiment.

[0018] Figure 4B illustrates a first section of an embodiment of a 16-pixel shared image sensor architecture and 4 transistors 450 having a pixel reading system, in accordance with an illustrative embodiment, having connection points A-B to indicate the continuation of the elements in figure 4C.

[0019] Figure 4C illustrates a second section of an embodiment of a 16-pixel shared image sensor architecture and 4 transistors 450 having a pixel reading system, in accordance with an illustrative embodiment, having connection points A-B to indicate the continuation of the elements in figure 4B.

[0020] Figure 5A illustrates an embodiment of a 3D stacked CMOS image sensor comprising the interlaced shared pixel architecture of Figures 4A and 4B with pixel-level fine-tilt hybrid coupling.

[0021] Figure 5B illustrates another embodiment of a 3D stacked CMOS image sensor comprising the interlaced shared pixel architecture of Figures 4A and 4B with column/row level fusion.

[0022] Figure 6A illustrates a first section of a timing diagram of the 4 shared image sensor pixels and four interlaced transistor architecture of Figure 1B, according to an illustrative embodiment, having connection points A-X to indicate the continuation of elements in figure 6B.

[0023] Figure 6B illustrates a second section of a timing diagram of the 4 shared image sensor pixels and four interlaced transistor architecture of Figure 1B, in accordance with an illustrative embodiment, having connection points A-X to indicate the continuation of elements of figure 6A.

[0024] Figure 7 illustrates an example of a reading block diagram of the architecture of 4 shared image sensor pixels and four interlaced transistors of Figure 1B in accordance with the timing diagram of Figures 6A and 6B.

[0025] Figure 8 illustrates a high-level schematic diagram of an embodiment of an image capture device with full well capacity extension capabilities.

Detailed Description Introduction

[0026] Embodiments of the description refer to systems and techniques for the generation and implementation of sub-micron pixels capable of low noise and high gain readout, high resolution and high color fidelity outputs, and an increased dynamic range using architectures vertically integrated, stacked three-dimensional (3D) pixels. As pixel size continues to decrease, the necessary components within the pixel to maintain the desired image capture qualities and characteristics (e.g., low noise, high gain, high resolution and color fidelity, etc.) reduce the amount of light available to the pixel's light sensing structure, e.g., the photodetector, photodiode, or similar structure or device. For example, as the pixel size decreases, there is less physical area in the pixel since components cannot be eliminated and the size of components can only be reduced to a certain point based on general manufacturing and technology constraints. Accordingly, additional architectures can be developed that maintain the number and size of components in each pixel while increasing the area with which the photodetector, photodiode, or similar structure or device can absorb light and generate a charge in response to the absorbed light. . The readout architecture, including an additional storage capacitor, can implement a signal readout scheme to enable extension of the entire well capability by amplifying the signal-to-noise ratio (SNR) and dynamic range. The associated readout architecture may be implemented, in various embodiments, with a four-transistor configuration and 4 shared CIS pixels, 8 shared pixels, 16 shared pixels, or other suitable pixel configurations. Pixel readout components including retuning transistors, amplification transistors, and a timing scheme and storage capacitor can cooperate to store charges accumulated from the photodetectors or photodiodes to perform multiple pixel readouts. The terms "pixel" and "photodiode", "photodetector", "photo gate", etc. can be used interchangeably here.

[0027] In an example, where a transfer gate, timing circuit and reset transistor are all activated, a photodiode and a floating diffusion node can be reset. Additionally, charge integration into the storage capacitor can occur when the transfer gate, timing circuit, and reset transistor are all turned off, allowing the photon charge to be collected in a photodiode. After that the charge accumulates on the photodiodes.

[0028] In some embodiments, the storage capacitor can be used for charge integration. The storage capacitor can allow smaller dumps from the photodiode to be stored in the storage capacitor. Accordingly, the charge on the storage capacitor becomes larger as more dumps from the photodiodes are combined. When the timing circuit is turned on one or more times in conjunction with the transfer gate, the charge on the photodiode can be dumped to the storage capacitor. Accordingly, the storage capacitor can hold charges from multiple readings of a pixel or group of pixels.

[0029] In some examples, the primary source of noise within a CMOS pixel is kTC (or reset) noise arising from the reconfiguration of the storage capacitor and/or capacitive floating diffusion node through the resistive channel of the reset transistor (a few tens of electrons). An embodiment of a readout mode that can be implemented using embodiments of the architecture described herein can include a first readout taken immediately after a reconfiguration or before another voltage is applied to the storage capacitor and/or capacitive floating diffusion node. . This first reading can store the kTC noise in memory as a baseline. Such kTC noise may originate from readjusted capacitor noise and may be desirable to improve image quality, to reduce, eliminate or otherwise compensate for kTC noise. Accordingly, a second reading can be performed after charge integration on the storage capacitor (e.g., including multiple pixel or pixel charge dumps, where charges generated by photons integrate) by turning on the selector circuit again. Due to the additional charge storage capacity of the storage capacitor and multiple photodiode charge dumps controlled by the timing scheme, the two readings can provide multiplication of the total pixel capacity proportional to the number of charge dumps. Since the kTC noise was stored in memory as a baseline in the first frame, this reading method can compensate for the kTC noise in the second reading. By taking both readings, for example, sampling the storage capacitor or floating diffusion node after the storage capacitor or floating diffusion node is reset, but before the transfer port is turned on and after the transfer port be turned on, correlated double sampling with a short sampling time can be performed, thus eliminating kTC noise.

[0030] Another embodiment of a reading mode that can be implemented using the embodiments of the well full capacity extension architecture described here can perform multiple readings and obtain the charge difference between two charge dumps of a photodiode. The resulting differential frame can be free from kTC noise. In some embodiments, multiple readings may be performed in a low bit depth mode to conserve power if high accuracy is not required, for example, by a preview image in the viewfinder or for auto exposure adjustments. In some embodiments, multiple readings may be performed in normal bit depth mode for more accurate image information. In some embodiments, for example high dynamic range (HDR) imaging, two different integration times may be used for charge dumps in two readings used to generate the differential frame.

[0031] A pixel reading system can be used for any CMOS, CCD or other image sensor. In some embodiments, the sensor may be, for example, a 32 MP/30 fps image sensor having pixels of approximately 0.5 μm with a total well capacity of approximately 1000 -e. The image sensor can be designed to have a readout speed of 10b/240-fps. Some embodiments of the image sensor may be a digitally integrated design with an 8-frame rolling shutter speed, for example, implementing an interleaved rolling shutter without any need for a full frame. In one example, data may be sent from an external memory, e.g., DRAM, at speeds of approximately 12b/30-fps. Such an image sensor can result in an equivalent pixel total well capacity multiplied by a factor of eight, for example, achieving a total well capacity of approximately 8000-e per pixel. These image sensor specifications represent only one embodiment of an image sensor utilizing the pixel readout system, and other image sensors with varying specifications may be used in other embodiments.

[0032] A pixel array may include a plurality of pixels arranged in a predetermined number of rows and columns (e.g., M rows and N columns). Each pixel may represent a singular charge sensing element of the pixel array. Each of the plurality of pixels may each include a photosensitive element, e.g., a photogate, photoconductor, photodiode, or other photodetector, overlying a substrate for accumulating charge generated by light on an underlying portion of the substrate. The pixel array may, in some embodiments, include one or more filters positioned to filter incoming light, for example, a cutoff filter or a color filter. For example, the photosensitive element of a CMOS pixel may be one of an exhausted p-n junction photodiode or a field-induced exhaustion region beneath a photogate.

[0033] A timing generator can provide timing signals to read values representing the light accumulated in each of the pixels of the pixel array. For example, the timing generator can be a column and row trigger. The timing generator may include control logic to control the reset operations, exposure time, line time, and pixel timing for the pixel array and may also provide timing signals to an analog/digital converter (ADC). The reading circuitry may provide a circuitry for reading each of the pixels in the pixel assembly. For example, the circuitry may include a plurality of row and column lines provided for the entire assembly. The column and row lines of the read circuit assembly may be electronically connected to the column sample and hold (S/H) circuit assembly, pixel circuit assembly, and row control circuit assembly that operate in accordance with with the timing provided by the timing generator. In operation, the pixels of each row in the pixel array can be switched on at the same time by a row selection line, and the pixels of each column can be selectively output by a column selection line.

[0034] Each pixel may include a set of circuits for reading a charge collected in each of the plurality of pixels. For example, one embodiment of the pixel array is connected to each pixel and includes an output field effect transistor formed on the substrate and a charge transfer section formed on the substrate adjacent to the pixel having a sensor node, typically a sensor node. floating diffusion, connected to the gate of an output transistor. The charge transfer section of the pixel circuitry may include at least one electronic component, e.g., a transistor, for transferring charge from the underlying portion of the substrate to the floating diffusion node and another electronic component, e.g., a transistor. reset to reconfigure the node to a predetermined load level prior to load transfer. The light charge can be amplified when it moves from the initial charge accumulation region to the floating diffusion node, and the charge at the floating diffusion node can be converted into a pixel output voltage by a source-follower output transistor. As discussed in greater detail below, the pixel circuitry may additionally include a storage capacitor or other electronic charge storage device for storing multiple charge dumps from a pixel or pixels in the analog domain. The storage capacitor may be positioned beyond the floating diffusion node in the pixel circuitry (with respect to the pixel position) in some embodiments, and may have a greater capacitance than that of the floating diffusion node. The storage capacitor may be on the same sensor chip or on the back chip of a pixel-to-pixel stack array connection in various embodiments.

[0035] After passing through the pixel circuitry, the pixel signals can be passed through an amplifier to increase the strength of the pixel signal (e.g., voltage or current). The timing generator, the pixel assembly, the pixel circuitry, and the amplifier together can perform the functions of: (1) converting photon to charge; (2) image charge accumulation; (3) charge transfer to the buoyant diffusion node accompanied by charge amplification; (4) reconfiguring the floating diffusion node to a known state before transferring charge to it; (5) selection of a pixel for reading; and (6) sending and amplifying a signal representing the pixel charge. The three-dimensional (3D) or shared-pixel stacked architecture described here can perform these functions while reducing pixel size and increasing the number of pixels in the same area, while increasing image speed, sensitivity, resolution, dynamic range, and color fidelity. pixel arrangement.

[0036] Figure 1A illustrates an embodiment of a shared pixel architecture 100 for use as a pixel of a pixel reading system, according to an illustrative embodiment. Some embodiments of the image sensor may be a solid-state image sensor, for example a CMOS image sensor, which has four 4-transistor (4T) pixels sharing the pixel arrangement and a compact layout. The 4T 100 shared pixel architecture may be used as the pixel architecture for pixels in the pixel array, in some embodiments. The 4 shared pixel architecture 4T 100 includes four pixels, and although many similar shared pixel architectures exist and can be arranged in the array in a similar manner, for simplicity only one 4 shared pixel architecture 4T 100 is illustrated in larger details.

[0037] The 4T 100 shared 4-pixel architecture includes four photodiode circuits in parallel. The photodiode circuits comprise photodiodes PD1-PD4 and their corresponding transfer ports TG1-TG4. Each of the photodiode circuits further comprises a timing circuit TS1-TS4 and a storage capacitor CS1-CS4 in series with respective photodiodes PD1-PD4 between photodiodes PD1-PD4 and a floating diffuse node. Individual storage capacitors CS1-CS4 for each of the photodiodes PD1-PD4 can be used to temporarily store the charge absorbed by each of the photodiodes PD1-PD4 before the charge is transferred to the floating diffusion node. The pixel readout system may comprise a floating diffusion node FD, reset transistor RST, voltage supply VDD, source follower amplifier SF_AMP, selector transistor SEL, output voltage node Vcol and current source Ibias. These elements can perform functions similar to those described above. Sharing the floating diffusion node RD, the source-following amplifier SF_AMP, the line selection transistor SEL, and the retuning transistor RST among the adjacent photodiodes PD1-PD4 and transfer gates TG1-TG4 assists in increasing the supply that is sensitive to light. The supply factor is increased due to the sharing of components between multiple pixel architectures, reduces the total number of transistors, capacitors and other components, coupled with a larger number of shared pixels in the 100 shared pixel architecture. components between a plurality of pixels reduces the pixel area filled with transistors and other components, and thus increases the pixel area that is sensitive to light. The illustrated architecture 100 results in approximately 2.0 transistors per pixel. Components can be shared across four separate photodiodes and associated transfer ports. In some embodiments, the shared components may be shared by eight separate photodiodes or 16 separate photodiodes or more separate photodiodes.

[0038] In some embodiments, the PD1-PD4 photodiodes may include a photodiode used to detect a red component of input light, two photodiodes used to detect a green component of the input light, and a photodiode used to detect a blue component of the input light. entrance light. Although not illustrated in this figure, the color representation described may follow the Bayer color standard, where a shared architecture comprises two green pixels diagonally and a red pixel diagonally with a blue pixel in a four-pixel architecture. In some embodiments, the floating diffusion node FD of Figure 1A may represent one or more floating diffusion nodes. For example, each photodiode circuit may have an individual floating diffusion node (not illustrated in this figure). In some embodiments, two or more photodiode circuits may share one or more floating diffusion nodes (not illustrated in this figure). However, as shown here, the one or more floating diffusion nodes can be combined into a single floating diffusion node FD in the figures for reasons of schematic simplicity.

[0039] Charge can be collected by each of the photodiodes PD1-PD4 as long as the corresponding transfer ports TG1-TG4 are turned off. Once the charges have accumulated on the photodiodes PD1-PD4, the charges accumulated on each of the photodiodes PD1-PD4 can be temporarily transferred to the respective storage capacitors CS1-CS4. For example, the charge that accumulates in the photodiode PD1 when the transfer gate TG1 is closed and the photodiode is exposed to light of the specified color, can be transferred to the storage capacitor CS1 when the transfer gate TG1 is opened. Once the charges are located on the CS1-CS4 storage capacitors, the TG1-TG4 transfer ports can be closed. In some embodiments, the CS1-CS4 storage capacitors may have greater charge capacities than the PD1-PD4 photodiodes, and the CS1-CS4 storage capacitors may receive multiple charge dumps from their respective PD1-PD4 photodiodes before the charges in the storage capacitors CS1-CS4 be transferred to the floating diffusion node FD. Charges can be additionally transferred to the floating diffusion node FD when respective timing circuits TS1-TS4 are activated while transfer ports TG1-TG4 are closed. In some embodiments, both transfer ports TG1-TG4 and timing circuits TS1-TS4 can be opened at the same time, thereby allowing both the charges accumulated in the photodiodes PD1-PD4 and the charges in the storage capacitors CS1- CS4 to accumulate at floating diffusion node FD. The individual storage capacitors CS1-CS4 and timing circuits TS1-TS4 allow the charges from the corresponding photodiodes PD1-PD4 to be transferred to the floating diffusion node FD individually.

[0040] Intermediate charge storage in storage capacitors CS1-CS4 between photodiodes PD1-PD4 and the floating diffusion node FD may be useful in discerning charge contributions from individual photodiodes PD1-PD4. Without the individual storage capacitors CS1-CS4, in some embodiments, a single shared storage capacitor or floating diffuse node FD may have difficulty supporting the multiple charge transfers from multiple photodiodes PD1-PD4 without losing signal and creating artifacts. When the charge is transferred directly from the PD1-PD4 photodiodes to the FD floating diffusion node after the charge/integration time, the FD floating diffusion node, which may comprise a parasitic capacitor within the silicon wafer of the PD1-PD4 photodiodes, may not retain enough charge to extend the dynamic range of a sensor with small pixels. Accordingly, the charge from photodiodes PD1-PD4 can be dumped several times onto their respective storage capacitors CS1-CS4 before the charges from each of the storage capacitors CS1-CS4 are read individually through the floating diffusion node FD to the set of reading circuits described above. Storage capacitors CS1-CS4, as described above, can be configured with an effective capacitance large enough to store multiple charge dumps from their respective photodiodes PD1-PD4, for example, eight or more charge dumps. In some embodiments, the total well capacity of a pixel can be effectively multiplied in the analog domain by the number of charge dumps stored in storage capacitors CS1-CS4. In some embodiments, the storage capacitors CS1-CS4 and the timing circuits TS1-TS4 are formed in the same layer as the photodiodes PD1-PD4 in the shared pixel architecture 100. In some embodiments, the storage capacitors CS1-CS4 and the Timing circuits TS1-TS4 can be formed in the second layer together with the remaining components of the readout circuitry.

[0041] In an example, where one or more of the transfer ports TG1-TG4, timing circuits TS1-TS4, and reset transistor RST are all turned on, the corresponding photodiode of the one or more photodiodes PD1-PD4, the one or more storage capacitors CS1-CS4, and the floating diffusion node FD can be reset depending on which TG1-TG4 and TS1-TS4 are activated. In some embodiments, the photodiodes PD1-PD4 and the storage capacitors CS1-CS4 may each be readjusted before being exposed to the light source. Charge integration into photodiodes PD1-PD4 can occur when the respective transfer ports TG1-TG4 are turned off, allowing photon charge to be collected on the corresponding photodiode PD1-PD4. Charge integration on storage capacitors CS1-CS4 can occur when respective timing circuits TS1-TS4 are off and respective transfer ports TG1-TG4 are open to allow charge from photodiodes PD1-PD4 to accumulate on the storage capacitors. CS1-CS4 storage.

[0042] In some embodiments, charge integration on photodiodes PD1-PD4 may occur when the respective transfer ports TG1-TG4, the timing circuits TS1-TS4, and the reset transistor RST are all turned off, allowing the charge of photons is collected in the corresponding photodiode PD1-PD4. By selectively connecting the transfer port TG1-TG4, the charge on the corresponding photodiode PD1-PD4 (e.g., one or more photodiodes PD1-PD4 having an associated transfer port turned on) is transferred to the floating diffusion node FD through the capacitors storage circuits CS1-CS4 and timing circuits TS1-TS4. In some embodiments, one or more transfer ports TG1-TG4 and timing circuits TS1-TS4 may be connected simultaneously to transfer charge directly from the associated photodiodes PD1-PD4 directly to the floating diffusion node FD without storing the same in the charge capacitors. CS1-CS4 storage. When a row or column of photodiodes PD1-PD4 is selected to be read by activating the SEL transistor, the charge stored in the floating diffusion node FD is converted to a voltage through the SF_AMP amplifier. This reading voltage can be transferred to the Vcol output. In some embodiments, the charge stored in one of the storage capacitors CS1-S4 can be converted to a voltage through the amplifier SF_AMP when the respective timing circuits TS1-TS4 are turned on, and this readout voltage can be transferred at the Vcol output. In some embodiments, if desired, the charge stored in one of the photodiodes PD1-PD4 can be converted to a voltage through the amplifier SF_AMP when the respective transfer ports TG1-TG4 and the timing circuits TS1-TS4 are turned on.

[0043] In some embodiments, timing circuits TS1-TS4 may include high-speed logic to regulate the number of charge dumps sent from photodiodes PD1-PD4 to storage capacitors CS1-CS4 and to determine when to open to allow the charge on the respective storage capacitors CS1-CS4 to be read through the floating diffusion node. In some embodiments, only one storage capacitor of the CS1-CS4 storage capacitors can be read by the read circuitry at a time. In this way, timing circuits TS1-TS4 can be coordinated so that no two are opened together. By accumulating multiple charge dumps of PD1-PD4 photodiodes in the analog domain, device power can be saved compared to accumulating multiple charge dumps of PD1-PD4 photodiodes in the digital domain. Sequential reading of PD1-PD4 photodiodes using TS1-TS4 timing circuits and readout circuitry can control the reading of PD1-PD4 photodiodes to increase resolution compared to parallel scanning. Due to the high-speed logic of the TS1-TS4 timing circuits, high video frame rates (e.g., 30 fps at 8 MP full resolution) can still be achieved while sampling each PD1-PD4 photodiode in the multiple pixel array. times in the analog domain, for example eight readings per pixel per frame. In some embodiments, the timing scheme may be a transistor with a line width of approximately 20 nm.

[0044] Figure 1B illustrates an embodiment of an interleaved architecture of four transistors and 4 shared pixels, generally designated as a first architecture 105, according to an illustrative embodiment. As illustrated in Figure 1B, there are four photodiodes PDR1, PDR2, PDG1, and PDG3 (or similar structures or devices), with a pair of photodiodes for a first color, e.g., red (PDR1 and PDR2), and a second pair of photodiodes for a second color, for example, green (PDG1 and PDG3). These photodiodes PDR1, PDR2, PDG1 and PDG3 can correspond to the photodiodes PD1-PD4 as referred to in figure 1A. As described above, each of the photodiodes PDR1, PDR2, PDG1 and PDG3 has a dedicated transfer port TG1-TG4 to control the integration time of the charges in each of the respective photodiodes PDR1, PDR2, PDG1, PDG3. Thus, the TG1 transfer port controls charge integration and transfer in the PDR1 photodiode, while the TG2 transfer port controls the charge integration and transfer in the PDR2 photodiode. Similarly, the TG3 and TG4 transfer ports in Figure 1B control the integration and charge transfer in the PDG1 and PDG3 photodiodes, respectively. As discussed above, the three transistors illustrated between the PDR1-PDR2 and PDG1-PDG3 photodiode pairs are shared between the four photodiodes PDR1, PDR2, PDG1 and PDG3. The transistor at the top of this column of transistors is the SF_AMP amplification transistor, the middle transistor is the SEL selection transistor, and the bottom transistor is the RST reset transistor. Two floating diffusion nodes FD1 and FD2 are illustrated, FD1 being located between photodiodes PDR1 and PDG1 and the amplification transistor SF_AMP and FD2 being located between photodiodes PDR2 and PDG3 and the amplification transistor SF_AMP. In some embodiments, the two floating broadcast nodes FD1 and FD2 may be combined into a single floating broadcast node or divided into additional floating broadcast nodes. Not illustrated in the shared pixel circuitry is the timing circuitry TS and the storage capacitor CS, although in some embodiments, these two components may be included in the shared pixel circuitry.

[0045] Photodiodes PDR1 and PDR2 are the two photodiodes in the leftmost column of the schematic in Figure 1B. Photodiodes PDR1 and PDR2 are configured to perceive red light. Thus, when red light is perceived, photodiodes PDR1 and PDR2 each generate a charge in response to the amount of red light perceived over a period of time. Similarly, photodiodes PDG1 and PDG3 are two photodiodes in the rightmost column and are each configured to perceive green light, each generating a charge when green light is perceived. The central column comprises the shared transistors SF_AMP, SEL and RST and the shared floating diffusion points FD1 and FD2. SF_AMP, as described above, can be configured to convert the load input of one of the photodiodes PDR1, PDR2, PDG1 and PDG3 into corresponding voltage signals to be output during a readout sequence. The SEL selection transistor may be configured to select a single row of the pixel array to be read (or sent) as described above and may allow the SF_AMP amplification transistor to convert a charge to a voltage when a particular row or column is selected. Finally, the reset transistor RST can be configured to release (or set to a reference point) the charge of each of the photodiodes PDR1, PDR2, PDG1, and PDG3 and the floating diffusion nodes FD1 and FD2. To reset photodiodes PDR1, PDR2, PDG1, and PDG3, the reset transistor RST may need to be switched on in conjunction with transfer ports TG1, TG2, TG3, and TG3, respectively.

[0046] Figure 1C illustrates an embodiment of two shared four-transistor and 4-pixel architectures from Figure 1B in an interlaced pixel architecture set, according to an illustrative embodiment. A first architecture of 4 transistors and 4 shared pixels may correspond to the first architecture 104 from Figure 1B. A second four-transistor, four-shared-pixel architecture may be presented as a second architecture 110. As described above with respect to Figure 1B, the first four-transistor, four-shared-pixel architecture 105 on the left comprises photodiodes PDR1, PDR2, PDG1, and PDG3. along with SF_AMP, SEL and RST transistors and floating diffusion nodes FD1 and FD2. Similarly, the second shared 4-transistor, 4-pixel architecture 110 on the right comprises photodiodes PDB1, PDB2, PDG2, and PDG4 along with transistors SF_AMP1, SEL1, and RST1 and floating diffusion nodes FD3 and FD4. The components of the second shared 4-transistor, 4-pixel architecture 110 function in the same way as the components described above with respect to Figures 1A and 1B, with photodiodes PDB1 and PDB2 being configured to generate a current in response to perceived blue light. PDG2 and PDG4 of the second shared four-transistor, four-pixel architecture generate current signals in response to exposure to green light in addition to those generated by PDG1 and PDG3. The floating diffusion node FD3 can be located between the photodiodes PDB1 and PDG1 and the amplification transistor SF_AMP1 and FD4 can be located between the photodiodes PDB2 and PDG4 and the amplification transistor SF_AMP1.

[0047] The combination of the two architectures of 4 transistors and 4 shared pixels 105, 110 can provide a color representation following the Bayer color standard, where each full unit comprises two green pixels (e.g., a green odd pixel and a green odd pixel green pair) diagonally paired with the blue pixel and the red pixel diagonally. Accordingly, in some embodiments, PDG1 and PDG3 may be referred to as green odd photodiodes while PDG2 and PDG4 may be referred to as green even photodiodes. In some embodiments, other colored patterns may be used in an interlaced set; selection among various colored patterns may depend on at least one application of the pixel array.

[0048] The shared components in the central column of the second architecture 110 comprise the transistors SF_AMP1, SEL1 and RST1 and the floating diffusion points FD3 and FD4. SF_AMP1, as described above, can be configured to convert the load input of one of the photodiodes PDB1, PDB2, PDG2 and PDG4 into corresponding voltage signals to be read. The selection transistor SEL2 may be configured to select a single row from the pixel array of the second architecture 110 to be read (or sent), as described above. Finally, the reset transistor RST1 can be configured to release the charge from each of the photodiodes PDB1, PDB2, PDG2, and PDG4 and floating diffusion nodes FD3 and FD4. To release the charge from each of the photodiodes PDB1, PDB2, PDG2 and PDG4, the respective transfer ports TG1_1, TG2_1, TG3_1 and TG4_1 can be activated together with the reset transistor RST1.

[0049] Figure 2 shows the architectures of four transistors and four shared pixels 105 and 110 of Figures 1B and 1C in an interlaced pixel architecture set designated interlaced set 200, according to an illustrative embodiment. Figure 2 can show how the interlaced architectures 105 and 110 of Figures 1B and 1C can physically align. For example, the four-transistor, four-pixel shared architectures 105 and 110 of Figure 1C are illustrated forming the interlaced set 200 of six four-transistor, four-pixel shared architectures (three each of both 105 and 110). For example, the first row of shared 4-pixel architectures might be the 105 pixel architecture, while the second row of shared four-pixel architectures might be the 110 pixel architecture. Although not individually labeled as such in this figure, each of the six shared four-transistor, four-pixel architectures comprises the components described above with respect to Figures 1B and 1C (e.g., each comprising four photodiodes (not individually labeled in this figure), four transfer gate transistors (not individually labeled in this figure), figure)). The transfer gate transistors and the reset and selection transistors of each of the four-transistor, four-pixel shared architectures are additionally coupled to the buses indicated on the left side of Figure 2. The embodiment illustrated in Figure 2 features twelve buses associated with six signals, each of the six signals being communicated on two separate buses.

[0050] The two separate buses for each signal can be used to communicate with separate shared pixel architectures due to the interlaced representation in the array, where the photodiodes and transistors of adjacent pixel architectures forming the interlaced array 200 are not all aligned in a united horizontal direction. For example, the transistors for each shared 4-pixel architecture 105 may not be a single row horizontally across the array and are instead separated into alternating rows of PDRm and PDGn red and green paired photodiodes, where m represents the number of PDX photodiode being presented and n represents the number of PDX photodiode being presented, respectively, and blue and green odd photodiodes PDBm and PDGn, respectively. Thus, due to the interlaced assembly 200, the TG1_m transistors of two adjacent shared 4-pixel architectures 105 and 110 may not be in a single row, but instead in two rows offset from each other. Accordingly, two buses are used to communicate the TG_1 signal to all TG1_m transistors of a given row of adjacent shared 4-pixel architectures 105 and 110. Similarly, two buses are used to communicate the signals TG_2, TG_3, TG_4, SEL and RES for all respective transistors of a given "row" of 4 adjacent shared pixel architectures, where, as described above, the adjacent shared pixel architectures 105 and 110 of the interlaced set 200 are offset from each other. This horizontal bus architecture can switch across the array vertically so that each shared pixel architecture 105 and 110 of the interlaced array 200 can connect to each of the busses for respective transistors. Accordingly, the transfer ports of Figures 1B and 1C above are coupled to the TG_1 and TG_2 bus lines of Figure 2, respectively. Similarly, the transfer ports of Figures 1B and 1C above are coupled to the TG_3 and TG_4 bus lines of Figure 2, respectively. The reset transistors of the shared four-transistor, four-pixel architectures 105 and 110 of Figure 2 are each coupled to the RST reset bus line. Similarly, the selection transistors of the shared 4-transistor, 4-pixel architectures 105 and 110 of Figure 2 are each coupled to the SEL selection bus line.

[0051] Additionally, the amplification transistors and the selection transistors are each additionally coupled to one of the vertical channels indicated at the top and bottom of figure 2. Figure 2 shows reading channels that read a voltage corresponding to the stored charge in the photodiodes. The readout channels alternate in ascending/descending directions, where each of the photodiodes of a shared 4-transistor, 4-pixel architecture 105 and 110 is connected to the readout channel 205, while the shared architecture 110 is coupled to the readout channel 210 The read channel 205 comprises pbus_y1 and pvh_y1, where the voltage from pbus_y1 is transferred to pvh_y1 through the selection transistor and the amplification transistor based on the charge within the photodiode being read when the line selection transistor is active and the. transfer gate transistor is active for the particular photodiode. These readout channels may each be coupled to the shared amplification and selection transistors of the shared pixel architectures so that charges from the photodiodes of the shared pixel architectures 105 and 110 through the interlaced array 200 are sent through the readout channels. 205 and 210. In this way, each pair of readout channels can be configured to send two-column signals from the shared pixel architectures 105 and 110 of the interlaced array 200.

[0052] Each of the read signal channels of the pair of read channels described above can be dedicated to a specific pair of colors. For example, in Figure 2, the read channel pvh_y1/pbus_y1 can be dedicated to reading signals from the red photodiodes and the green photodiodes pairs, while the read channel pvh_y2/pbus_y2 can be dedicated to reading signals from the blue photodiodes and photodiodes green oddballs. In some embodiments, the readout channels may be arranged along the interlaced array 200 such that the readout channel/photodiode color correlation is maintained. Additionally, in order to obtain a 1-color reading per channel where the channels, as described above, are dedicated to a shared pixel architecture having two-color photodiodes, individual colors of the coupled shared pixel architecture are read at specific times. In this way, each read channel of the pair of read channels can be configured to read according to a timing scheme, alternating between the two photodiode colors of the coupled shared pixel architecture 105 or 110, so that a single color is read on the channel at a particular time. Such a timing scheme is described in greater detail below with reference to Figures 3A, 3B, 6A and 6B.

[0053] In the working interlaced set 200, each photodiode of each shared pixel architecture 105 and 110 can generate a charge when exposed to their respective colors of light. However, while the respective transfer port associated with the photodiode generating the charge is closed, the charge is not transferred away from the photodiode. For example, when photodiode PD1 in Figure 1A is exposed to red light, photodiode PD1 can generate a charge. While the TG1 transfer port is closed, charge cannot be transferred away from the PD1 photodiode and is instead integrated (e.g. accumulates) in the PD1 photodiode. When the TG1 transfer port receives a signal on the TG_1 bus, the TG1 transfer port can open, allowing the charge from the photodiode PD1 to be transferred to the floating diffusion node FD1. The floating broadcast node FD1 can store the payload received from PD1 over time. The floating diffusion node FD1 can be reset if the reset transistor RST receives a reset signal from the RST bus, or it can alternatively send the integrated load through the amplification transistor SF_AMP in response to the selection transistor SEL receiving a signal. SEL bus selection. In some embodiments, although not illustrated, the floating diffusion node FD1 may transfer the stored charge to a storage capacitor CS1. When the SEL selection transistor receives a selection signal, the SF_AMP amplification transistor can convert the integrated load to be sent on the pvh_y1/pbus_y1 readout channel. This process can be applied in a similar way to each PD photodiode of the shared pixel architecture 105 and 110 so that the readout channel can be dedicated to a single color at any given time.

[0054] The shared pixel architecture 105 and 110 shown in Figures 1B-2 can provide several advantages with respect to the representation and architecture presented. For example, vertical scan channels may provide a reading of 1 color per channel when readings are taken according to a timing scheme. In a 1 color per channel reading, each color has a dedicated channel at a given time. As illustrated in Figure 2, the first shared four-pixel architecture can comprise red photodiodes PDR1 and PDR2 with green odd photodiodes PDG1 and PDG3. In this way, the vertical read channel 205 can be dedicated to a single color when paired with a timing scheme that alternates between reading the red photodiodes PDR1 and PDR2 and the green odd photodiodes PDG1 and PDG3. This way, the odd green and red colors have a dedicated channel when they are being read. The same applies to the green and blue paired photodiodes PDG2, PDG4, PDB1 and PDB2.

[0055] Reading one color per channel provided by the architecture of 4 colored pixels 105 and 110 may have its own advantages, including the ability to distribute signals with lower noise and higher gain than signals distributed across channels shared by more than one color . This may result from each channel being completely separate from other channels, allowing changes to one channel to be maintained independent of other signals. Additionally, one color per channel can provide lower fixed pattern noise than embodiments where multiple colors share a channel, as the photodiodes are not combined into a single channel, and offset and gain error corrections can be applied. regardless of color. Additionally, reading one color per channel can result in smaller areas and shared line control for the shared pixel architecture 105 and 110 and thus the interlaced array 200. Color-separated channels can also provide parallel processing capabilities. , so that high-resolution devices (e.g. HD cameras and digital SLR cameras) can process the high resolutions at a high data rate. Additionally, temporal noise can be reduced by separate channels as smaller capacitors (e.g., storage capacitors) can be used, which contribute to temporal noise.

[0056] Table 1 compares the interlaced shared pixel architecture described here with non-interlaced shared pixel architectures.

[0057] Table 1:

[0058] As illustrated by Table 1, previous shared architectures have been more limited than the integrated shared architectures described here. As illustrated in Table 1, a 2 x 2 shared pixel architecture can provide an average of 3 horizontal lines per pixel, one average vertical line per pixel, no vertical bins, 0.5 output colors per column, one read circuit per column and no single channel capability per color. A 2 x 2 transfer port shared pixel architecture can provide an average of 2 horizontal lines per pixel, one average vertical line per pixel, no vertical bins, 0.5 output colors per column, one read circuit per column, and no single channel capability per column. A shared 4 x 1 pixel architecture can provide an average of 1.5 horizontal lines per pixel, 2 average vertical lines per pixel, vertical binning, 1 output color per column, one read circuit per column, and no channel capacity single by color. An integrated shared pixel architecture can provide an average of 3 horizontal lines per pixel, 2 average vertical lines per pixel, vertical binning, 1 output color per column, 2 read circuits per column, and single channel capability per color. An integrated transfer port shared pixel architecture can provide an average of 2 horizontal lines per pixel, 2 average vertical lines per pixel, vertical binning, 1 output color per column, 1 read circuits per column, a single channel capacity by color.

[0059] Figure 3A illustrates a 4-color reading sequence per channel of a 1 x 4 interlaced 4 shared pixel architecture, according to an illustrative embodiment. Figure 3A presents an example of an arrangement of red, blue and green pixels in a Bayer configuration. Each of the pixels in the set can be assigned according to its respective row and column number, [r, c], where "r" represents the row number and "c" represents the column number. For example, pixel [0,0] may correspond to pixel Gr in the upper left corner of the set, where the top row is row 0 and the leftmost column is column 0. Each column and row of pixels in the set comprises two pixel colors in an alternating manner. For example, row [0] comprises green Gr pixels and red R pixels, while row [1] comprises blue B pixels and green Gb pixels. Similarly, column [0] comprises green Gr pixels and blue B pixels, while column [1] comprises red pixels R and green pixels Gb. Additionally, each pixel is coupled to a vertical read channel of the plurality of vertical read channels 305 (upward) and 310 (downward). The vertical readout channels 305a-305c may correspond to the vertical readout channels 205, while the vertical readout channel 310a-310c may correspond to the vertical readout channels 210, as referred to in Figure 2. In the architecture of 4 interlaced shared pixels 1 x 4 as illustrated, the green Gr and green Gb pixels are coupled to the same downstream readout channels 310a-310c, while the red R and blue B pixels are coupled to the same upstream readout channels 305a-305c. On the left side of the pixel array, representative signals TG_1, TG_2, TG_3 and TG_4 are illustrated, each corresponding to one of lines 0, 1, 2 and 3, respectively. The TG_1, TG_2, TG_3 and TG_4 signals may correspond to signals received on buses of the same designation as referred to in figure 2. Accordingly, when the TG_1 bus indicates a signal to the TG1 transfer ports, the pixels of the line to which the ports transfer signals TG1 are connected (here, line 0) are read vertically.

[0060] The diagram illustrates how color pixel charges are read from the shared pixel architecture and "dumped" onto sample and hold capacitors in parallel and subsequently removed sequentially based on the SEL select signal (not illustrated in this figure). and the transfer gate signals TG_1-TG_4. As illustrated by the embodiment in Figure 3A, each color is read as a separate color channel when read according to a timing scheme, thus allowing each color channel to have a different gain applied to it to achieve a fidelity of desired color and/or white balance (e.g., different color processing per channel is available, as discussed above). When the TG_1 signal is received by the respective transfer port TG1, the pixels in line 0 can be read on their corresponding readout channels 305 and 310. In this way, a readout of the pixels in line 0 can result in the pixel Gr [0,0 ] being read by the downward read channel 310a, the pixel R[0,1] being read by the upward read channel 305b, the pixel Gr[0,2] being read by the downward read channel 310b, the pixel R[0, 3] being read by the upward read channel 305c, and the pixel Gr [0,4] being read by the downward read channel 310c. Similarly, the remaining lines 1 to 3 can be read within the sample and hold capacitors. In some embodiments, each read channel 305a-305c and 310a-310c may feed into a separate sample and hold capacitor. In some other embodiments, the sampling and holding capacitors may be shared between two or more readout channels 305a-305c and 310a-310c.

[0061] The diagram further illustrates the sequence of channel reads separated by corresponding line numbers, referred to as banks 306 and 311. For example, in bank 306, the first up read channel 306a collects the charges from the blue pixels of column 0 , as illustrated by the first column of loads read {drop, B[1,0], drop, B[3,0]}. "Discarded" charges are charges that are ignored since there is no pixel to be read. For example, line 0 read into upstream read channel 305a may be discarded since there is no column of pixels to the left of upstream read channel 305a, so upstream read channel 305a reads a value that does not correspond to a charge from an existing pixel. Accordingly, values that are read that do not match existing pixel loads can simply be discarded or ignored. The charges B[1,0] and B[3,0] represent the charges of two blue pixels in column 0 in figures 1 and 3, respectively.

[0062] Similarly, the upward read channel 306b reads charged {R[0,1], B[1,2], R[2,1], B[3,2]}, collecting the red and blue charges from both columns 1 and 2 and upstream read channel 305c collects the red and blue charges from both columns 3 and 4, resulting in {R[0,3], B[1,4], R[2,3 ], B[3,4]}. In this way, the sequence of channel reads separated by corresponding line numbers indicates which pixel was read by a particular channel. For example, as indicated in Figure 3A, for line [0], the read channel 305a has a dropped charge value, the read channel 305b has a red pixel charge at [0,1], the read channel 305c has the red pixel charge at [0,3], and the read channel 305d (not illustrated in this figure) has the red pixel charge at [0,5]. The sequence of channel reads for the remaining lines 1-3 for up-read channels 305a-305d and lines 0-3 for down-read channels 310a-310c present load sources in a similar manner. The sequence of channel reads for downstream read channels 310a-310c can be illustrated in bank 311.

[0063] As illustrated in Figure 3A, the charges on the pixels can be read in parallel across each column, as each column for a given row receives only one charge from a single color pixel to be stored in the sample and hold capacitors. related. Subsequently, the charges on the sample and hold capacitors are changed sequentially. In order to maintain the Bayer pattern group in read payloads, the data needs to be correctly aligned, or read according to a certain pattern or time sequence. For example, the odd rows of bank 306 may be delayed by a "horizontal" clock (e.g., a pixel time), while the even and odd rows of bank 311 may also be delayed by a "horizontal" clock. Since the charge is changed sequentially from the sample and hold capacitors, the remaining reading process is similar to that of a 1 x 4 linear structure.

[0064] Vertical sharing as illustrated in Figure 3A is similar to the traditional vertical, shared, interlaced pixel architecture. Additionally, the shared architecture is capable of compartmentalizing the load in both horizontal and vertical directions. Charge compartmentalization can be important as it allows charge on more than one pixel/photodiode to be combined in one or both horizontal and vertical directions in the analog domain. This charge compartmentalization thus amplifies the charge capacity (e.g., the total available charge) that can be saved from the photodiodes. The pixel-level compartmentalization made available by the interlaced shared pixel architecture can provide better low-light performance where capturing and displaying the full resolution of an image can be difficult. Charge compartmentalization can amplify the output level by combining the horizontal and vertical pixel outputs. For example, with respect to the interlocking shared-pixel architecture 105 and 110 illustrated in Figures 1B-2, the adjacent red, blue, odd-green, and even-green photodiodes illustrated in each four-transistor, four-shared-pixel architecture 105 and 110 may be combined. into a single pixel output when combined with suitable timing schemes (e.g., horizontal binning) and then combined vertically with outputs from other shared four-transistor, four-pixel architectures (e.g., vertical binning). Such compartmentalization can be useful in "preview modes" as provided on various imaging devices, where, since the previous modes tend to display an image at a reduced resolution, the preview mode generated by a set of architectures of interlaced shared pixels can have a higher resolution than those generated by non-interlaced shared pixel architectures.

[0065] Figure 3B illustrates a 4-color reading sequence per channel of a 2 x 2 interlaced 4 shared pixel architecture, according to an illustrative embodiment. Figure 3B presents an example of an arrangement of red, blue and green pixels in a Bayer configuration. Each of the pixels in the set can be referred to according to its respective row and column number, [r,c], where "r" represents the row number and "c" represents the column number. For example, pixel [0,0] might correspond to pixel Gr in the upper left corner of the set, where the top row is row 0 and the leftmost column is column 0. Each pixel can be coupled to a channel vertical reading among the plurality of vertical reading channels 355 (ascending) and 360 (descending). The vertical readout channels may correspond to the vertical readout channels 205 and 210 as referred to in Figure 2. In the 2 x 2 interlaced 4 shared pixel architecture as illustrated, the green Gr and red R pixels are coupled to the same upward readout channels 355a -355d, while the green Gb and blue B pixels are coupled to the same downstream readout channels 360a-360c. On the left side of the pixel array are illustrated representative signals TG_1, TG_2, TG_3 and TG_4, each corresponding to one of lines 0, 1, 2 and 3, respectively. The TG_1, TG_2, TG_3 and TG_4 signals may correspond to signals received on buses of the same designation as referred to in figure 2. According to when the TG_1 bus indicates a signal to the TG1 transfer ports, the pixels of the line to which the ports transfer signals TG1 are connected (here, line 0) are read vertically.

[0066] The diagram illustrates how the colored pixel charges are read from the shared pixel architecture and "dumped" into sample and hold capacitors in parallel and subsequently changed sequentially based on the SEL selection signal (not illustrated in this figure). and transfer gate signals TG_1-TG_4, according to a timing scheme (not illustrated in this figure). When the TG_1 signal is received by the respective transfer port TG1, the pixels in line 0 can be read on their corresponding readout channels 355 and 360. In this way, a readout of the pixels in line 0 can result in the pixel Gr [0,0 ] being read by the up-read channel 355a, the pixel R[0,1] being read by the up-read channel 355b, the pixel Gr[0,2] being read by the up-read channel 355b, the pixel R[0, 3] being read by the upward read channel 355c, and the pixel Gr [0,4] being read by the upward read channel 355c. Similarly, the remaining lines 1-3 can be read from the up and down sample and hold capacitors. In some embodiments, each read channel 355a-355d and 360a-360c may feed into a sample and hold capacitor. In some other embodiments, the sampling and holding capacitors may be shared between two or more readout channels 355a-355d and 360a-360c. Accordingly, in the 2 x 2 interlaced 4 shared pixel structure, each row of pixels is read on alternate read channels. Single channel per color can be maintained by reading specific color pixels at specific times, so that only red pixels can be read vertically at a given time, while green GR pixels are read vertically in the same channel at a different time.

[0067] The diagram further illustrates the sequence of channel reads separated by corresponding line numbers, referred to as banks 356 and 361. For example, in bank 356, the first up read channel 355a collects charges from the green Gr pixels of column 0 , as illustrated by the first column of loads read {discard, Gr[0,0], discard, Gr[2,0]}. "Discarded" charges are charges that are ignored since there are no pixels to be read. For example, line 0 read for upstream read channel 305a may be discarded since there is no column of pixels to the left of upstream read channel 305a, so that upstream read channel 305a reads a value that does not correspond to a charge from an existing pixel. Accordingly, values that are read that do not match existing pixel loads can simply be discarded or ignored. The charges Gr[0,0] and GR[2,0] represent the charges of two green pixels Gr in column 0 in rows 0 and 2, respectively.

[0068] Similarly, the upward read channel 305b reads the charges {R[0,1], Gr[0,2], R[2,1], Gr[2,2]}, collecting the red charges and green Gr from both columns 1 and 2, and the up-read channel 305c collects the red and green charges Gr from both columns 3 and 4, resulting in {R[0,3], Gr[0,4], R[2,3], Gr[2,4]}. In this way, the sequence of channel reads separated by corresponding line numbers indicates that the pixels were read by a particular channel. For example, as indicated in Figure 3B, for line[0], read channel 305a had a discarded charge value, read channel 305b had a red pixel charge at [0,1], the read channel 305c presented a red pixel charge at [0,3] and the readout channel 305d (not illustrated in this figure) presented the red pixel charge at [0,5]. The sequence of channel reads for the remaining lines 1-3 for the up-read channels 305-through 305d and lines 0-3 for the down-read channels 310a-310c present charge sources in a similar manner. The sequence of channel reads for downstream read channels 310a-310c can be illustrated in bank 361.

[0069] As illustrated in Figure 3B, the charges on the pixels can be read in parallel through each column, as each column for a given row receives a charge from two colored pixels to be stored in the respective sampling and retention capacitors. Subsequently, the charges on the sample and hold capacitors are changed sequentially. In order to maintain the Bayer pattern group in read loads, the data needs to be correctly aligned, or read according to a certain pattern or time sequence. For example, the odd rows of bank 356 can be delayed by a "horizontal" clock, while the even and odd rows of bank 361 can also be delayed by a "horizontal" clock. Since the charge is changed sequentially from the sampling capacitors and retention, the remaining reading process is similar to that of a 2 x 2 (non-interlaced) square structure.

[0070] The reconfiguration and readout schemes and sequences for two architectures shown in Figures 3A and 3B are similar despite being applied to different physical designs for locating and routing buses and pixel control components (e.g., transfer ports, adjustment, selection and amplification transistors).

[0071] Figure 4A illustrates an embodiment of an interlaced shared 4-transistor 8-pixel image sensor architecture 400 having a pixel reading system, according to an illustrative embodiment. Some embodiments of the image sensor may be a solid-state image sensor, for example, a CMOS image sensor, which has eight 4-transistor (4T) pixels sharing the pixel circuitry and a compact representation. The 4T 400 shared 8-pixel architecture may be used as the pixel architecture for the pixels in the pixel array, in some embodiments. The 4T 400 shared 8-pixel architecture includes eight pixels, and although many of these pixels are arranged in the array, for simplicity only one 4T 400 shared 8-pixel architecture is illustrated in greater detail.

[0072] The 4T 400 shared 8-pixel architecture includes eight photodiode circuits, an FD floating diffusion node, an RST retuning transistor, a VDD voltage supply, an SF_AMP source follower amplifier, an SEL selector transistor, a of output voltage Vcol and a current source Ibias. In some embodiments, the photodiode circuits may each comprise a photodiode PD1-PD8, a transfer gate TG1-TG8, a storage capacitor CS1-CS8, and a timing circuit TS1-TS8. As mentioned above, in some embodiments, the floating diffusion node FD may represent one or more floating diffusion points dedicated to a photodiode circuit or shared among multiple photodiode circuits. The components of the readout circuit set shown in Figure 4A can perform similar functions as described above with respect to Figures 1A - 2. These components can be shared by the 8 separate photodiode circuits having their associated photodiodes PD1-PD8, transfer ports TG1 -TG8, CS1-CS8 storage capacitors and TS1-TS8 timing circuits. Sharing the floating diffusion node FD, source follower amplifier SF_AMP, line selection transistor SEL, and retuning transistor RST among adjacent photodiode circuits (e.g., in series) assists in increasing the supply factor of the pixel, the supply factor representing the percentage of the pixel area that is sensitive to light. The illustrated architecture 400 results in approximately 1.5 transistors per pixel. In some embodiments of the PD1-PD8 photodiodes, two photodiodes may be used to detect a red component of the input light, four photodiodes may be used to detect a green component of the input light, and two photodiodes may be used to detect a blue component. of the incoming light, according to a Bayer color standard.

[0073] As described above, in some embodiments the timing circuits TS1-TS8 of the photodiode circuits may include high-speed logic to regulate the number of charge dumps sent from the photodiodes PD1-PD8 to the storage capacitors CS1-CS8 and to determine when to open to allow the charge on the respective storage capacitors CS1-CS8 to be read through the floating diffusion node. In some embodiments, only one storage capacitor of the CS1-CS8 storage capacitors can be read by the read circuitry at a time. In this way, timing circuits TS1-TS8 can be coordinated so that no two are opened together. By accumulating multiple charge dumps from photodiodes PD1-PD8 in the analog domain, device power can be saved compared to accumulating multiple charge dumps from photodiodes PD1-PD8 in the digital domain. from the storage capacitors CS1-CS8 through the floating diffusion node FD, through the source follower SF_AMP and through the selection transistor SEL to the output voltage node Vcol.

[0074] Figure 4A also illustrates an embodiment of partitioning the pixel array and pixel circuitry into separate stacked structures (e.g., silicon wafers). A stacked structure may be desirable where the number of components and overall presentation of the shared pixel architecture limits the area available for light absorption. For example, with reference to Figures 1B and 2, all components shown can be located on the same layer (e.g., the same silicon part). As can be seen, the limited area can be easily filled with shared components and individual PD photodiodes, TG transfer gates, CS storage capacitors, and TS timing circuits. As discussed above, the large number of components reduces the amount of light capable of reflecting from or being blocked by these components and structures coupling the components in the area of the PD photodiode. Additionally, as more components (e.g., transistors, contacts or buses) are introduced into the interlaced array architecture of shared pixels coplanar with the PD photodiodes, less space may be available and more light may be blocked and prevented from reaching the PD photodiodes. where stacking is not used.

[0075] Alternatively, the components of the shared pixel architecture may be separated into different layers in a stacked pixel structure. For example, a first part including the photodiodes PD1-PD8, the corresponding transfer gates TG1-TG8, the corresponding storage capacitors CS1-CS8, the corresponding timing circuits TS1-TS8, and the floating diffusion node FD can be replaced on a 410 photodiode wafer configured to integrate the input light load. A second part including the RST reset transistor, the VDD voltage supply, the SF_AMP source follower amplifier, the SEL selector transistor, the Vcol output voltage node, and the Ibias current source can be replaced on an assembly wafer. of pixel circuitry 420. In some embodiments, the pixel circuitry wafer 420 may be built on top of the photodiode wafer 410 opposite the side exposed to input light. Accordingly, the surface space for sensing incoming light can be increased through both the space-saving space of the shared pixel architecture in addition to the separation of the photodiodes and the pixel circuitry on different wafers. When the pixel circuitry components and structures are located on an individual layer (e.g., the pixel circuitry wafer 420), more real state is available for absorption of incoming light on the photodiode wafer 410.

[0076] Depending on the shared pixel architecture used, the division of components may change, and/or the connection points between the various layers may change. For example, in the interlaced shared pixel architecture, the connection points between the lower and upper layers can be the floating diffusion nodes. For example, in some embodiments, the timing circuitry TS and the source follower amplifier SF_AMP of the pixel circuitry wafer 420 may be connected to the floating diffusion node FD of the photodiode wafer. In some other embodiments, for example, the 2 x 2 shared pixel architecture, the connection points may be row/column interconnections.

[0077] The separation or partition of the shared architecture in the three-dimensional stack configuration is not a trivial matter. The relocation of components between the various layers may be limited by current technology (e.g., the determination between fusion bonds or fine-pitch hybrid bonds, as discussed below), and the partitioning and location of the various components may impact performance. of shared pixel architecture. For example, the signal-to-noise ratio, load capacity, or how well background noise can be suppressed can each be impacted by the partitioning of components between the various 3D layers.

[0078] In one embodiment, the photodiode wafer 410 may be configured as a back-side illuminated image sensor (BSI), where the photodiodes PD1-PD8, the transfer ports TG1-TG8, the storage capacitors CS1-CS8 and the TS1-TS8 timing circuits described above are integrated into the BSI image sensor. The BSI image sensor may have a structure attached to it to provide support for the BSI image sensor, which may have inferior structural integrity due to manufacturing and design constraints (e.g., due to the BSI image sensor needing to be very thin to allow light to penetrate the silicon substrate, the BSI image sensor wafer may be fragile and susceptible to damage). In some embodiments, the structure supporting the BSI image sensor wafer may be a "dummy" or "blank" silicon wafer, accordingly, components located on the wafer of pixel circuitry 420 may be integrated into the wafer. bracket used to provide structural support for the BSI image sensor. In this way, the BSI image sensor can be designed to be more sensitive to light, where the electrical components used to generate and read signals in response to perceived light can be located more efficiently structurally. In some embodiments, components indicated as being on photodiode wafer 410 or pixel circuitry wafer 420 may be manipulated or changed so that different components are on different wafers than those illustrated in Figure 4A. For example, in some embodiments, components of the shared pixel architecture may be separated between the photodiode wafer 410 and the pixel circuitry wafer 420 based on whether they have similar electrical characteristics, manufacturing techniques, operational constraints, or any other characteristic that may affect the design, manufacture or operation of the imaging sensor being designed or components integrated into the imaging sensor.

[0079] In some embodiments, various other 3D stacked designs or technologies may be implemented and may divide the circuit components, elements, and blocks through various stacked technologies and characteristics (e.g., fill slope or density). Such designs and implementations can deliver superior detector performance that 2D sensor configurations cannot.

[0080] In some embodiments, components integrated in the upper layer (e.g., pixel circuitry wafer 420) may be connected to components integrated in the lower layer (e.g., photodiode wafer 410) via a connection at one or more connection points. In some embodiments, the floating diffusion node FD may be configured to function as the connection point between the upper layer (the pixel circuitry layer 420) and the lower layer (the photodiode wafer 410) via a link. fine slope hybrid. In some embodiments, the floating broadcast nodes may be configured to function as the connection point between the upper layer and the lower layer via a fusion bond. The reset transistor RST and the source follower amplifier SF_AMP of the pixel circuitry wafer 420 can be connected to the floating diffusion node FD of the photodiode wafer 410. Further details regarding fine slope hybrid connections will be provided below regarding to Figure 5A, while additional details regarding fusion joints will be provided with respect to Figure 5B. Several other types of connections can be used to couple the top and bottom layers of the wafers.

[0081] Figure 4B and Figure 4C illustrate two sections of an embodiment of a four-transistor architecture and 16 shared image sensor pixels 450 having a pixel reading system, in accordance with an illustrative embodiment, wherein the points of connection A-B indicate the continuation of the elements between figures 4B and 4C. Some embodiments of the image sensor may be a solid-state image sensor, for example, a CMOS image sensor that has sixteen 4T pixels sharing the pixel circuitry, and a compact presentation. The 4T 450 shared 16-pixel architecture can be used as the pixel architecture for the pixels in the pixel array. The 4T 450 shared 16-pixel architecture includes sixteen pixels, and although many of these pixels are arranged in the array, for simplicity only the 4T 450 shared 16-pixel architecture is illustrated in greater detail.

[0082] The 4T 450 shared 16-pixel architecture includes sixteen photodiode circuits, an FD floating diffusion node, an RST retuning transistor, a VDD voltage supply, an SF_AMP source follower amplifier, an SEL selector transistor, a of output voltage Vcol, and a current source Ibias. As mentioned above, in some embodiments, the floating diffusion node FD may represent one or more floating diffusion points dedicated to a photodiode circuit or shared among multiple photodiode circuits. The components of Figures 4B and 4C can perform functions similar to those described above with respect to Figures 1A and 4A. The components of the readout circuitry may be shared by sixteen separate photodiode circuits. The photodiode circuits, as described above with respect to Figures 1A and 4A, may comprise photodiodes PD1-PD16, transfer gates TG1-TG16, storage capacitors CS1-CS16, and timing circuits TS1-TS16. Sharing the floating diffusion node FD, the source-following amplifier SF_AMP, the line selection transistor SEL, and the retuning transistor RST among adjacent photodiode circuits can assist in increasing the fill factor of the pixel architecture, the fill factor representing the percentage of the pixel area that is sensitive to light. The illustrated architecture 450 results in approximately 1.25 transistors per pixel. In some embodiments of the PD1-PD16 photodiodes, four photodiodes may be used to detect a red component of the input light, eight photodiodes may be used to detect a green component of the input light, and four photodiodes may be used to detect a blue component. of the entrance light. As can be seen from the comparison of the 4 shared pixels, 8 shared pixels and 16 shared pixels architectures, the greater the number of shared pixels, the lower the efficient results of transistors per pixel.

[0083] As described above, in some embodiments, the timing circuits TS1-TS16 of the photodiode circuits may include high-speed logic to regulate the number of charge dumps sent from the photodiodes PD1-PD16 to the storage capacitors CS1- CS16 and to determine when to open to allow the charge on the respective storage capacitors CS1-CS6 to be read through the floating diffusion node. In some embodiments, only one storage capacitor of the CS1-CS16 storage capacitors can be read by the read circuitry at a time. In this way, timing circuits TS1-TS16 can be coordinated so that no two are opened together. By accumulating multiple charge dumps of PD1-PD16 photodiodes in the analog domain, device power can be saved compared to accumulating multiple charge dumps of PD1-PD16 photodiodes in the digital domain. The accumulated charge can be read from the CS1-CS16 storage capacitors through the FD floating diffusion node, through the SF_AMP source follower, and through the SEL selection transistor to the Vcol output voltage node.

[0084] Figures 4B and 4C also illustrate an embodiment of partitioning the pixel array and pixel circuitry into separate stacked structures (e.g., silicon wafers), similar to that described above with respect to Figure 4A. For example, a first part including the photodiodes PD1-PD16, the corresponding transfer gates TG1-TG16, the corresponding storage capacitors CS1-CS16, the corresponding timing circuits TS1-TS16, and the floating diffusion node FD can be replaced on a 460 photodiode wafer configured to integrate the input light load. A second part including the reset transistor RST, the voltage supply VDD, the source follower amplifier SF_AMP, the selection transistor SEL, the output voltage node Vcol, and the current source Ibias can be located on a chip wafer. pixel circuitry assembly 470. In some embodiments, one or more of these components may be located on a third pixel circuitry assembly wafer, not illustrated in this figure. Accordingly, the surface space for light detection can be increased through both the space-saving design of the shared pixel architecture in addition to the separation of the photodiode circuits and the pixel circuit assembly on different wafers. The surface space for light detection can be increased since when the pixel circuitry structures and the components forming them are located on the same layer as the photodiode circuits, e.g., the photodiode wafer 460, the state real available for light absorption is reduced (for example, light is reflected or blocked by components or the connections between them and is therefore not absorbed by photodiodes PD1-PD16).

[0085] When pixel circuitry components and structures are located on an individual layer (e.g., pixel circuitry wafer 470), more real state is available to absorb light on the photodiode wafer 460 by the photodiodes PD1-PD16. For example, the photodiode wafer 460 may be configured as a back-side illuminated (BSI) image sensor, where the components described above as being placed on the photodiode wafer 460 are integrated into the BSI image sensor. A BSI image sensor may have a structure attached to it to provide support for the BSI image sensor, which may have less structural integrity due to manufacturing and design constraints (e.g., because the BSI image sensor must be very thin To allow light to penetrate the silicon substrate, the BSI image sensor wafer can be fragile and susceptible to damage). In some embodiments, this structure supporting the BSI image sensor wafer may be a "dummy" or "blank" silicon wafer, accordingly, components located on the pixel circuit assembly wafer 470 may be integrated into the wafer. bracket used to provide structural support for the BSI image sensor. In this way, the BSI image sensor can be designed to be more sensitive to light, where the electrical components used to generate and read signals in response to perceived light can be more efficiently located structurally in a way that increases the area with which the PD photodiode can absorb light. In some embodiments, components as indicated as being on the photodiode wafer 460 or the pixel circuit assembly wafer 470 may be manipulated or changed so that different components are on different wafers than those illustrated in Figures 4B and 4C. For example, in some embodiments, components of the shared pixel architecture may be separated between the photodiode wafer 460 and the pixel circuitry wafer 470 based on whether they have similar electrical characteristics, manufacturing techniques, operational constraints, etc. or any other characteristic that may affect the design, manufacture or operation of the imaging sensor being designated or the components integrated into the imaging sensor.

[0086] In some embodiments, components integrated into the upper layer (e.g., pixel circuit assembly wafer 470) may be connected to components integrated into the lower layer (e.g., photodiode wafer 460) through a connection in a or more connection points. In some embodiments, the floating diffusion node FD may be configured to function as the connection point between the top layer (the pixel circuitry layer 470) and the bottom layer (the photodiode wafer 460) via a link. fine slope hybrid. In some embodiments, the upper and lower layers may be connected via a fusion bond at the same or another connection point with respect to the floating diffusion node FD. Fusion bonding can be used for row or column interconnections, where the reading of an entire row or column is transferred to the upper layer. In some embodiments, the type of connections between the upper and lower layers may determine, in part, the division of components between the upper layer and the lower layer. For example, when fusion bonds are used to couple the top and bottom layer, more of the components can be integrated into the bottom layer. The SEL selection transistor and SF_AMP source follower amplifier of the 470 pixel circuitry wafer can be connected to the FD floating diffusion node of the 460 photodiode wafer. to Figure 5A, while additional details regarding fusion bonds will be provided with respect to Figure 5B. In some embodiments, the photodiode wafer 460 may comprise a detector array wafer and the pixel circuitry wafer may comprise a Pixel FET/AFE/ADE/ADC Mixed Mode ASIC Wafer, as illustrated in Figures 4B and 4B.

[0087] Figure 5A illustrates an embodiment of a 3D stacked CMOS image sensor comprising the interlaced shared pixel architecture of Figures 4A, 4B and 4C with pixel-level fine tilt hybrid bonding. The 3D stacked CMOS image sensor features three distinct layers of the 3D stacked CMOS image sensor. The first (lower) layer 505 may comprise the lower layer described above as the photodiode wafer 410, 460. As illustrated in Figure 5A, the first layer 505 may comprise a BSI sensor layer. The BSI 505 sensor layer as illustrated illustrates a sample of three PD1-PD3 photodiodes from the shared pixel architectures of Figures 1A-1C. Photodiodes PD1-PD3 are illustrated having transfer ports TG1-TG3, respectively, connecting photodiodes PD1-PD3 to individual floating diffusion nodes FD1-FD3. Floating diffusion nodes FD1-FD3 are illustrated as each connecting the intermediate layer 506 via individual fine-pitch hybrid bonds.

[0088] The second (intermediate) layer 506 may comprise the top layer described above as the pixel circuitry wafer 470. The second layer 506 may comprise the analog front end (AFE), the conversion circuitry A /D, and the pixel circuitry described above. For example, the second layer 506 may comprise the TSR reset transistor, the SEL selection transistor, the SF_AMP amplification transistor, and the TS timing circuit with the CS storage capacitor. For BSI sensors as illustrated in the first layer 505, the second layer 506 may pre-comprise the support wafer that provides structural support for the BSI sensor layers, but does not provide any functional capabilities. As illustrated in Figure 5A and as discussed above with respect to Figures 4A and 4B, the second layer 506 may be configured to provide structural support and functional support through the pixel circuitry components integrated into the second layer 506.

[0089] The third (top) layer 507 can be configured as the image signal processor or the digital signal processing layer or readout circuitry layer. For example, the third layer 507 may comprise logic chips or other circuitry configured to perform final processing and/or reading of signals generated by the BSI sensor and converted into digital form by the reading circuitry. In some embodiments, the third layer 507 may be excluded from the 3D CMOS stack structure, and components configured to further process the signal from the pixel circuitry may be integrated into the second layer 506.

[0090] As illustrated in Figure 5A, an input light 510 to which photodiodes PD1-PD3 are exposed can emit upwardly from the bottom of the figure, thus allowing the majority of the light generated to be incident on the photodiodes PD1- PD3 without needing to pass through the pixel circuitry wafer 470. As discussed above, relocating the components for the pixel circuitry to the second layer 506 frees up the area in the first layer 505 that may no longer provide exposure of the photodiodes PD1-PD3 to light. Accordingly, PD1-PD3 photodiodes can be more efficient and faster. Based on the light they are exposed to, the PD1-PD3 photodiodes can generate current signals that can be transferred to the floating diffusion nodes when the respective transfer gate TG1-TG3 is activated via a signal from the transfer gate buses. (not illustrated in this figure). Then, the current signals in the floating diffusion nodes FD1-FD3 can be transferred to the second layer pixel circuitry 506 through the fine slope hybrid connections. The pixel circuitry can then configure the current signals received through the fine-pitch hybrid links to be read with 1 color per channel as described above with respect to Figures 2 and 3.

[0091] Figure 5B illustrates another embodiment of a 3D stacked CMOS image sensor comprising the interlaced shared pixel architecture of Figures 4A and 4B with column/row level fusion bonding. In the embodiment presented in figure 5B, there are four structural levels. The first (lower) level 555 is identified as the BSI sensor layer, while the second level 556 is identified as the analog front end (AFE) and analog digital conversion (ADC) layer, the third level 557 is identified as being the ISP/DSP, and the fourth (top) layer is the PC panel substrate (PCB), e.g. F/R4. The structure and integrated components of the various layers may be similar to layers 505-507 of Figure 5A. In some embodiments, the structure and integrated components of the various layers may be different from those of layers 505-507 of Figure 5A. While the division of components between the first layer 505 and the second layer 506 of Figure 5A corresponds to the division of components as illustrated in Figures 4A and 4B, the division of components between the first layer 555 and the second layer 556 of Figure 5B may correspond to a division where most of the components of the photodiode circuit and the pixel circuit are on the same layer. For example, while Figures 4A and 4B show the PD1-PD3 photodiodes and TG1-TG3 transfer ports as being on a detector array wafer 410, 460 while the shared pixel circuitry has been separated on the detector array wafer. pixel circuits 420, 470, the 3D cross section illustrated in Figure 5B represents a presentation in which all components of Figures 4A and 4B are integrated on the same silicon layer except for the Ibias current source and where the top layer is coupled to the middle layer through one or more fusion bonds.

[0092] For example in the first layer 555, photodiodes PD1-PD3 may be configured to convert light energy received through light 560 flowing upward from the bottom of the page into current signals. The converted current signals can be transferred from the photodiodes PD1-PD3 to the floating diffusion nodes FD1-FD3 associated with each of the photodiodes PD1-PD3 via transfer gate transistors TG1-TG3 in response to receiving the signal on the respective buses. TG_1-TG_3 as referred to in figures 4A and 4B.

[0093] The second layer 556 may comprise an analog layer. The second layer 556 may comprise an analog front end (AFE) and/or an A/D conversion circuitry described above. For example, the second layer 556 may comprise components configured to perform analog manipulation of signals received from the second BSI layer (first layer 555). For BSI sensors as illustrated in the first layer 555, the second layer 556 may previously comprise the support wafer that provided structural support for the BSI sensor layers but did not provide any functional capabilities. As illustrated in Figure 5B, the second layer 556 may be configured to provide structural support and functional support through the analog components integrated into the second layer 556. In some embodiments, the readout circuitry components may be integrated into the second layer 556. This circuitry may include the sample/hold capacitors discussed above and other components used to read the charge values from the pixels.

[0094] The third layer 557 may be configured as the image signal processor or digital signal processing layer or readout circuitry layer. For example, the third layer 557 may comprise logic chips and another set of circuitry configured to perform final processing and/or reading of the signals generated by the BSI sensor and converted into digital form by the readout circuitry. In some embodiments, the third layer 557 may be excluded from the 3D CMOS stack structure, and components configured to further process the signal from the readout circuitry may be integrated into the third layer 557.

[0095] Figure 6A and Figure 6B illustrate two sections of a timing diagram of the shared four-transistor, 4-pixel image sensor interlaced architecture of Figure 1B, in accordance with an illustrative embodiment, having connection points A-X to indicate the continuation of the elements between figures 6A and 6B. Figures 6A and 6B illustrate a timing diagram with increasing time along the x axis and with on-off activations of various signals along the y axis. The various signals together with the y-axis may correspond to transistors or other components of the pixel circuit described above or the readout circuit described above. The top half of the timing diagram illustrates turn-on timings for the reset transistor (referred to as RES in Figures 1A through 2; labeled "Reset" in Figures 6A and 6B), the transfer gates (referred to as TG1-TG4 in Figures 1A to 2; labeled TG_P1, TG_P2, TG_P3, TG_P4 in Figures 6A and 6B), and the timing for activation of the row selection transistor (referred to as SEL in Figures 1A to 2; labeled Row_Sel in Figures 6A and 6B). The lower half of the timing diagram illustrates turn-on timings for components powering various sample/hold capacitors (labeled SM11, SM21, SM12, and SM22 in Figures 6A and 6B) and speaker amplification switches (labeled Phi21 and Phi22 in Figures 6A and 6B).

[0096] In this way, the activation timings of the transistors and other components are illustrated in conjunction with the activation timings of the sample and hold components SM11, SM21, SM12 and SM22 and column amplification components Phi21 and Phi22. The timing diagram illustrates that the reset transistor is activated periodically. When any of the TG_P1-TG-P4 transfer ports are activated at the same time as the reset transistor, the photodiodes (referred to as PD1-PD4 in Figures 1A through 2; labeled P1-P4 in Figures 6A and 6B) are reset to a standard voltage to which the reset transistor is coupled. For example, at time t0, the reset transistor and the TG-P1 transfer gate are illustrated as both being activated at the same time. In this way, at time t0, the photodiode coupled to the TG_P1 transfer port (e.g. photodiode PD1) is readjusted to the coupled voltage. Each of the TG_P1 - TG_P4 transfer ports is activated simultaneously with the reset transistor at different times, so that only a single TG_P1 - TG_P4 transfer port is activated simultaneously with the reset transistor. Additionally, when the Reset reset transistor is active, but none of the TG_P1- TG_P4 transfer ports are active, the storage capacitor or floating diffusion node is reset to the coupled voltage.

[0097] The period of time between activations for a TG_P1-TG_P4 transfer port associated with a PD photodiode may represent the integration period of the photodiode coupled to the particular TG_P1 - TG_P4. For example, between time t0 and time t6, the photodiode coupled to the TG-P1 transfer port (e.g. PD1) can integrate light and generate a charge corresponding to the integrated light. At time t0, the photodiode PD1 can be reset when both the transfer gate transistor TG_P1 and the reset transistor PD1 are turned on at the same time. At time t6, the charge accumulated in PD1 can be transferred to a floating storage capacitor/diffusion node. As illustrated, each of the TG_P1-TG_P4 transfer ports has an integration time associated with it between subsequent activations of the respective TG_P1 - TG_P4 transfer ports. The row select transistor Row_Sel indicates when the row select transistor is enabled for a reading from a particular transfer gate TG_P1-TG_P4 and photodiode combination. The photodiodes can integrate light until the TG_P1-TG_P4 transfer port associated with the photodiode is activated to transfer the integrated charge to the storage capacitor.

[0098] As indicated in Figures 6A and 6B, a "single line time" can indicate the amount of time that passes during which a single line of pixels is read. As illustrated in Figures 6A and 6B, reading a line can comprise reading more than one pixel. For example, in figure 2, each of the four illustrated lines can comprise two different pixels. Similarly, the amount of time that passes between the start of a first reading P1 and a second reading subsequent to P1 can be defined as "time of a frame", where the pixels of a given when are read The time "t_pix" illustrated in the timing diagram can indicate the time of pixel, which completed a reconfiguration sampling and signal levels of a singular pixel during the reading period. When reading all the pixels in a row, the period of time is referred to as a row time.

[0099] As indicated in figures 6A and 6B, the row selection transistor Row_Sel performs two readings for each photodiode PD1-PD4. The two separate readings from each photodiode PD1-PD4 can provide compensation and/or noise reduction. For example, at time t5, the row selection transistor Row_Sel is activated for a first reading from the storage capacitor and/or floating diffusion node. This initial reading occurs shortly after the storage capacitor and/or the floating diffusion node is reset by the Reset reset transistor activating at time t4; This initial reading can provide the baseline for noise associated with the reading. Subsequently, the transfer gate TG_P1 can be activated at time t6 to transfer the charge from the photodiode PD1 coupled to the transfer gate transistor TG_P1 to the storage capacitor and/or floating diffusion node. Then, after TG_P1 is activated at time t6, the row selection transistor Row_Sel is activated at time t7 for a second reading from the storage capacitor and/or floating diffusion node. This second reading can provide a reading value that can be corrected based on the baseline reading value. The two indicated readings may correspond to the noise reduction measurements described above. By taking two readings, for example by sampling the storage capacitor before and after the TG_P1-TG-P4 transfer port is turned on, correlated double sampling with a short sampling time can be performed, thus eliminating at least minus one kTC noise. Additionally, other types of noise can be eliminated or compensated by implementing similar multiple reading techniques.

[0100] In some embodiments, the readout column circuitry may comprise one sample/hold capacitor per column. In some embodiments, the readout column circuitry for an imaging system may comprise a pair of sample/hold capacitors per column. In any case, sample/hold capacitors can be used to reduce a noise reading from the imaging system as described above. Signals SM11, SM21, SM12 and SM22 can represent the signals used to obtain the baseline (reference) and reading (sample). For example, SM11 sampling/holding: the retuned signal can be used to baseline the storage capacitor or floating diffusion node before "dumping" the charge from one of the photodiodes PD1-PD4 into the storage capacitor or node of fluctuating diffusion, as illustrated at time t5. Then, after the charge of photodiode P1 is transferred into the capacitor and storage or floating diffusion node at time t6, the sample/hold signal SM21 can be used to obtain the charge transferred from photodiode P1. Then, the charge read at time t4 can be subtracted from the charge read at time t7 to obtain the reading value without the noise that is common between the baseline and the sampled values. The ampSW-1/SW-2 column can represent the amplification components that are amplifying the values read from the upper and lower column reading channels, as shown in figure 7.

[0101] Figure 7 illustrates an example of a readout block diagram of the interlaced architecture of 4 transistors and 4 shared image sensor pixels of Figure 1B in accordance with the timing diagram of Figures 6A and 6B. As shown, there are two reading circuits, one for the loads read by the upward reading channel and one for the loads read by the downward reading channel. The various components above and below the pixel array comprise sampling switches, sampling capacitors, column addressing multiplexers and signal and reconfiguration buses, and variable gain amplifier. These components, in combination, can receive signals from the pixel array, amplify the signals, and multiplex the signals to one or more video signals.

Illustrative Imaging Device Overview

[0102] Figure 8 illustrates a high-level schematic diagram of an embodiment of an image capture device 700, the device 700 having a set of components including an image processor 720 connected to a camera 701 (image sensor). Image processor 720 is also in communication with a working memory 765, memory 730, device processor 755, which in turn is in communication with store 770, and an optional electronic display 760.

[0103] Device 700 may be a portable personal computing device, e.g., a mobile phone, digital camera, tablet computer, personal digital assistant, or the like. Device 700 may also be a stationary computing device or any device. A plurality of applications may be available to the user on device 700. These applications may include traditional photographic and video applications, e.g., applications pertaining to user management of load dump number, number of differential frames, image creation applications. HDR image, and the like.

[0104] Image capture device 700 includes camera 701 for capturing external images. The camera 701 may include a pixel array 710 and an additional storage capacitor readout circuitry 715 as described above. According to the architectures described above, storage capacitors may have the capacitance to store a number of charge dumps from the associated pixel. Camera 701 can be configured to capture continuous or intermittent preview frames in addition to capturing final full resolution images.

[0105] Image processor 720 may be configured to perform various processing operations on received preview frames. Processor 720 may be a general purpose processing unit or a processor specifically designed for imaging applications. Examples of image processing operations include AWB and AEC data generation, LED current calculation, cropping, scaling (e.g., to a different resolution), image stitching, image format conversion, color interpolation, image processing, color, image filtering (e.g. spatial image filtering), lens artifact or defect correction, etc. The processor 720 may, in some embodiments, comprise a plurality of processors. The processor 720 may be one or more of the dedicated image signal processors (ISPs) or a software implementation of a processor.

[0106] As illustrated, the image processor 720 is connected to a memory 730 and a working memory 765. In the illustrated embodiment, the memory 730 stores the capture control module 735, the deposit capacity full extension module 740, the noise compensation module 780, and the operating system 750. The memory modules 730 include instructions that configure the image processor 720 of the device processor 755 to perform various device management and image processing tasks. Working memory 765 may be used by image processor 720 to store a working set of processor instructions contained in memory modules 730. Alternatively, working memory 765 may also be used by image processor 720 to store dynamic data. created during operation of device 700.

[0107] The total dump capacity extension module 740 may store submodules of the timing scheme module 742 and the load dump number handling module 744. Together, these modules may cooperate to perform tasks pertaining to determining of each pixel integration time and multiple charge dumps from the pixel to the storage capacitor in the readout architecture.

[0108] The noise compensation module 780 may store submodules of the frame capture module 782 and digital aggregation module 784. In some embodiments, the frame capture module 782 may be provided with instructions that configure the processor 720 to carry out the process 500 described above by providing instructions to the image sensor readout circuitry. In some embodiments, the digital aggregation module 784 may be provided with instructions that configure the processor 720 to perform the process 600 described above to aggregate multiple payloads into the digital domain.

[0109] As mentioned above, the image processor 720 is configured by several modules stored in the memories. The capture control module 735 may include instructions that configure the image processor 720 to adjust the focus position of the camera 701. The capture control module 735 may additionally include instructions that control the overall image capture functions of the device 700. For example, capture control module 735 may include instructions that call subroutines to configure image processor 720 to capture preview image data or full resolution image data including the one or more frames of a target image scene using camera 701.

[0110] Operating system module 750 configures image processor 720 to manage working memory 765 and processing resources of device 700. For example, operating system module 750 may include device triggers to manage image processing resources. hardware, e.g., camera 701. Therefore, in some embodiments, instructions contained in the image processing modules discussed above may not interact with these hardware resources directly, but instead interact through standard subroutines or APIs located in operating system component 750. Instructions within operating system 750 can then interact directly with these hardware components. The operating system module 750 may further configure the image processor 720 to share information with the device processor 755.

[0111] Device processor 755 may be configured to control monitor 760 to display the captured image, or a preview of the captured image, to a user. Monitor 760 may be external to imaging device 200 or may be part of imaging device 200. Monitor 760 may also be configured to provide a viewfinder display of a preview image for use prior to capture. of an image, for example, presenting the user with a visual representation of the dynamic beech of the image scene and with a user interface to manually adjust the number of analog load dump and/or digitally accumulated differential frames. Monitor 760 may comprise an LCD or LD screen, and may implement touch-sensitive technologies.

[0112] Device processor 755 may write data to storage module 770, e.g., data represented digitally accumulated differential frames. While the storage module 770 is graphically represented as a traditional disk device, those skilled in the art will understand that the storage module 770 may include a disk drive, e.g., a floppy disk drive, a hard disk drive, a optical disk drive or a magneto-optical disk drive, or a solid-state memory, for example, a FLASH memory, RAM, ROM and/or EEPROM. The storage module 770 may also include multiple memory units, and any of the memory units may be configured to be within the image capture device 700, or may be outside the image capture device 700. For example, the Storage module 770 may include a ROM memory containing system program instructions stored within the image capture device 700. The storage module 770 may also include memory cards or high-speed memories configured to store captured images that may be removable. of the camera. The storage module 770 may also be outside the device 700, and in an illustrative device 700 may wirelessly transmit data to the storage module 770, for example, via a network connection.

[0113] Although Figure 8 depicts a device having separate components to include a processor, imaging sensor, and memory, those skilled in the art will recognize that these separate components can be combined in various ways to achieve particular design objectives. . For example, in an alternative embodiment, memory components may be combined with processor components, for example, to save costs and/or to improve performance.

[0114] Additionally, although Figure 8 illustrates two memory components, including memory component 720 comprising multiple modules and a separate memory 765 comprising working memory, those skilled in the art will recognize various embodiments utilizing different memory architectures. For example, a design may utilize ROM memory or static RAM for storing processor instructions implementing modules contained in memory 730. The processor instructions may be loaded into RAM to facilitate execution by the image processor 720. For example, the working memory 765 may comprise RAM memory, with instructions loaded into working memory 765 prior to execution by processor 720.

Systems Implementation and Terminology

[0115] The implementations described here provide systems, methods, and apparatus for increasing light absorption by photodiode pixels and enabling low-noise, high-gain readouts, high-resolution, high-color-fidelity outputs, and an increased dynamic range utilizing architectures vertically integrated, stacked three-dimensional (3D) pixels. Those skilled in the art will recognize that these embodiments can be implemented in hardware, software, firmware, or any combination thereof.

[0116] In some embodiments, the circuits, processes and systems discussed above may be used in a wireless communication device. Wireless communication device can be a type of electronic device used to communicate wirelessly with other electronic devices. Examples of wireless communication devices include cell phones, smartphones, Personal Digital Assistants (PDAs), ereaders, gaming systems, music players, netbooks, wireless modems, laptop computers, tablet devices, etc.

[0117] The wireless communication device may include one or more image sensors, two or more image signal processors, a memory including instructions or modules for carrying out the CNR process discussed above. The device may also have data, a processor loading instructions and/or data from memory, one or more communication interfaces, one or more input devices, one or more output devices, e.g., a display device, and a source/ power interface. The wireless communication device may additionally include a transmitter and a receiver. The transmitter and receiver can be referred to together as a transceiver. The transceiver can be coupled to one or more antennas for transmitting and/or receiving wireless signals.

[0118] The wireless communication device may wirelessly connect to another electronic device (e.g., base station). A wireless communication device may alternatively be referred to as a mobile device, a mobile station, a subscriber station, a user equipment (UE), a remote station, an access terminal, a mobile terminal, a terminal, a user terminal, a subscriber unit, etc. Examples of wireless communication devices include laptop or desktop computers, cell phones, smartphones, wireless modems, e-readers, tablet devices, gaming systems, etc. Wireless communication devices may operate in accordance with one or more industry standards, for example, the 3rd Partnership Project. Generation (3GPP). Therefore, the general term "wireless communication device" may include wireless communication devices described with varying nomenclature in accordance with industry standards (e.g., access terminal, user equipment (UE), remote terminal, etc.).

[0119] The functions described here may be stored as one or more instructions in a processor-readable or computer-readable medium. The term "computer-readable medium" refers to any available medium that can be accessed by a computer or processor. By way of example, and not limitation, such medium may comprise RAM, ROM, EEPROM, flash memory, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that may be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Floppy disk and disc, as used herein, include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray® disc, where floppy disks typically reproduce data magnetically, while discs reproduce data optically with lasers. It should be noted that a computer-readable medium may be tangible and non-transitory. The term "computer program product" refers to a computing device or processor in combination with code or instructions (e.g., a "program") that can be executed, processed, or computed by the computing device or processor. As used herein, the term "code" may refer to software, instructions, code or data that is executable by a computing device or processor.

[0120] Software or instructions may also be transmitted via a transmission medium. For example, if the software is transmitted from a network site, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies, e.g., infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies, e.g., infrared, radio, and microwave are included in the definition of transmission medium .

[0121] The methods described here comprise one or more steps or actions to achieve the method described. Method steps and/or actions can be interchanged with one another without departing from the scope of claims. In other words, unless a specific order of steps or actions is necessary for the proper operation of the method being described, the order and/or use of specific steps and/or actions may be modified without departing from the scope of the claims. .

[0122] It should be noted that the terms "couple", "coupled" or other variations of the word couple as used herein may indicate a direct or indirect connection. For example, if a first component is "coupled" to a second component, the first component may be indirectly connected to the second component or directly connected to the second component. As used here, the term "plurality" denotes two or more. For example, a plurality of components indicates two or more components.

[0123] The term "determining" encompasses a wide variety of actions, and therefore "determining" may include calculating, computing, processing, deriving, investigating, querying (e.g., querying a table, database, or other data structure). data), determining and the like. Furthermore, "determining" may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), or the like. Furthermore, "determining" may include resolving, selecting, choosing, establishing, and the like.

[0124] The phrase "based on" does not mean "based solely on" unless expressly specified otherwise. In other words, the phrase "based on" describes both "based only on" and "based at least on."

[0125] In the above description, specific details are provided to provide an in-depth understanding of the examples. For example, it will be understood by those skilled in the art that the examples can be practiced without these specific details. For example, electrical components/devices can be illustrated in the form of block diagrams so as not to obscure the examples with unnecessary details. In other cases, such components, other structures and techniques may be illustrated in detail to further explain the examples.

[0126] Headings are included here for reference and to assist in locating various sections. These headings shall not limit the scope of the concepts described in this regard. Such concepts may have applicability throughout the specification.

[0127] It is also noted that the examples can be described as a process, which is presented as a flowchart, a finite state diagram, a structure diagram, or a block diagram. Although a flowchart may describe operations as a sequential process, many of the operations may be performed in parallel, or simultaneously, and the process may be repeated. Additionally, the order of operations may have a new arrangement. A process ends when its operations are completed. A process can correspond to a method, a function, a procedure, a subroutine, a subprogram, etc. A process may correspond to a software function, its termination corresponding to a return from the function to the calling function or main function.

[0128] The foregoing description of the described implementations is provided to enable any person skilled in the art to create or make use of the present invention. Various modifications to these implementations will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other implementations without departing from the spirit or scope of the invention. Accordingly, the present invention should not be limited to the implementations illustrated here, but the broadest scope consistent with the principles and novelty features described here should be agreed upon.

Claims (8)

1. Image creation system, characterized by the fact that it comprises: a plurality of pixels configured to convert light into a charge; one or more amplifier transistors (SF_AMP) configured to convert a charge of a plurality of pixels; one or more selection transistors (SEL) configured to select a row or column from among the plurality of pixels to be read; one or more retuning transistors (RST) configured to retun at least one of a plurality of pixels; a plurality of transfer gate transistors (TG1, TG2), each of the plurality of transfer gate transistors (TG1, TG2) corresponding to one of the plurality of pixels; an array of pixels including the plurality of pixels arranged in one or more shared pixel architectures, wherein each of the one or more shared pixel architectures comprises: a storage capacitor (CS1, CS2) connected to be charged by a photodiode ( PD1, PD2), the storage capacitor (CS1, CS2) having capacitance for storing an accumulated charge representing a plurality of charge dumps from the connected photodiode (PD1, PD2), each of the plurality of charge dumps comprising a charge representative of the light integrated into the connected photodiode (PD1, PD2), wherein the storage capacitor (CS1, CS2) is arranged to be in series with the photodiode (PD1, PD2) via a transfer gate transistor (TG1, TG2 ); and a transistor (TS1, TS2) in communication with the storage capacitor (CS1, CS2) and configured to control the flow of charge from the storage capacitor (CS1, CS2) to a floating diffusion (FD) node; the set being arranged in a plurality of rows and columns; a first silicon structure (460, 505) in a first plane on which the plurality of pixels is arranged; and a second silicon structure (470, 506) in a second plane upon which at least one of the one or more amplifier transistors (SF_AMP), selection transistors (SEL), and reset transistors (RST) are arranged, the background being different from, but parallel to and superimposed on the foreground. 2. Imaging system according to claim 1, characterized by the fact that the floating diffusion node is disposed in the first silicon structure in a first plane and electrically coupled to the one or more amplifier transistors disposed in the second structure silicon in a background. 3. The imaging system of claim 2, wherein the floating diffusion node disposed on the first silicon structure in a first plane is electrically coupled to the one or more amplifier transistors disposed on the second silicon structure. silicon in a background via a fine pitch hybrid bond. 4. The imaging system of claim 2, wherein the floating diffusion node disposed on the first silicon structure in a first plane is electrically coupled to the one or more amplifier transistors disposed on the second silicon structure. silicon in a second plane through a fusion bond. 5. The imaging system of claim 1, wherein the one or more shared pixel architectures forming the pixel array are arranged in an interlaced manner and comprise the one or more amplifier transistors, a or more selection transistors, and one or more reset transistors being shared by a subset of pixels of the plurality of pixels. 6. The image creation system of claim 1, wherein each of the one or more shared pixel architectures is shared between at least two pixels among the plurality of pixels. 7. The imaging system of claim 6, wherein the floating diffusion node of each of the one or more shared pixel architectures is connected between the transistor (TS1, TS2) in communication with the storage capacitor (CS1, CS2) of each of the at least two pixels and the reset transistor, the reset transistor configured to reset one or more of the floating diffusion node, one or more storage capacitors associated with each pixel of the plurality of pixels, and each pixel among the plurality of pixels at a predetermined charge level prior to the plurality of charge dumps. 8. The imaging system of claim 1, wherein each of the one or more shared pixel architectures further comprises: a source-following amplifier configured to receive the accumulated charge from the storage capacitor; and a line selection transistor configured to activate the source follow amplifier of a line selected from the plurality of pixels.