BR112017010809A2 - fornecimento de controle de alocação de memória cache compartilhada em sistemas de memória cache compartilhada - Google Patents
fornecimento de controle de alocação de memória cache compartilhada em sistemas de memória cache compartilhadaInfo
- Publication number
- BR112017010809A2 BR112017010809A2 BR112017010809A BR112017010809A BR112017010809A2 BR 112017010809 A2 BR112017010809 A2 BR 112017010809A2 BR 112017010809 A BR112017010809 A BR 112017010809A BR 112017010809 A BR112017010809 A BR 112017010809A BR 112017010809 A2 BR112017010809 A2 BR 112017010809A2
- Authority
- BR
- Brazil
- Prior art keywords
- cache
- qos
- shared cache
- class
- partition
- Prior art date
Links
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
- G06F12/0833—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means in combination with broadcast means (e.g. for invalidation or updating)
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
- G06F12/121—Replacement control using replacement algorithms
- G06F12/128—Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3037—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a memory, e.g. virtual memory, cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1016—Performance improvement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1041—Resource optimization
- G06F2212/1044—Space efficiency improvement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/31—Providing disk cache in a specific location of a storage system
- G06F2212/314—In storage network, e.g. network attached cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/60—Details of cache memory
- G06F2212/6042—Allocation of cache space to multiple users or processors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/62—Details of cache specific to multiprocessor cache arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
fornecimento de controle de alocação de memória cache compartilhada em sistemas de memória cache compartilhada é apresentado. em um aspecto, um controlador de cache de um sistema de memória cache compartilhada compreendendo uma pluralidade de linhas de cache é apresentado. o controlador de cache compreende um circuito de alocação de cache fornecendo uma máscara de bits de mapeamento mínimo para mapear uma classe de qualidade de serviço (qos) para uma partição mínima das linhas de cache, e uma máscara de bits de mapeamento máximo para mapear a classe qos para uma partição máxima das linhas de cache. o circuito de alocação de cache recebe uma solicitação de acesso à memória compreendendo um identificador qos (qosid) da classe qos, e é configurado para determinar se a solicitação de acesso à memória corresponde a uma linha de cache dentre a pluralidade de linhas de cache. se não, o circuito de alocação de cache seleciona, como uma partição de destino, a partição mínima mapeada para a classe qos ou a partição máxima mapeada para a classe qos.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201462084480P | 2014-11-25 | 2014-11-25 | |
US14/861,025 US9678875B2 (en) | 2014-11-25 | 2015-09-22 | Providing shared cache memory allocation control in shared cache memory systems |
PCT/US2015/059677 WO2016085641A1 (en) | 2014-11-25 | 2015-11-09 | Providing shared cache memory allocation control in shared cache memory systems |
Publications (1)
Publication Number | Publication Date |
---|---|
BR112017010809A2 true BR112017010809A2 (pt) | 2017-12-26 |
Family
ID=56010346
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BR112017010809A BR112017010809A2 (pt) | 2014-11-25 | 2015-11-09 | fornecimento de controle de alocação de memória cache compartilhada em sistemas de memória cache compartilhada |
Country Status (11)
Country | Link |
---|---|
US (1) | US9678875B2 (pt) |
EP (1) | EP3224728B1 (pt) |
JP (1) | JP6262407B1 (pt) |
KR (1) | KR101851294B1 (pt) |
CN (1) | CN107111557B (pt) |
AU (1) | AU2015354703A1 (pt) |
BR (1) | BR112017010809A2 (pt) |
ES (1) | ES2693341T3 (pt) |
HU (1) | HUE040009T2 (pt) |
TW (1) | TWI619016B (pt) |
WO (1) | WO2016085641A1 (pt) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10055158B2 (en) * | 2016-09-22 | 2018-08-21 | Qualcomm Incorporated | Providing flexible management of heterogeneous memory systems using spatial quality of service (QoS) tagging in processor-based systems |
US10678690B2 (en) * | 2017-08-29 | 2020-06-09 | Qualcomm Incorporated | Providing fine-grained quality of service (QoS) control using interpolation for partitioned resources in processor-based systems |
US10649900B2 (en) * | 2017-11-06 | 2020-05-12 | Samsung Electronics Co., Ltd. | Method to avoid cache access conflict between load and fill |
CN109240829B (zh) * | 2018-08-29 | 2021-02-02 | 盛科网络(苏州)有限公司 | 用于交换芯片的申请、管理独占资源的方法及装置 |
US10884959B2 (en) * | 2019-02-13 | 2021-01-05 | Google Llc | Way partitioning for a system-level cache |
EP3924832A4 (en) * | 2019-02-14 | 2022-11-23 | Telefonaktiebolaget Lm Ericsson (Publ) | MEMORY MANAGEMENT CONTROL METHODS AND DEVICES |
US11093287B2 (en) | 2019-05-24 | 2021-08-17 | Intel Corporation | Data management for edge architectures |
US11762770B2 (en) * | 2020-10-22 | 2023-09-19 | EMC IP Holding Company LLC | Cache memory management |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08147218A (ja) * | 1994-11-24 | 1996-06-07 | Fujitsu Ltd | キャッシュ制御装置 |
US20040199727A1 (en) * | 2003-04-02 | 2004-10-07 | Narad Charles E. | Cache allocation |
US7047366B1 (en) | 2003-06-17 | 2006-05-16 | Emc Corporation | QOS feature knobs |
EP1913533A1 (en) * | 2005-08-05 | 2008-04-23 | Pfizer Products Incorporated | Automated batch manufacturing |
JP4643479B2 (ja) * | 2006-03-22 | 2011-03-02 | 株式会社東芝 | アクセス制御装置、アクセス制御システム、プロセッサ、アクセス制御方法およびメモリアクセス制御方法 |
US7725657B2 (en) * | 2007-03-21 | 2010-05-25 | Intel Corporation | Dynamic quality of service (QoS) for a shared cache |
US20090138220A1 (en) * | 2007-11-28 | 2009-05-28 | Bell Jr Robert H | Power-aware line intervention for a multiprocessor directory-based coherency protocol |
US8296522B2 (en) | 2007-12-20 | 2012-10-23 | Intel Corporation | Method, apparatus, and system for shared cache usage to different partitions in a socket with sub-socket partitioning |
TW201110619A (en) * | 2009-09-01 | 2011-03-16 | Fiber Logic Communications Inc | Telecommunication network transmission diver system and method |
US8621149B2 (en) | 2009-12-23 | 2013-12-31 | Intel Corporation | Controlling access to a cache memory using privilege level information |
TWI584662B (zh) * | 2011-06-01 | 2017-05-21 | 內數位專利控股公司 | 內容傳遞網路互連(cdni)機制 |
US8850122B2 (en) | 2011-11-30 | 2014-09-30 | International Business Machines Corporation | Cache optimization via predictive cache size modification |
US8751746B2 (en) | 2011-12-15 | 2014-06-10 | Apple Inc. | QoS management in the L2 cache |
US9824013B2 (en) | 2012-05-08 | 2017-11-21 | Qualcomm Incorporated | Per thread cacheline allocation mechanism in shared partitioned caches in multi-threaded processors |
KR101593161B1 (ko) * | 2014-10-02 | 2016-02-15 | 한국전자통신연구원 | 메모리 관리 장치 및 방법 |
-
2015
- 2015-09-22 US US14/861,025 patent/US9678875B2/en active Active
- 2015-11-09 HU HUE15797546A patent/HUE040009T2/hu unknown
- 2015-11-09 JP JP2017525964A patent/JP6262407B1/ja active Active
- 2015-11-09 CN CN201580061555.XA patent/CN107111557B/zh active Active
- 2015-11-09 WO PCT/US2015/059677 patent/WO2016085641A1/en active Application Filing
- 2015-11-09 KR KR1020177013368A patent/KR101851294B1/ko active IP Right Grant
- 2015-11-09 EP EP15797546.7A patent/EP3224728B1/en active Active
- 2015-11-09 TW TW104136888A patent/TWI619016B/zh not_active IP Right Cessation
- 2015-11-09 AU AU2015354703A patent/AU2015354703A1/en not_active Abandoned
- 2015-11-09 ES ES15797546.7T patent/ES2693341T3/es active Active
- 2015-11-09 BR BR112017010809A patent/BR112017010809A2/pt not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
WO2016085641A1 (en) | 2016-06-02 |
KR101851294B1 (ko) | 2018-04-23 |
KR20170087457A (ko) | 2017-07-28 |
TWI619016B (zh) | 2018-03-21 |
EP3224728B1 (en) | 2018-08-15 |
AU2015354703A1 (en) | 2017-05-04 |
TW201633148A (zh) | 2016-09-16 |
HUE040009T2 (hu) | 2019-02-28 |
US9678875B2 (en) | 2017-06-13 |
US20160147656A1 (en) | 2016-05-26 |
ES2693341T3 (es) | 2018-12-11 |
JP2018503888A (ja) | 2018-02-08 |
JP6262407B1 (ja) | 2018-01-17 |
EP3224728A1 (en) | 2017-10-04 |
CN107111557A (zh) | 2017-08-29 |
CN107111557B (zh) | 2018-09-14 |
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Legal Events
Date | Code | Title | Description |
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B11A | Dismissal acc. art.33 of ipl - examination not requested within 36 months of filing | ||
B11Y | Definitive dismissal acc. article 33 of ipl - extension of time limit for request of examination expired |