BR112015022683A2 - sistema de processamento e método de realização de uma operação de manipulação de dados - Google Patents

sistema de processamento e método de realização de uma operação de manipulação de dados

Info

Publication number
BR112015022683A2
BR112015022683A2 BR112015022683A BR112015022683A BR112015022683A2 BR 112015022683 A2 BR112015022683 A2 BR 112015022683A2 BR 112015022683 A BR112015022683 A BR 112015022683A BR 112015022683 A BR112015022683 A BR 112015022683A BR 112015022683 A2 BR112015022683 A2 BR 112015022683A2
Authority
BR
Brazil
Prior art keywords
processing system
data manipulation
manipulation operation
data
processing
Prior art date
Application number
BR112015022683A
Other languages
English (en)
Other versions
BR112015022683B1 (pt
Inventor
d hadley James
R Anderson Jeremy
C Merten Matthew
Li Tong
B Kadgi Vijaykumar
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of BR112015022683A2 publication Critical patent/BR112015022683A2/pt
Publication of BR112015022683B1 publication Critical patent/BR112015022683B1/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/443—Optimisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30094—Condition code generation, e.g. Carry, Zero flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/3013—Organisation of register space, e.g. banked or distributed register file according to data content, e.g. floating-point registers, address registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
  • Storage Device Security (AREA)
BR112015022683-3A 2013-04-11 2014-04-09 Sistema de processamento e método de realização de uma operação de manipulação de dados BR112015022683B1 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/861,009 US9292288B2 (en) 2013-04-11 2013-04-11 Systems and methods for flag tracking in move elimination operations
US13/861,009 2013-04-11
PCT/US2014/033486 WO2014169032A1 (en) 2013-04-11 2014-04-09 Systems and methods for flag tracking in move elimination operations

Publications (2)

Publication Number Publication Date
BR112015022683A2 true BR112015022683A2 (pt) 2018-07-31
BR112015022683B1 BR112015022683B1 (pt) 2021-12-21

Family

ID=51687620

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112015022683-3A BR112015022683B1 (pt) 2013-04-11 2014-04-09 Sistema de processamento e método de realização de uma operação de manipulação de dados

Country Status (8)

Country Link
US (1) US9292288B2 (pt)
EP (1) EP2984557B1 (pt)
KR (1) KR101655713B1 (pt)
CN (1) CN105190538B (pt)
BR (1) BR112015022683B1 (pt)
RU (1) RU2628156C2 (pt)
TW (1) TWI528291B (pt)
WO (1) WO2014169032A1 (pt)

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US9823925B2 (en) * 2014-03-28 2017-11-21 Intel Corporation Instruction and logic for a logical move in an out-of-order processor
US10853077B2 (en) 2015-08-26 2020-12-01 Huawei Technologies Co., Ltd. Handling Instruction Data and Shared resources in a Processor Having an Architecture Including a Pre-Execution Pipeline and a Resource and a Resource Tracker Circuit Based on Credit Availability
US11221853B2 (en) 2015-08-26 2022-01-11 Huawei Technologies Co., Ltd. Method of dispatching instruction data when a number of available resource credits meets a resource requirement
US10198264B2 (en) * 2015-12-15 2019-02-05 Intel Corporation Sorting data and merging sorted data in an instruction set architecture
US20170177336A1 (en) * 2015-12-22 2017-06-22 Intel Corporation Hardware cancellation monitor for floating point operations
US10261790B2 (en) * 2016-03-31 2019-04-16 Intel Corporation Memory copy instructions, processors, methods, and systems
US10114768B2 (en) * 2016-08-29 2018-10-30 Intel Corporation Enhance memory access permission based on per-page current privilege level
US10713177B2 (en) 2016-09-09 2020-07-14 Intel Corporation Defining virtualized page attributes based on guest page attributes
WO2018058363A1 (en) * 2016-09-28 2018-04-05 Intel Corporation Measuring per-node bandwidth within non-uniform memory access (numa) systems
US10282296B2 (en) * 2016-12-12 2019-05-07 Intel Corporation Zeroing a cache line
US10949205B2 (en) 2018-12-20 2021-03-16 International Business Machines Corporation Implementation of execution compression of instructions in slice target register file mapper
CN112286577B (zh) * 2020-10-30 2022-12-06 上海兆芯集成电路有限公司 处理器及其操作方法

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US6047369A (en) * 1994-02-28 2000-04-04 Intel Corporation Flag renaming and flag masks within register alias table
US5838941A (en) 1996-12-30 1998-11-17 Intel Corporation Out-of-order superscalar microprocessor with a renaming device that maps instructions from memory to registers
US6341370B1 (en) * 1998-04-24 2002-01-22 Sun Microsystems, Inc. Integration of data prefetching and modulo scheduling using postpass prefetch insertion
US6122656A (en) * 1998-07-31 2000-09-19 Advanced Micro Devices, Inc. Processor configured to map logical register numbers to physical register numbers using virtual register numbers
US6253310B1 (en) * 1998-12-31 2001-06-26 Intel Corporation Delayed deallocation of an arithmetic flags register
US6505293B1 (en) 1999-07-07 2003-01-07 Intel Corporation Register renaming to optimize identical register values
US6625723B1 (en) * 1999-07-07 2003-09-23 Intel Corporation Unified renaming scheme for load and store instructions
US6594754B1 (en) * 1999-07-07 2003-07-15 Intel Corporation Mapping destination logical register to physical register storing immediate or renamed source register of move instruction and using mapping counters
US6591332B1 (en) 2000-04-28 2003-07-08 Hewlett-Packard Development Company, L.P. Apparatus and method for tracking flushes of cache entries in a data processing system
US7155599B2 (en) * 2000-12-29 2006-12-26 Intel Corporation Method and apparatus for a register renaming structure
US6772317B2 (en) * 2001-05-17 2004-08-03 Intel Corporation Method and apparatus for optimizing load memory accesses
US6889344B2 (en) 2001-08-09 2005-05-03 International Business Machines Corporation System and method for exposing hidden events on system buses
US6910121B2 (en) 2002-01-02 2005-06-21 Intel Corporation System and method of reducing the number of copies from alias registers to real registers in the commitment of instructions
US20030217249A1 (en) * 2002-05-20 2003-11-20 The Regents Of The University Of Michigan Method and apparatus for virtual register renaming to implement an out-of-order processor
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US7711898B2 (en) * 2003-12-18 2010-05-04 Intel Corporation Register alias table cache to map a logical register to a physical register
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US8661230B2 (en) * 2011-04-15 2014-02-25 International Business Machines Corporation Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions
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Also Published As

Publication number Publication date
RU2628156C2 (ru) 2017-08-15
CN105190538B (zh) 2018-11-09
EP2984557B1 (en) 2020-03-04
TWI528291B (zh) 2016-04-01
RU2015138900A (ru) 2017-03-16
EP2984557A4 (en) 2017-12-20
CN105190538A (zh) 2015-12-23
TW201506797A (zh) 2015-02-16
KR20150119038A (ko) 2015-10-23
US9292288B2 (en) 2016-03-22
BR112015022683B1 (pt) 2021-12-21
EP2984557A1 (en) 2016-02-17
US20140310504A1 (en) 2014-10-16
WO2014169032A1 (en) 2014-10-16
KR101655713B1 (ko) 2016-09-07

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Legal Events

Date Code Title Description
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 09/04/2014, OBSERVADAS AS CONDICOES LEGAIS.

B21F Lapse acc. art. 78, item iv - on non-payment of the annual fees in time

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B24J Lapse because of non-payment of annual fees (definitively: art 78 iv lpi, resolution 113/2013 art. 12)

Free format text: EM VIRTUDE DA EXTINCAO PUBLICADA NA RPI 2717 DE 31-01-2023 E CONSIDERANDO AUSENCIA DE MANIFESTACAO DENTRO DOS PRAZOS LEGAIS, INFORMO QUE CABE SER MANTIDA A EXTINCAO DA PATENTE E SEUS CERTIFICADOS, CONFORME O DISPOSTO NO ARTIGO 12, DA RESOLUCAO 113/2013.