BR0006099A - Circuit arrangement, and, device for reading and / or writing information on an optical information carrier - Google Patents

Circuit arrangement, and, device for reading and / or writing information on an optical information carrier

Info

Publication number
BR0006099A
BR0006099A BR0006099-2A BR0006099A BR0006099A BR 0006099 A BR0006099 A BR 0006099A BR 0006099 A BR0006099 A BR 0006099A BR 0006099 A BR0006099 A BR 0006099A
Authority
BR
Brazil
Prior art keywords
circuit arrangement
reading
terminal
output
writing
Prior art date
Application number
BR0006099-2A
Other languages
Portuguese (pt)
Inventor
Johannes Aldegonda The Homberg
Albert Hendrik Jan Immink
Eise Carel Dijkmans
Original Assignee
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Publication of BR0006099A publication Critical patent/BR0006099A/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B7/00—Recording or reproducing by optical means, e.g. recording using a thermal beam of optical radiation by modifying optical properties or the physical structure, reproducing using an optical beam at lower power by sensing optical properties; Record carriers therefor
    • G11B7/12—Heads, e.g. forming of the optical beam spot or modulation of the optical beam
    • G11B7/125—Optical beam sources therefor, e.g. laser control circuitry specially adapted for optical storage devices; Modulators, e.g. means for controlling the size or intensity of optical spots or optical traces
    • G11B7/126—Circuits, methods or arrangements for laser control or stabilisation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10046—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter
    • G11B20/10203—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter baseline correction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/30—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor
    • H03F3/3001—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor with field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/003—Changing the DC level

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Optics & Photonics (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)
  • Optical Head (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)

Abstract

"ARRANJO DE CIRCUITO, E, DISPOSITIVO PARA LER E/OU ESCREVER INFORMAçãO EM UMA PORTADORA DE INFORMAçãO óPTICA" Um arranjo de circuito de acordo com a invenção possui um primeiro (1) e segundo (2) terminal de suprimento para receber voltagens de suprimento (Vdd e Vss, respectivamente), O arranjo de circuito possui adicionalmente um terminal de entrada (3) para receber um sinal de entrada (Si) e possui um terminal de saída (4) para suprir um sinal de saída (So). O arranjo de circuito inclui ainda meios de deslocamento de nível para efetuar um deslocamento no nível de CC do sinal de saída (So) com relação ao sinal de entrada (Si). Os meios de deslocamento de nível incluem uma fonte de corrente (5) e meios resistivos (6). O terminal de saída (4) é conectado a uma saída da fonte de corrente (5). O terminal de saída (4) é também conectado ao terminal de entrada (3) via meios resistivos (6). A invenção refere-se também a um dispositivo para ler/escrever uma portadora de gravação óptica, incluindo um tal arranjo de circuito."CIRCUIT ARRANGEMENT, E, DEVICE FOR READING AND / OR WRITING INFORMATION ON AN OPTICAL INFORMATION CARRIER" A circuit arrangement according to the invention has a first (1) and second (2) supply terminal to receive supply voltages (Vdd and Vss, respectively), The circuit arrangement additionally has an input terminal (3) to receive an input signal (Si) and has an output terminal (4) to supply an output signal (So). The circuit arrangement further includes level displacement means for effecting a displacement at the DC level of the output signal (So) with respect to the input signal (Si). The level displacement means include a current source (5) and resistive means (6). The output terminal (4) is connected to an output of the current source (5). The output terminal (4) is also connected to the input terminal (3) via resistive means (6). The invention also relates to a device for reading / writing an optical recording carrier, including such a circuit arrangement.

BR0006099-2A 1999-05-06 2000-04-20 Circuit arrangement, and, device for reading and / or writing information on an optical information carrier BR0006099A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP99201415 1999-05-06
PCT/EP2000/003779 WO2000069070A1 (en) 1999-05-06 2000-04-20 Circuit arrangement and optical read/write device including the circuit arrangement

Publications (1)

Publication Number Publication Date
BR0006099A true BR0006099A (en) 2001-04-03

Family

ID=8240182

Family Applications (1)

Application Number Title Priority Date Filing Date
BR0006099-2A BR0006099A (en) 1999-05-06 2000-04-20 Circuit arrangement, and, device for reading and / or writing information on an optical information carrier

Country Status (6)

Country Link
EP (1) EP1095451A1 (en)
JP (1) JP2002544698A (en)
KR (1) KR20010071726A (en)
CN (1) CN1316132A (en)
BR (1) BR0006099A (en)
WO (1) WO2000069070A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017152923A (en) * 2016-02-24 2017-08-31 株式会社デンソー Load drive device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4767946A (en) * 1987-01-12 1988-08-30 Tektronix, Inc. High-speed supply independent level shifter
JP3381937B2 (en) * 1992-05-22 2003-03-04 株式会社東芝 Intermediate potential generation circuit
EP0678984B1 (en) * 1994-04-15 2000-07-26 STMicroelectronics S.r.l. High-to-low-voltage signal level shift circuit
JPH08181546A (en) * 1994-12-27 1996-07-12 Mitsubishi Electric Corp Level shift circuit
US5682108A (en) * 1995-05-17 1997-10-28 Integrated Device Technology, Inc. High speed level translator

Also Published As

Publication number Publication date
CN1316132A (en) 2001-10-03
WO2000069070A1 (en) 2000-11-16
KR20010071726A (en) 2001-07-31
EP1095451A1 (en) 2001-05-02
JP2002544698A (en) 2002-12-24

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Legal Events

Date Code Title Description
FA10 Dismissal: dismissal - article 33 of industrial property law
B11Y Definitive dismissal acc. article 33 of ipl - extension of time limit for request of examination expired