JPH02273846A - Write inhibition monitor circuit for semiconductor storage - Google Patents

Abstract

PURPOSE:To easily detect the presence or absence of a write inhibiting function of a semiconductor storage by converting three types of write inhibition monitor signals corresponding to a semiconductor storage to be connected or the state of this storage into the corresponding binary signals. CONSTITUTION:An end of each of resistances 24a and 24b is connected to a write inhibition monitor signal line 17. The resistance value R1 is set so that the line 17 can secure three different voltage levels in accordance with the write grant or inhibition state of a semiconductor storage 101 or the state of the line 17. Then the means 25a and 25b are added to binarize the three different voltage levels. This binarized signal decides the presence or absence of the line 17 in the storage 101. As a result, the presence or absence of the line 17 can be accurately decided for the storage 101.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an interface circuit for a semiconductor memory device,
In particular, the present invention relates to a circuit that determines the presence or absence of a write inhibit function.

[Conventional technology]

A memory card is a semiconductor storage device that is detachably connected to a data processing device. The data processing device is equipped with a write-protection monitor circuit that determines whether the memory card is in a write-protected state or in a write-enabled state.

FIG. 3 is a circuit diagram showing a main part of a conventional write-protection monitor circuit to which a memory card 101 in a write-protection state is connected.

The write protect monitor circuit captures the potential of the write protect monitor signal line 17 connected to the input terminal of the unidirectional buffer 23 as a write protect monitor signal layer, and uses the output signal of the unidirectional buffer 23 to control the memory card 101. This is to determine whether it is in a write-protected state or in a normal state. The write-inhibit monitor signal line 17 is connected to a power source via a monitor pull-up resistor 22.

The circuit configuration of the memory card 101 with write protection function is shown in the fourth example.
As shown in the figure.

In the figure, when the memory card 101 is connected to a data processing device, the static RAMI is supplied with power from the power supply of the data processing device via the power supply terminal 9 and the power supply control circuit 3. When the memory card 101 is removed from the data processing device, the static RAMI is connected to the internal battery 4 by the current limiting resistor 5. Power is supplied via a reverse voltage prevention diode 6.

Further, the connection point between the power supply terminal 9 and the power supply control circuit 3 is grounded via the input resistor 7, and the power supply control circuit 3 and the static RA
The connection point with MI is connected to the chip enable signal line 8 via a pull-up resistor.

An address signal ADD applied from the data processing device is input to the address input terminal (ADD) of the static RAMI via the address bus 12. Similarly, the output enable signal plane given from the data processing device is sent to the output enable signal input terminal (sub) of the static RAMI via the output enable signal line 14.
is input to. The data signal DATA is applied to the data terminal (DATA) of the static RAMI during a read operation.
) is input to the data processing device through the data bus 13, and during a write operation, the data is input from the data processing device through the data bus 13 to the data terminal (DATA) of the static RAMI. The chip enable signal layer provided from the data processing device is input to a 3-state unidirectional buffer 2, whose output is sent to the static RAMI.
is input manually to the chip enable signal input terminal (Yoshi).

The control terminal of the 3-state t1 direction buffer 2 is
It is connected to the power supply control circuit 3 via a protect signal line 11. The write enable signal layer given from the data processing device is a 3-state unidirectional buffer 1 for write inhibition.
8, and its output is input to the write enable input terminal (line) of the static RAMI. A control terminal of the write-inhibiting three-state unidirectional buffer 18 is connected to the power supply control circuit 3 via a series resistor 19 and a protect signal line 11 . On the other hand, the control terminal of the write-protection three-state unidirectional buffer 18 is also connected to one side fixed contact a of the write-protection switch 20. The write protect monitor signal line 17 is connected to the other fixed contact of the write protect switch 20. The write protect switch 20 has a fixed contact a connected to the control terminal of the write protect three-stem unidirectional buffer 18, and a write protect monitor signal 'l.
It consists of a fixed contact connected to lA17 and a movable contact C whose one side is grounded.

Further, the connection point between the power supply terminal 9 and the power supply control circuit 3 is connected to the write inhibit monitor signal line 17 via an input-type resistor 21. A connection point between the power supply control circuit 3 and the static RAMI is connected to a write enable signal line 16 via a pull-up resistor 8.

The operation related to writing in the memory card 101 with the write inhibit function will be described.

When the write protect switch 20 is switched to the fixed contact a side, that is, the control terminal side of the write protect three-state unidirectional buffer 18, the control terminal of the write protect three state unidirectional buffer 18 is grounded and disconnected. It becomes sable state. Therefore, the write enable signal layer from the data processing device is connected to the 3-state unidirectional buffer 18 for write inhibition.
Since the write-inhibiting 3-state unidirectional buffer 18 does not output a write enable signal layer even if the static RA is manually operated, the static RA is in a write-inhibited state. When this write-protected memory card 101 is connected to the write-protect monitor circuit, the write-protect monitor signal line 17 is pulled up via the monitor pull-up resistor 22, so the output of the unidirectional buffer 23 is The signal is at "H" level.

On the other hand, when the write protect switch 20 is switched to the fixed contact side, that is, the write protect monitor signal line 17 side, the control terminal of the write protect 3-state unidirectional buffer 18 is in the enabled state at the "I(" level). Since the write enable signal layer output from the data processing device is input to the static RAMI,
It becomes possible to write to. At this time, the write protect monitor signal line 17 is grounded, so the write protect monitor signal is “L”.
“It becomes a level.

Therefore, when the output signal of the unidirectional buffer 23 in the write protection monitor circuit is at the "H" level, the data processing device determines that the memory card connected to the data processing device is in the write protection state, and the unidirectional buffer When the output signal of 23 is at the "L" level, it is determined that the memory card connected to the data processing device is in a write-enabled state.

[Problem to be solved by the invention]

However, when a memory card without a write-protection function is connected to the conventional write-protection monitor circuit, the following problems occur.

FIG. 5 is a circuit diagram showing the circuit configuration of a memory card 100 without a write inhibit function. The write enable signal layer provided from the data processing device is the write enable signal line 16.
The signal is input to the write enable signal input terminal (WE) of the static RAMI via the write enable signal input terminal (WE) of the static RAMI.

Furthermore, the memory card 100 is not provided with a connection terminal for the write-protection monitor signal line of the write-protection monitor circuit. Static RAMI power supply configuration and address bus12.
Data bus 13. Output enable signal line 14.
The configuration of the chip enable signal line 15 is similar to the configuration of the memory card 101 without the write inhibit function.

Therefore, when the memory card 100 is connected to the write-protection monitor circuit, one end of the write-protection monitor signal line 17 is open, so that it is always pulled up via the monitor pull-up resistor 22. Therefore, the output signal of the unidirectional buffer 23 is always at the "H" level. Therefore, when using the conventional write-protection monitor circuit, there is a problem in that the data processing device incorrectly determines that the memory card 100 without the write-protection function is in a write-protected state when the memory card 100 is connected.

[Means to solve the problem]

The write protect monitor circuit of the present invention includes two resistors, one end of which is connected to the write protect monitor signal line. A voltage is applied between these resistors. The resistance value of the resistor corresponds to the write-enabled state or write-inhibited state of the semiconductor memory device or the state of the write-inhibited monitor signal line heat.
The write inhibit monitor signal line is set so that three different voltage levels can be obtained. Furthermore, these three voltage levels are
The present invention is characterized in that it is provided with means for converting into a value, and the presence or absence of a write inhibit monitor signal line in the semiconductor memory device is determined based on the binary signal.

[Effect]

There are three types of write-protection monitor signal lines, depending on the write-enabled state or write-protection state of the semiconductor memory device connected to the write-protection monitor circuit of the present invention, or the state of no write-protection monitor signal line. Indicates the voltage level °. The three types of voltage levels are converted into binary signals corresponding to the presence or absence of the write-protect monitor signal line, so the presence or absence of the write-protect monitor signal line in the connected semiconductor memory device is determined based on the binary signals. do.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained below based on drawings showing one embodiment thereof.

FIG. 1 is a circuit diagram showing a main part of a write protection monitor circuit of the present invention to which a memory card 101 is connected. In the figure, the write inhibit monitor signal line 17 is connected to the comparator 25a.
The negative input terminal of the comparator 25b is connected to the positive input terminal of the comparator 25b. Furthermore, the write-protection monitor signal line 17 is connected to a circuit (not shown) that determines whether or not the connected memory card 101 is in a write-protection state. Variable resistors 27a and 27b and series-connected monitor resistors 24a and 24b are connected in parallel between the power supply 29 of the write-protection monitor circuit and the ground line. The positive input terminal of the comparator 25a and the negative input terminal of the comparator 25b are connected to intermediate terminals of the variable resistors 27a and 27b, respectively. The outputs of the comparators 25a, 25b are connected together and input to the unidirectional buffer 23. The output v0 is pulled up via a resistor 26. The unidirectional buffer 23 outputs a signal gate for determining whether or not the write inhibit function exists.

Note that the memory card 101 is equipped with a power switch (not shown), and even though the memory card 101 is connected to a data processing device, power supply from the data processing device to the memory card 101 is stopped. can be done.

When a memory card 101 with a write-protection function is connected to the write-protection monitor circuit having the above configuration, and the write-protection switch 20 is switched to the fixed contact a side, that is, when the memory card 101 is The potential of the write inhibit monitor signal line 17 in the write inhibit state will be explained.

The potential of the power supply 1 is vI, the resistance value of the monitor resistor 24 and the input resistor 21 is R1, the resistance value of the input resistor 7 is R,
Let (R, >> R,).

As shown in the figure, a parallel circuit of an input pull amplifier resistor 21 and a monitor resistor 24a, and a monitor resistor 24 are connected in series between the power supply 29 and the ground line. The combined resistance value of these is R from equation (1).

RI RI The write inhibit monitor signal line 17 is connected to the input resistor 21.
Since it is connected to the connection point between the parallel circuit of the monitor resistor 24a and the monitor resistor 24, the potential of the write inhibit monitor signal line 17 becomes 1 as shown in equation (2).

In the state described above, that is, in the write-inhibited state, when the power switch of the memory card 101 is turned off, the potential of the write-inhibit monitor signal line 17 is as follows.

Between the power supply 29 and the installation line, there are a monitor resistor 24a, a monitor resistor 24b, and a human pull amplifier resistor 21. connected in series. A parallel circuit consisting of input resistors is connected in series. The combined resistance value of these is R, as shown by equation (3). In equation (3), as described above, <R,>
>R1 relationship, it is close to R1+R, =R.

R, +R,R.

= R, ... (3) When the power to the memory card 101 is turned off, the write-protect monitor signal line 17 is installed through a parallel circuit of the monitor resistor 24b and the input pull amplifier resistor 21, so the write-protect monitor is disabled. The potential of the signal gland 17 is 1 as shown in equation (4).

It is 0■ regardless of the operation of the power switch of the memory card 101.

From the above, when the memory card 101 with write protection function is connected to the write protection monitor circuit, the write protection switch 20
Depending on the state of the power switch of the memory card 101, the power of the write-protect monitor signal line 1.7 may change.If the memory card 100 without the write-protect function is connected to the write-protect monitor circuit, the write-protect monitor signal line As a result of being divided by the monitor resistors 24a and 24b, the potential of 17 is <Vl as shown in equation (5).

Next, the potential of the write inhibit monitor signal line 17 when the write inhibit switch 20 of the memory card 101 is switched to the fixed contact side, that is, in the write enabled state, will be described.

When the write protect switch 20 is switched to the fixed setting side, the write protect monitor signal line 17 is grounded, so the memory card 100 without the write protect function is not equipped with a power switch. When connected, the potential of the write inhibit monitor signal line 17 is always ■
It becomes 1.

Now, the comparison reference voltage V of the comparator 25a is ■, ), comparison base of comparator 25b I level.

Therefore, if the output of the unidirectional buffer 23 which inputs the output v0 of the comparators 25a and 25b is the write-protection function presence/absence determination signal PM, then the memory card 1 without the write-protection function
When 00 is connected, write inhibit monitor signal =
v, so PM="H" and memory card 10
When 1 is connected, writing is prohibited. These comparison reference voltages VH and V are set by variable resistors 27a and 2, respectively.
7b.

Fig. 2 Outputs of comparators 25a and 25b ■. (vertical axis) and the potential of the write inhibit monitor signal line 17, that is, the potential of the write inhibit monitor signal -P (horizontal axis). As shown in the figure, when the potential of the write-protection monitor signal line 17 is smaller than or larger than ■, the outputs of the comparators 25a and 25b are ■. is "L" level, and when the potential of the write inhibit monitor signal 17 is ■, ~■□, the output V0 of the comparators 25a and 25b is "H" and PM
= L1.

Note that when the write-protection monitor memory card 101 is disabled, whether the memory card 101 is in a write-protection state or in a write-enabled state is determined by the write-protection monitor signal line as in the past. . In other words, when the write protect switch 20 is switched to the fixed contact a side while the memory card 101 is powered on, that is, in the write protect state, the write protect monitor signal line is at "H" level, and the write protect switch 20 is switched to the fixed contact a side. In the permission state, that is, when the write protect switch 20 is switched to the fixed contact side, the write protect monitor signal WP
is at "L" level.

Further, in this embodiment, the resistance values of two resistors whose one ends are connected to the write-protection monitor signal line 17 are determined by the pull-amplifier resistor 21 provided in the memory card 101 with the write-protection function.
However, the present invention is not limited to this, and two comparison reference voltages whose boundary is the potential vl of the write protect monitor signal ridge when a memory card 100 without a write protect function is connected. It suffices if the resistance value is such that □+VL can be set, that is, Vt).

(Effects of the Invention) As explained above, the write protection monitor circuit of the present invention has the following features:
Three types of write-inhibit monitor signals depending on the connected semiconductor storage device or its state are converted into binary signals corresponding to the presence or absence of the write-inhibit monitor signal line of the connected semiconductor storage device. It is possible to detect whether a semiconductor memory device has a write inhibit function.

Furthermore, for a semiconductor memory device with a write-protection function, it can be determined from the voltage level of the write-protection monitor signal whether the semiconductor memory device is in a write-protection state or a write-enabled state.

Therefore, the write-protection circuit of the present invention can accurately determine the state of the connected semiconductor memory device, and therefore always incorrectly determines that a semiconductor memory device without a write-protection function that is in the write-enabled state is write-protected. This has the effect that no problem will occur unless data is written.

J 4. Simplified view of the drawings Figure 1 is a circuit diagram showing the configuration of the main part of the write-protection monitor circuit according to the present invention, and Figure 2 is the reference voltage and output of the comparator in the write-protection monitor circuit of the present invention. Graph showing the relationship between signals, Figure 3 is a circuit diagram showing the configuration of the main part of a conventional write protection monitor circuit, Figure 4 is a circuit diagram showing the circuit configuration of a memory card without write protection function, Figure 5 FIG. 2 is a circuit diagram showing a circuit configuration of a memory card with a write-protection function.

17...Write protect monitor signal line 20...Write protect switch 24a, 24b...
Monitor fIE resistors 25a, 25b... Comparators In the drawings, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] (1) Semiconductor memory that determines whether a semiconductor memory device has a write-protection monitor signal line pulled up by a resistor, whether it is in a write-enabled state or a write-protection state from the voltage level of the write-protection monitor signal line. The write protect monitor circuit of the device includes two resistors having a resistance value set in relation to the resistance value of the resistor, one end of each resistor is connected to the write protect monitor signal line, and each other is connected to the write protect monitor signal line. The three ends of the write inhibit monitor signal line are connected to different potentials, and the write inhibit monitor signal line is obtained in accordance with the write enable state or write inhibit state of the semiconductor memory device or the state where the write inhibit monitor signal line is absent. 1. A write-inhibit monitor circuit for a semiconductor memory device, comprising means for binarizing different voltage levels, and determining the presence or absence of the write-inhibit monitor signal line based on the binarized signal.