BR0002492A - Decodificação de viterbi utilizando correção de mudança incorreta simples - Google Patents

Decodificação de viterbi utilizando correção de mudança incorreta simples

Info

Publication number
BR0002492A
BR0002492A BR0002492-9A BR0002492A BR0002492A BR 0002492 A BR0002492 A BR 0002492A BR 0002492 A BR0002492 A BR 0002492A BR 0002492 A BR0002492 A BR 0002492A
Authority
BR
Brazil
Prior art keywords
search
viterbi
recursive
path
stage
Prior art date
Application number
BR0002492-9A
Other languages
English (en)
Inventor
Stephen Alan Allpress
Mark David Hahm
Original Assignee
Lucent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lucent Technologies Inc filed Critical Lucent Technologies Inc
Publication of BR0002492A publication Critical patent/BR0002492A/pt

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4107—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing add, compare, select [ACS] operations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4115—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors list output Viterbi decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4161—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management
    • H03M13/4169—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management using traceback

Landscapes

  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

<B>DECODIFICAçãO DE VITERBI UTILIZANDO CORREçãO DE MUDANçA INCORRETA SIMPLES<D> Um método de decodificação recursivo de mudança incorreta única (SWT) e decodificador de Viterbi que não necessita circuitos ou processamento adicionais para pesquisar uma lista de funcionamento das L melhores trajetórias. Se a trajetória mais provável (ML) falha os testes métricos de qualidade de quadro, é feita uma pesquisa através de uma treliça usando as informações remanescentes (pesquisa) existentes armazenadas em uma memória remanescente (pesquisa). Uma interação no algoritmo recursivo inclui pesquisar ao longo da trajetória ML até um estágio específico, em seguida desviar da trajetória ML e seguir as informações remanescentes ao longo daquela nova trajetória de desvio e finalmente verificar o quadro totalmente decodificado para ver se as métricas de qualidade do quadro são aceitáveis para o quadro. Estas mesmas etapas de pesquisa podem ser realizadas para cada estágio na treliça, desviando de um estágio diferente na trajetória ML de cada vez. Um método de decodificação recursivo de mudança incorreta única (SWT) e decodificador de Viterbi que excede o desempenho do algoritmo genérico de Viterbi e dos vários decodificadores convencionais de listas de Viterbi, o qual é muito menos complexo computacional e fisicamente.
BR0002492-9A 1999-05-28 2000-05-25 Decodificação de viterbi utilizando correção de mudança incorreta simples BR0002492A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/321,794 US6378106B1 (en) 1999-05-28 1999-05-28 Viterbi decoding using single-wrong-turn correction

Publications (1)

Publication Number Publication Date
BR0002492A true BR0002492A (pt) 2001-01-02

Family

ID=23252055

Family Applications (1)

Application Number Title Priority Date Filing Date
BR0002492-9A BR0002492A (pt) 1999-05-28 2000-05-25 Decodificação de viterbi utilizando correção de mudança incorreta simples

Country Status (8)

Country Link
US (1) US6378106B1 (pt)
EP (1) EP1056212A3 (pt)
JP (1) JP2001024527A (pt)
KR (1) KR20000077417A (pt)
CN (1) CN1275836A (pt)
AU (1) AU3636300A (pt)
BR (1) BR0002492A (pt)
CA (1) CA2308905A1 (pt)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6700938B1 (en) * 1999-09-29 2004-03-02 Motorola, Inc. Method for determining quality of trellis decoded block data
SG125064A1 (en) * 2002-02-15 2006-09-29 Panasonic Singapore Lab Pte Lt Traceback operation in viterbi decoding for rate-k/n convolutional codes
US7139312B2 (en) * 2002-05-23 2006-11-21 Stmicroelectronics, Inc. System and method for improving coding gain performance within gigabit phy viterbi decoder
TWI350066B (en) * 2003-04-17 2011-10-01 Icera Inc Apparatus and method for turbo decoder termination
US7359464B2 (en) * 2003-12-31 2008-04-15 Intel Corporation Trellis decoder and method of decoding
GB2411326B (en) * 2004-02-19 2006-05-17 Matsushita Electric Ind Co Ltd Viterbi decoder with single wrong turn correction
US8046662B2 (en) 2004-08-20 2011-10-25 Broadcom Corporation Method and system for decoding control data in GSM-based systems using inherent redundancy
US7716565B2 (en) 2004-08-20 2010-05-11 Broadcom Corporation Method and system for decoding video, voice, and speech data using redundancy
US7809090B2 (en) * 2005-12-28 2010-10-05 Alcatel-Lucent Usa Inc. Blind data rate identification for enhanced receivers
KR101181723B1 (ko) * 2006-02-07 2012-09-19 삼성전자주식회사 무선 통신 시스템에서 페이징 메시지 디코딩 방법과 장치
JP2008118327A (ja) * 2006-11-02 2008-05-22 Nec Electronics Corp ビタビ復号方法
KR101462211B1 (ko) * 2008-01-30 2014-11-17 삼성전자주식회사 이동통신 시스템의 복호 장치 및 방법
US8181098B2 (en) * 2008-06-11 2012-05-15 Freescale Semiconductor, Inc. Error correcting Viterbi decoder
US8402342B2 (en) 2010-02-26 2013-03-19 Research In Motion Limited Method and system for cyclic redundancy check
US8433004B2 (en) * 2010-02-26 2013-04-30 Research In Motion Limited Low-latency viterbi survivor memory architecture and method using register exchange, trace-back, and trace-forward
US8438463B2 (en) * 2010-12-08 2013-05-07 Research In Motion Limited Decoding tail-biting convolutional codes
KR102375951B1 (ko) 2015-07-29 2022-03-17 삼성전자주식회사 오류 감소를 위한 디코딩 장치 및 방법

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3340618B2 (ja) 1996-04-19 2002-11-05 松下電器産業株式会社 誤り検出方法
KR100212836B1 (ko) * 1996-06-14 1999-08-02 전주범 비터비 디코더의 트레이스백 진행 구조
US5917837A (en) * 1996-09-11 1999-06-29 Qualcomm, Incorporated Method and apparatus for performing decoding of codes with the use of side information associated with the encoded data
US6094465A (en) * 1997-03-21 2000-07-25 Qualcomm Incorporated Method and apparatus for performing decoding of CRC outer concatenated codes
JP3464121B2 (ja) * 1997-06-11 2003-11-05 沖電気工業株式会社 ビタビ復号方法及びビタビ復号装置
JP3094957B2 (ja) 1997-06-30 2000-10-03 日本電気株式会社 移動通信システムの上り選択サイトダイバーシチにおける無線基地局受信データ伝送システム

Also Published As

Publication number Publication date
AU3636300A (en) 2000-11-30
US6378106B1 (en) 2002-04-23
EP1056212A3 (en) 2001-04-11
CA2308905A1 (en) 2000-11-28
EP1056212A2 (en) 2000-11-29
KR20000077417A (ko) 2000-12-26
CN1275836A (zh) 2000-12-06
JP2001024527A (ja) 2001-01-26

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Legal Events

Date Code Title Description
FA10 Dismissal: dismissal - article 33 of industrial property law
B11Y Definitive dismissal - extension of time limit for request of examination expired [chapter 11.1.1 patent gazette]
B15K Others concerning applications: alteration of classification

Ipc: H03M 13/00 (2006.01), H03M 13/41 (2006.01)