BE893001A - ADD BINARY - Google Patents

ADD BINARY

Info

Publication number
BE893001A
BE893001A BE2/59683A BE2059683A BE893001A BE 893001 A BE893001 A BE 893001A BE 2/59683 A BE2/59683 A BE 2/59683A BE 2059683 A BE2059683 A BE 2059683A BE 893001 A BE893001 A BE 893001A
Authority
BE
Belgium
Prior art keywords
add binary
binary
add
Prior art date
Application number
BE2/59683A
Other languages
French (fr)
Inventor
C P H Lerouge
Original Assignee
Int Standard Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Int Standard Electric Corp filed Critical Int Standard Electric Corp
Publication of BE893001A publication Critical patent/BE893001A/en
Priority to BE2/60140A priority Critical patent/BE897170R/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/503—Half or full adders, i.e. basic adder cells for one denomination using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
BE2/59683A 1981-04-29 1982-04-28 ADD BINARY BE893001A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
BE2/60140A BE897170R (en) 1982-04-28 1983-06-30 Bipolar binary adder for three input variables - uses differential transistor pairs to obtain sum and remainder signals for output matching stage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8108531A FR2505065A1 (en) 1981-04-29 1981-04-29 MOS transistor binary adder cell - has single logic gate between carry input and output controlled by decoder circuit receiving bits to be added

Publications (1)

Publication Number Publication Date
BE893001A true BE893001A (en) 1982-10-28

Family

ID=9257898

Family Applications (1)

Application Number Title Priority Date Filing Date
BE2/59683A BE893001A (en) 1981-04-29 1982-04-28 ADD BINARY

Country Status (2)

Country Link
BE (1) BE893001A (en)
FR (1) FR2505065A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4689763A (en) * 1985-01-04 1987-08-25 Advanced Micro Devices, Inc. CMOS full adder circuit

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2053444A5 (en) * 1969-07-04 1971-04-16 Thomson Csf
US3602705A (en) * 1970-03-25 1971-08-31 Westinghouse Electric Corp Binary full adder circuit
US3767906A (en) * 1972-01-21 1973-10-23 Rca Corp Multifunction full adder
US3932734A (en) * 1974-03-08 1976-01-13 Hawker Siddeley Dynamics Limited Binary parallel adder employing high speed gating circuitry
DE2647982A1 (en) * 1976-10-22 1978-04-27 Siemens Ag LOGICAL CIRCUIT ARRANGEMENT IN INTEGRATED MOS CIRCUIT TECHNOLOGY
US4152775A (en) * 1977-07-20 1979-05-01 Intel Corporation Single line propagation adder and method for binary addition

Also Published As

Publication number Publication date
FR2505065A1 (en) 1982-11-05

Similar Documents

Publication Publication Date Title
BE893795A (en) INHALER-DOSER
AT382116B (en) NOISE-DAMPED RAILWHEEL
AR228298A1 (en) CUBE-PUZZLE
FI821899A0 (en) SYREKONVERTERINGSPROCESS FOER FAST METALLSTEN
BE889765A (en) STIJGERELEMENT
AT372860B (en) SCHIPAAR
BE893877A (en) MOND-EN TANDVERZORGINGSMIDDEL
FI822774L (en) FAESTNINGSSTAONG
MA19539A1 (en) N Acylaminophenylpyrazoles
BE894481A (en) STROMINGSMETER
AT384100B (en) TURNTUBES
FI822756L (en) VENTILKONSTRUKTION
BE891918A (en) DRAAIBARE SCHOORSTEENKAP
BE895065R (en) BINARY ADDER
BE893032R (en) BINARY ADDER
ATA373181A (en) TRIMWAY TRANSITION
BE891837A (en) ANTHRACYCLINE-GLYCOSIDES
FI821261A0 (en) FAESTSAETE FOER FILTERPAOSAR
AT385733B (en) SKIBOB
FI824106L (en) FOERPACKNING
ATA183681A (en) BLOCKHAUS
BE893001A (en) ADD BINARY
AT379276B (en) HOERGERAET
AT374656B (en) MAISHAECKSLER
BE893857A (en) COUNTER-SHOWCASE

Legal Events

Date Code Title Description
RE Patent lapsed

Owner name: ALCATEL N.V.

Effective date: 19880430

RR Patent reestablished after lapse

Free format text: 890113 *ALCATEL N.V.

RE Patent lapsed

Owner name: ALCATEL N.V.

Effective date: 19900430