FR2053444A5 - - Google Patents

Info

Publication number
FR2053444A5
FR2053444A5 FR6922743A FR6922743A FR2053444A5 FR 2053444 A5 FR2053444 A5 FR 2053444A5 FR 6922743 A FR6922743 A FR 6922743A FR 6922743 A FR6922743 A FR 6922743A FR 2053444 A5 FR2053444 A5 FR 2053444A5
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR6922743A
Other languages
French (fr)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Thomson CSF SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson CSF SA filed Critical Thomson CSF SA
Priority to FR6922743A priority Critical patent/FR2053444A5/fr
Application granted granted Critical
Publication of FR2053444A5 publication Critical patent/FR2053444A5/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/503—Half or full adders, i.e. basic adder cells for one denomination using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/4816—Pass transistors

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
FR6922743A 1969-07-04 1969-07-04 Expired FR2053444A5 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR6922743A FR2053444A5 (en) 1969-07-04 1969-07-04

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR6922743A FR2053444A5 (en) 1969-07-04 1969-07-04

Publications (1)

Publication Number Publication Date
FR2053444A5 true FR2053444A5 (en) 1971-04-16

Family

ID=9036972

Family Applications (1)

Application Number Title Priority Date Filing Date
FR6922743A Expired FR2053444A5 (en) 1969-07-04 1969-07-04

Country Status (1)

Country Link
FR (1) FR2053444A5 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0048352A1 (en) * 1980-09-20 1982-03-31 Deutsche ITT Industries GmbH Binary MOS-switched carry parallel adder
FR2505065A1 (en) * 1981-04-29 1982-11-05 Labo Cent Telecommunicat MOS transistor binary adder cell - has single logic gate between carry input and output controlled by decoder circuit receiving bits to be added
FR2546317A1 (en) * 1983-05-20 1984-11-23 Efcis Adder with a routing switch structure
EP0187698A2 (en) * 1985-01-04 1986-07-16 Advanced Micro Devices, Inc. Balanced full adder circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0048352A1 (en) * 1980-09-20 1982-03-31 Deutsche ITT Industries GmbH Binary MOS-switched carry parallel adder
FR2505065A1 (en) * 1981-04-29 1982-11-05 Labo Cent Telecommunicat MOS transistor binary adder cell - has single logic gate between carry input and output controlled by decoder circuit receiving bits to be added
FR2546317A1 (en) * 1983-05-20 1984-11-23 Efcis Adder with a routing switch structure
EP0187698A2 (en) * 1985-01-04 1986-07-16 Advanced Micro Devices, Inc. Balanced full adder circuit
EP0187698A3 (en) * 1985-01-04 1989-06-28 Advanced Micro Devices, Inc. Balanced full adder circuit

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Legal Events

Date Code Title Description
ST Notification of lapse