BE768899A - Interconnexion de dispositifs electriques - Google Patents

Interconnexion de dispositifs electriques

Info

Publication number
BE768899A
BE768899A BE768899A BE768899A BE768899A BE 768899 A BE768899 A BE 768899A BE 768899 A BE768899 A BE 768899A BE 768899 A BE768899 A BE 768899A BE 768899 A BE768899 A BE 768899A
Authority
BE
Belgium
Prior art keywords
interconnection
electrical devices
electrical
devices
Prior art date
Application number
BE768899A
Other languages
English (en)
French (fr)
Inventor
G E Smith
Original Assignee
Western Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co filed Critical Western Electric Co
Publication of BE768899A publication Critical patent/BE768899A/xx

Links

Classifications

    • H10W20/40—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N97/00—Electric solid-state thin-film or thick-film devices, not otherwise provided for
    • H10P50/667—
    • H10P95/00—
    • H10W20/062—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/041—Doping control in crystal growth
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/042—Doping, graded, for tapered etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/049—Equivalence and options
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/067—Graded energy gap
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/122—Polycrystalline

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
BE768899A 1970-06-29 1971-06-23 Interconnexion de dispositifs electriques BE768899A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US5078070A 1970-06-29 1970-06-29

Publications (1)

Publication Number Publication Date
BE768899A true BE768899A (fr) 1971-11-03

Family

ID=21967382

Family Applications (1)

Application Number Title Priority Date Filing Date
BE768899A BE768899A (fr) 1970-06-29 1971-06-23 Interconnexion de dispositifs electriques

Country Status (9)

Country Link
US (1) US3675319A (OSRAM)
JP (1) JPS557018B1 (OSRAM)
BE (1) BE768899A (OSRAM)
CA (1) CA922425A (OSRAM)
DE (1) DE2132099C3 (OSRAM)
FR (1) FR2096566B1 (OSRAM)
GB (1) GB1348731A (OSRAM)
NL (1) NL174413C (OSRAM)
SE (1) SE373983B (OSRAM)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3936331A (en) * 1974-04-01 1976-02-03 Fairchild Camera And Instrument Corporation Process for forming sloped topography contact areas between polycrystalline silicon and single-crystal silicon
GB1501114A (en) * 1974-04-25 1978-02-15 Rca Corp Method of making a semiconductor device
US4181564A (en) * 1978-04-24 1980-01-01 Bell Telephone Laboratories, Incorporated Fabrication of patterned silicon nitride insulating layers having gently sloping sidewalls
US4354309A (en) * 1978-12-29 1982-10-19 International Business Machines Corp. Method of manufacturing a metal-insulator-semiconductor device utilizing a graded deposition of polycrystalline silicon
US5285571A (en) * 1992-10-13 1994-02-15 General Electric Company Method for extending an electrical conductor over an edge of an HDI substrate
DE19649972C2 (de) * 1996-11-22 2002-11-07 Siemens Ag Verfahren zur Herstellung eines Leitungssatzes für Kraftfahrzeuge
US20140264340A1 (en) * 2013-03-14 2014-09-18 Sandia Corporation Reversible hybridization of large surface area array electronics
US9905471B2 (en) * 2016-04-28 2018-02-27 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit structure and method forming trenches with different depths

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3260634A (en) * 1961-02-17 1966-07-12 Motorola Inc Method of etching a semiconductor wafer to provide tapered dice
NL285523A (OSRAM) * 1961-11-24
FR1379429A (fr) * 1963-01-31 1964-11-20 Motorola Inc Procédé d'isolement électrique pour circuits miniaturisés
DE1564896A1 (de) * 1966-08-30 1970-01-08 Telefunken Patent Halbleiteranordnung
BE758160A (fr) * 1969-10-31 1971-04-01 Fairchild Camera Instr Co Structure metallique a couches multiples et procede de fabrication d'une telle structure
JPS563951B2 (OSRAM) * 1973-05-15 1981-01-28

Also Published As

Publication number Publication date
NL174413C (nl) 1984-06-01
US3675319A (en) 1972-07-11
JPS557018B1 (OSRAM) 1980-02-21
SE373983B (OSRAM) 1975-02-17
DE2132099A1 (de) 1972-01-05
GB1348731A (en) 1974-03-20
DE2132099C3 (de) 1983-12-01
DE2132099B2 (de) 1979-10-11
CA922425A (en) 1973-03-06
FR2096566A1 (OSRAM) 1972-02-18
NL7108656A (OSRAM) 1971-12-31
NL174413B (nl) 1984-01-02
FR2096566B1 (OSRAM) 1975-02-07

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Legal Events

Date Code Title Description
RE20 Patent expired

Owner name: WESTERN ELECTRIC CY INC.

Effective date: 19910623