BE753976A - PROCESS FOR OBTAINING SEMICONDUCTOR DEVICES WITH REDUCED LEVEL DIFFERENCES IN THE SURFACE, AND SEMICONDUCTOR DEVICES OBTAINED BY APPLYING THIS PROCEDURE - Google Patents

PROCESS FOR OBTAINING SEMICONDUCTOR DEVICES WITH REDUCED LEVEL DIFFERENCES IN THE SURFACE, AND SEMICONDUCTOR DEVICES OBTAINED BY APPLYING THIS PROCEDURE

Info

Publication number
BE753976A
BE753976A BE753976DA BE753976A BE 753976 A BE753976 A BE 753976A BE 753976D A BE753976D A BE 753976DA BE 753976 A BE753976 A BE 753976A
Authority
BE
Belgium
Prior art keywords
semiconductor devices
procedure
applying
reduced level
level differences
Prior art date
Application number
Other languages
French (fr)
Original Assignee
Soc Gen Semiconduttori Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soc Gen Semiconduttori Spa filed Critical Soc Gen Semiconduttori Spa
Publication of BE753976A publication Critical patent/BE753976A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76221—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO with a plurality of successive local oxidation steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
BE753976D 1969-07-30 1970-07-27 PROCESS FOR OBTAINING SEMICONDUCTOR DEVICES WITH REDUCED LEVEL DIFFERENCES IN THE SURFACE, AND SEMICONDUCTOR DEVICES OBTAINED BY APPLYING THIS PROCEDURE BE753976A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT5283069 1969-07-30

Publications (1)

Publication Number Publication Date
BE753976A true BE753976A (en) 1970-12-31

Family

ID=11277825

Family Applications (1)

Application Number Title Priority Date Filing Date
BE753976D BE753976A (en) 1969-07-30 1970-07-27 PROCESS FOR OBTAINING SEMICONDUCTOR DEVICES WITH REDUCED LEVEL DIFFERENCES IN THE SURFACE, AND SEMICONDUCTOR DEVICES OBTAINED BY APPLYING THIS PROCEDURE

Country Status (7)

Country Link
AU (1) AU1774570A (en)
BE (1) BE753976A (en)
CH (1) CH516871A (en)
DE (1) DE2031918A1 (en)
FR (1) FR2053271A7 (en)
IL (1) IL35015A0 (en)
NL (1) NL7011252A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3648125A (en) * 1971-02-02 1972-03-07 Fairchild Camera Instr Co Method of fabricating integrated circuits with oxidized isolation and the resulting structure
US3966514A (en) * 1975-06-30 1976-06-29 Ibm Corporation Method for forming dielectric isolation combining dielectric deposition and thermal oxidation
JPS5693344A (en) * 1979-12-26 1981-07-28 Fujitsu Ltd Manufacture of semiconductor device

Also Published As

Publication number Publication date
FR2053271B3 (en) 1973-04-27
AU1774570A (en) 1972-01-20
FR2053271A7 (en) 1971-04-16
CH516871A (en) 1971-12-15
DE2031918A1 (en) 1971-02-11
IL35015A0 (en) 1970-09-17
NL7011252A (en) 1971-02-02

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