CH516871A - Process for obtaining semiconductor devices with minimal surface unevenness, and semiconductor device obtained using said process - Google Patents

Process for obtaining semiconductor devices with minimal surface unevenness, and semiconductor device obtained using said process

Info

Publication number
CH516871A
CH516871A CH744070A CH744070A CH516871A CH 516871 A CH516871 A CH 516871A CH 744070 A CH744070 A CH 744070A CH 744070 A CH744070 A CH 744070A CH 516871 A CH516871 A CH 516871A
Authority
CH
Switzerland
Prior art keywords
device obtained
surface unevenness
semiconductor device
minimal surface
obtaining
Prior art date
Application number
CH744070A
Other languages
Italian (it)
Inventor
Franco Dr Morandi
Original Assignee
Soc Gen Semiconduttori Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soc Gen Semiconduttori Spa filed Critical Soc Gen Semiconduttori Spa
Publication of CH516871A publication Critical patent/CH516871A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76221—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO with a plurality of successive local oxidation steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
CH744070A 1969-07-30 1970-05-20 Process for obtaining semiconductor devices with minimal surface unevenness, and semiconductor device obtained using said process CH516871A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT5283069 1969-07-30

Publications (1)

Publication Number Publication Date
CH516871A true CH516871A (en) 1971-12-15

Family

ID=11277825

Family Applications (1)

Application Number Title Priority Date Filing Date
CH744070A CH516871A (en) 1969-07-30 1970-05-20 Process for obtaining semiconductor devices with minimal surface unevenness, and semiconductor device obtained using said process

Country Status (7)

Country Link
AU (1) AU1774570A (en)
BE (1) BE753976A (en)
CH (1) CH516871A (en)
DE (1) DE2031918A1 (en)
FR (1) FR2053271A7 (en)
IL (1) IL35015A0 (en)
NL (1) NL7011252A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3648125A (en) * 1971-02-02 1972-03-07 Fairchild Camera Instr Co Method of fabricating integrated circuits with oxidized isolation and the resulting structure
US3966514A (en) * 1975-06-30 1976-06-29 Ibm Corporation Method for forming dielectric isolation combining dielectric deposition and thermal oxidation
JPS5693344A (en) * 1979-12-26 1981-07-28 Fujitsu Ltd Manufacture of semiconductor device

Also Published As

Publication number Publication date
FR2053271B3 (en) 1973-04-27
AU1774570A (en) 1972-01-20
FR2053271A7 (en) 1971-04-16
DE2031918A1 (en) 1971-02-11
BE753976A (en) 1970-12-31
IL35015A0 (en) 1970-09-17
NL7011252A (en) 1971-02-02

Similar Documents

Publication Publication Date Title
BR6915742D0 (en) SEMICONDUCTOR DEVICE
NL162253C (en) SEMICONDUCTOR DEVICE.
CH507591A (en) Semiconductor device
NL161617B (en) SEMI-CONDUCTOR DEVICE WITH FLAT SURFACE AND METHOD FOR MANUFACTURING THIS.
NL161923C (en) SEMICONDUCTOR DEVICE.
CH504108A (en) Semiconductor device
BR7018863D0 (en) INTEGRATED SEMICONDUCTOR DEVICE
BR6909280D0 (en) SEMICONDUCTOR DEVICE WITH MULTIPLE TERMINALS
BR7310275D0 (en) IMPROVEMENT IN A MULTIPLE JUNCLE SEMICONDUCTOR DEVICE
HK72478A (en) Semiconductor device
CH511512A (en) Semiconductor device
BR6909999D0 (en) SEMICONDUCTOR DEVICE
BE753246A (en) HETEROJUNCTION SEMICONDUCTOR DEVICE
BR7308693D0 (en) SEMICONDUCTOR DEVICE
NL163672C (en) SEMICONDUCTOR DEVICE.
BR7310282D0 (en) IMPROVEMENT IN A MULTIPLE JUNCLE SEMICONDUCTOR DEVICE
AT300961B (en) Semiconductor device
CH487504A (en) Semiconductor device
CH516871A (en) Process for obtaining semiconductor devices with minimal surface unevenness, and semiconductor device obtained using said process
DE1903342B2 (en) SEMI-CONDUCTOR DEVICE
CH499204A (en) Semiconductor device
CH513515A (en) Semiconductor device
BR6908675D0 (en) SEMICONDUCTOR DEVICE IN SHALLOW PACKAGE
IE34505L (en) Semiconductor device
AT310811B (en) Semiconductor element with cooling device

Legal Events

Date Code Title Description
PL Patent ceased