BE745547A - Dispositif pour commander l'echelonnement sequentiel d'instructions dans un systeme de traitement d'informations. - Google Patents

Dispositif pour commander l'echelonnement sequentiel d'instructions dans un systeme de traitement d'informations.

Info

Publication number
BE745547A
BE745547A BE745547DA BE745547A BE 745547 A BE745547 A BE 745547A BE 745547D A BE745547D A BE 745547DA BE 745547 A BE745547 A BE 745547A
Authority
BE
Belgium
Prior art keywords
instructions
controlling
information processing
processing system
sequential stage
Prior art date
Application number
Other languages
English (en)
Inventor
E W Reigel
H W Bingham
Original Assignee
Burroughs Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Burroughs Corp filed Critical Burroughs Corp
Publication of BE745547A publication Critical patent/BE745547A/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Devices For Executing Special Programs (AREA)
BE745547D 1969-02-05 1970-02-05 Dispositif pour commander l'echelonnement sequentiel d'instructions dans un systeme de traitement d'informations. BE745547A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US79677969A 1969-02-05 1969-02-05

Publications (1)

Publication Number Publication Date
BE745547A true BE745547A (fr) 1970-07-16

Family

ID=25169041

Family Applications (1)

Application Number Title Priority Date Filing Date
BE745547D BE745547A (fr) 1969-02-05 1970-02-05 Dispositif pour commander l'echelonnement sequentiel d'instructions dans un systeme de traitement d'informations.

Country Status (6)

Country Link
US (1) US3611306A (fr)
BE (1) BE745547A (fr)
CA (1) CA933665A (fr)
DE (1) DE2004886A1 (fr)
FR (1) FR2031265A5 (fr)
GB (1) GB1302513A (fr)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3678463A (en) * 1970-04-27 1972-07-18 Bell Telephone Labor Inc Controlled pause in data processing appartus
US3678464A (en) * 1970-06-29 1972-07-18 Bell Telephone Labor Inc Controlled pause and restart of magnetic disc memories and the like
US3781814A (en) * 1971-10-07 1973-12-25 Raytheon Co Method and apparatus for applying source language statements to a digital computer
US4156903A (en) * 1974-02-28 1979-05-29 Burroughs Corporation Data driven digital data processor
US3934232A (en) * 1974-04-25 1976-01-20 Honeywell Information Systems, Inc. Interprocessor communication apparatus for a data processing system
US4197589A (en) * 1977-12-05 1980-04-08 Texas Instruments Incorporated Operation sequencing mechanism
US4847755A (en) * 1985-10-31 1989-07-11 Mcc Development, Ltd. Parallel processing method and apparatus for increasing processing throughout by parallel processing low level instructions having natural concurrencies
US5021945A (en) * 1985-10-31 1991-06-04 Mcc Development, Ltd. Parallel processor system for processing natural concurrencies and method therefor
US4833599A (en) * 1987-04-20 1989-05-23 Multiflow Computer, Inc. Hierarchical priority branch handling for parallel execution in a parallel processor
US5159686A (en) * 1988-02-29 1992-10-27 Convex Computer Corporation Multi-processor computer system having process-independent communication register addressing
US5050070A (en) * 1988-02-29 1991-09-17 Convex Computer Corporation Multi-processor computer system having self-allocating processors
EP0422310A1 (fr) * 1989-10-10 1991-04-17 International Business Machines Corporation Méchanisme distribué pour la planification rapide d' objets partagés
US5263169A (en) * 1989-11-03 1993-11-16 Zoran Corporation Bus arbitration and resource management for concurrent vector signal processor architecture
US5214763A (en) * 1990-05-10 1993-05-25 International Business Machines Corporation Digital computer system capable of processing two or more instructions in parallel and having a coche and instruction compounding mechanism
EP0454985B1 (fr) * 1990-05-04 1996-12-18 International Business Machines Corporation Architecture de machine pour un jeu échelonnable d'instructions combinées
US5163139A (en) * 1990-08-29 1992-11-10 Hitachi America, Ltd. Instruction preprocessor for conditionally combining short memory instructions into virtual long instructions
DE69129569T2 (de) * 1990-09-05 1999-02-04 Philips Electronics N.V., Eindhoven Maschine mit sehr langem Befehlswort für leistungsfähige Durchführung von Programmen mit bedingten Verzweigungen
KR0176263B1 (ko) * 1991-03-11 1999-05-15 마이클 에이치. 모리스 비용기준 발견적 명령스케쥴링을 최적화하기 위한 방법 및 장치
US5673409A (en) * 1993-03-31 1997-09-30 Vlsi Technology, Inc. Self-defining instruction size
US5481743A (en) * 1993-09-30 1996-01-02 Apple Computer, Inc. Minimal instruction set computer architecture and multiple instruction issue method
US20020107903A1 (en) * 2000-11-07 2002-08-08 Richter Roger K. Methods and systems for the order serialization of information in a network processing environment
JP7087585B2 (ja) * 2018-03-30 2022-06-21 日本電気株式会社 情報処理装置、制御方法、及びプログラム

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3229260A (en) * 1962-03-02 1966-01-11 Ibm Multiprocessing computer system
US3346851A (en) * 1964-07-08 1967-10-10 Control Data Corp Simultaneous multiprocessing computer system
US3343135A (en) * 1964-08-13 1967-09-19 Ibm Compiling circuitry for a highly-parallel computing system
US3391390A (en) * 1964-09-09 1968-07-02 Bell Telephone Labor Inc Information storage and processing system utilizing associative memory
US3440611A (en) * 1966-01-14 1969-04-22 Ibm Parallel operations in a vector arithmetic computing system
US3470540A (en) * 1967-04-24 1969-09-30 Rca Corp Multiprocessing computer system with special instruction sequencing

Also Published As

Publication number Publication date
CA933665A (en) 1973-09-11
US3611306A (en) 1971-10-05
GB1302513A (fr) 1973-01-10
DE2004886A1 (de) 1970-11-05
FR2031265A5 (fr) 1970-11-13

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