BE647011A - Dispositifs à semi-conducteur dits tecnetrons pour redressement commandé et limitation de forts courants électriques - Google Patents

Dispositifs à semi-conducteur dits tecnetrons pour redressement commandé et limitation de forts courants électriques

Info

Publication number
BE647011A
BE647011A BE647011A BE647011A BE647011A BE 647011 A BE647011 A BE 647011A BE 647011 A BE647011 A BE 647011A BE 647011 A BE647011 A BE 647011A BE 647011 A BE647011 A BE 647011A
Authority
BE
Belgium
Prior art keywords
emi
tecnetrons
limitation
semiconductor devices
electric currents
Prior art date
Application number
BE647011A
Other languages
English (en)
Inventor
Stanislas Teszner
Original Assignee
Forges Et Ateliers De Constructions Electriques De Jeumont
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Forges Et Ateliers De Constructions Electriques De Jeumont filed Critical Forges Et Ateliers De Constructions Electriques De Jeumont
Publication of BE647011A publication Critical patent/BE647011A/fr

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/045Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads having an insulating passage through the base
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • H01L23/3672Foil-like cooling fins or heat sinks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/80Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4823Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a pin of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01327Intermediate phases, i.e. intermetallics compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description


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 <EMI ID=8.1>  franchement extrinsèque" 

  
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, ' tour de courant.

  
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l'état dit passant ou le dispositif doit être rendu le plus

  
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semiconducteur s'apparente à celui d'un amplificateur bloque, au contraire, à l'état passant il en diffère totalement.

  
La conciliation de ces caractéristiques apparemment contra*-,

  
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 <EMI ID=19.1>   <EMI ID=20.1>   <EMI ID=21.1> 

  
*MO<t  <EMI ID=22.1> 

  
type n), le contact de l'extrémité opposée constituant une

  
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service du dispositif.

  
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 <EMI ID=29.1> 

  
rant de service nominal*

  
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d'assurer une diffusion des porteurs minoritaires dans  <EMI ID=31.1>   <EMI ID=32.1> 

  
bande interdite fournit en môme tempe la liait" supérieur"

  
 <EMI ID=33.1> 

  
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largeur de la banda interdite puisque la limite supérieure de résistivité fixe la limite inférieure du produit du

  
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de porteurs. Corne d'autre part, le nombre de porteurs est  <EMI ID=36.1> 

  
trou 

  
Cependant* l'énonce des limite* donné ci-dessus est

  
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 <EMI ID=42.1>  diode de goulot en toute sécurité. Or, pour une tension

  
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Autant une constante. 

  
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Dans le cas d'un semi-conducteur riche en porte=*$ aine-

  
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attirée sont éliminés et avec eux, en nombre égal, des porteurs

  
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inférieur au délai de régénération de ces porteurs , que la

  
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 <EMI ID=55.1> 

  

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précis à titre d'exemple 

  
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tien des porteurs minoritaires par le champ longitudinal et  <EMI ID=61.1> 

  

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 <EMI ID=64.1> 

  

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On constate qu'on ne gagne ici aucunement sur la valeur

  
 <EMI ID=68.1> 

  
 <EMI ID=69.1> 

  
l'emploi d'un. telle substance avec une injection de porteurs minoritaires, au moins par l'une des électrodes terminales si éventuellement aussi par la diode de goulots 

  
 <EMI ID=70.1> 

  
est au contraire faible vis-à-vis du délai de leur élimination, la conductivité sera régie par la relation (5). Or, le rayon r sera toujours fourni par la relation (8), puisque l'injection de porteurs minoritaires doit disparaître à

  
 <EMI ID=71.1> 

  
la valeur de la résistance l'expression suivante 

  

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ainsi réalisé est 
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  <EMI ID=76.1> 

  
 <EMI ID=77.1> 

  
 <EMI ID=78.1> 

  
Il est bien entendu qu'une nouvelle réduction de la

  
 <EMI ID=79.1> 

  
nombre de porteurs minoritaires au-delà de l'état normal

  
 <EMI ID=80.1> 

  
d'injection de porteurs soit élevé et que d'autre parti leur

  
 <EMI ID=81.1> 

  
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 <EMI ID=83.1> 

  
goulot.

  
La réalisation des contacts d'extrémité répondant au schéma équivalent d'une diode shuntée par une résistance non-* linéaire, schéma représenté par la Pigé 4; peut être obtenue

  
 <EMI ID=84.1> 

  
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Les surfaces terminales sont d'abord traitées dans un

  
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 <EMI ID=87.1> 

  
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On produit de la aorte en surface une couche d'oxyde

  
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 <EMI ID=92.1> 

  
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composante essentiels le plomb et l'étain, et et, opérant à

  
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de la couche d'oxyde, qui assurent le fonctionnement du

  
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de connexion métallique soudée*

  
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 <EMI ID=103.1> 

  
titre simplement indicatif une relation entre

  
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 <EMI ID=105.1> 

  
de diffusion des porteur$ minoritaires de la substance   <EMI ID=106.1>   <EMI ID=107.1>  

  
 <EMI ID=108.1>  formée par 1'embase avec la pluralité des bâtonnets qui en

  
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usinage par ultra-sono" On procède alors à l'étamage de la face libre de l'embase, après quoi la structure est soumise

  
 <EMI ID=110.1> 

  
 <EMI ID=111.1> 

  
 <EMI ID=112.1> 

  
 <EMI ID=113.1> 

  
Ensuite la structure coiffée d'une grille 16 en indium et placée sur une plaquette métallique 19 *et mise tans, un

  
 <EMI ID=114.1> 

  
l'alliage indium-germanium, A cet effet elle cet portée pro-

  
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tous

  
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 <EMI ID=132.1> 

  
toutes considérations égale$ d'ailleurs$ une tension inverse

  
 <EMI ID=133.1>   <EMI ID=134.1> 

Claims (1)

  1. <EMI ID=135.1> <EMI ID=136.1>
    d'où il résulte une injection de porteurs de charge minori-
    <EMI ID=137.1>
    <EMI ID=138.1>
    quel que soit le mono de passage du courant"
    <EMI ID=139.1>
    <EMI ID=140.1>
    <EMI ID=141.1>
    <EMI ID=142.1>
    minoritaires par la partie du goulot polarisés dans le sens
    <EMI ID=143.1>
    <EMI ID=144.1>
    proche de l'intrinsèque avec une bande interdite d'une lar-
    <EMI ID=145.1>
    <EMI ID=146.1>
    <EMI ID=147.1>
    <EMI ID=148.1>
    <EMI ID=149.1>
    <EMI ID=150.1>
BE647011A 1957-11-30 1964-04-23 Dispositifs à semi-conducteur dits tecnetrons pour redressement commandé et limitation de forts courants électriques BE647011A (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR752813A FR72535E (fr) 1957-11-30 1957-11-30 Dispositif à semi-conducteur dit transistron unipolaire de puissance
FR867727A FR1301942A (fr) 1957-11-30 1961-07-11 Dispositifs à semi-conducteur dits tecnetrons pour redressement commandé et limitation de forts courants électriques

Publications (1)

Publication Number Publication Date
BE647011A true BE647011A (fr) 1964-05-13

Family

ID=74668069

Family Applications (2)

Application Number Title Priority Date Filing Date
BE647011A BE647011A (fr) 1957-11-30 1964-04-23 Dispositifs à semi-conducteur dits tecnetrons pour redressement commandé et limitation de forts courants électriques
BE655057A BE655057Q (fr) 1957-11-30 1964-10-30 Transistor de puissance à effet de champ

Family Applications After (1)

Application Number Title Priority Date Filing Date
BE655057A BE655057Q (fr) 1957-11-30 1964-10-30 Transistor de puissance à effet de champ

Country Status (3)

Country Link
BE (2) BE647011A (fr)
FR (3) FR1163241A (fr)
NL (2) NL101320C (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1129625B (de) * 1958-05-23 1962-05-17 Telefunken Patent Drifttransistor, bei dem der spezifische Widerstand in der Basiszone von der Emitter-zur Kollektorzone zunimmt
US3044909A (en) * 1958-10-23 1962-07-17 Shockley William Semiconductive wafer and method of making the same
DE1114939B (de) * 1960-02-09 1961-10-12 Intermetall Verfahren zur gleichzeitigen Herstellung mehrerer flaechenhafter Halbleiteranordnungen
NL123575C (fr) * 1960-04-01
US3281699A (en) * 1963-02-25 1966-10-25 Rca Corp Insulated-gate field-effect transistor oscillator circuits

Also Published As

Publication number Publication date
FR1163241A (fr) 1958-09-23
FR1301942A (fr) 1962-08-24
FR72535E (fr) 1960-04-14
BE655057Q (fr) 1965-02-15
NL223101A (fr) 1900-01-01
NL101320C (nl) 1962-05-15

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